diff options
| author | Paul Mackerras <paulus@ozlabs.org> | 2018-03-20 08:46:12 +1100 |
|---|---|---|
| committer | Michael Ellerman <mpe@ellerman.id.au> | 2018-03-24 00:38:00 +1100 |
| commit | dd0efb3f11cc0adcb4caa192ba09ad802d1fa6c0 (patch) | |
| tree | 81d298d24de0901b20c2c46e02c345c50285fcd9 /arch/powerpc/include/asm/cputable.h | |
| parent | c0d64cf9fefd58831ce2cc81b2683bfff3760f7a (diff) | |
| download | talos-op-linux-dd0efb3f11cc0adcb4caa192ba09ad802d1fa6c0.tar.gz talos-op-linux-dd0efb3f11cc0adcb4caa192ba09ad802d1fa6c0.zip | |
powerpc: Book E: Remove unused CPU_FTR_L2CSR bit
The CPU_FTR_L2CSR bit is never tested anywhere, so let's reclaim the
bit.
The last usage was removed in 86d63363defc ("powerpc/e500mc: Remove
dead L2 flushing code in idle_e500.S") (Jun 2015).
Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Diffstat (limited to 'arch/powerpc/include/asm/cputable.h')
| -rw-r--r-- | arch/powerpc/include/asm/cputable.h | 7 |
1 files changed, 3 insertions, 4 deletions
diff --git a/arch/powerpc/include/asm/cputable.h b/arch/powerpc/include/asm/cputable.h index 052db187805e..761b99c3dfad 100644 --- a/arch/powerpc/include/asm/cputable.h +++ b/arch/powerpc/include/asm/cputable.h @@ -139,7 +139,6 @@ static inline void cpu_feature_keys_init(void) { } #define CPU_FTR_TAU ASM_CONST(0x00000010) #define CPU_FTR_CAN_DOZE ASM_CONST(0x00000020) #define CPU_FTR_USE_RTC ASM_CONST(0x00000040) -#define CPU_FTR_L2CSR ASM_CONST(0x00000080) #define CPU_FTR_601 ASM_CONST(0x00000100) #define CPU_FTR_DBELL ASM_CONST(0x00000200) #define CPU_FTR_CAN_NAP ASM_CONST(0x00000400) @@ -385,18 +384,18 @@ static inline void cpu_feature_keys_init(void) { } CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | \ CPU_FTR_NODSISRALIGN | CPU_FTR_NOEXECUTE) #define CPU_FTRS_E500MC (CPU_FTR_NODSISRALIGN | \ - CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ + CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ CPU_FTR_DBELL | CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV) /* * e5500/e6500 erratum A-006958 is a timebase bug that can use the * same workaround as CPU_FTR_CELL_TB_BUG. */ #define CPU_FTRS_E5500 (CPU_FTR_NODSISRALIGN | \ - CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ + CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_CELL_TB_BUG) #define CPU_FTRS_E6500 (CPU_FTR_NODSISRALIGN | \ - CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ + CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \ CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \ CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP | \ CPU_FTR_CELL_TB_BUG | CPU_FTR_SMT) |
