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authorLinus Torvalds <torvalds@linux-foundation.org>2010-02-27 16:19:22 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2010-02-27 16:19:22 -0800
commitf1dd6ad599732fc89f36fdd65a2c2cf3c63a8711 (patch)
tree5092207128e47cba99dc0fe373fff6a36f4cb4b8 /arch/mips/sni/rm200.c
parent8d37a371b6869920e6c40c495c68eabba1ef3909 (diff)
parente10b234b3c4e255d3300a486c4ac15b43253ac6d (diff)
downloadtalos-op-linux-f1dd6ad599732fc89f36fdd65a2c2cf3c63a8711.tar.gz
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Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (141 commits) MIPS: Alchemy: defconfig updates MIPS: Alchemy: Fix Au1100 ethernet build failure MIPS: Alchemy: Repair db1500/bosporus builds MIPS: ARC: Cleanup unused definitions from sgialib.h MIPS: Cobalt: convert legacy port addresses to GT-64111 bus addresses MIPS: Alchemy: use 36bit addresses for PCMCIA resources. MIPS: Cobalt: Fix theoretical port aliasing issue MIPS: Use ALIGN(x, bytes) instead of __ALIGN_MASK(x, bytes - 1) MIPS: Crazy spinlock speed test. MIPS: Optimize spinlocks. MIPS: Alchemy: devboard PM needs to save CPLD registers. MIPS: PowerTV: Eliminate duplicate opcode definition macros MIPS: Lemote 2F: Move printks out of port_access_lock. MIPS: PNX833x: Convert IRQ controller locks to raw spinlocks. MIPS: Octeon: Replace spinlock with raw_spinlocks in dma-octeon.c. MIPS: Octeon: Replace rwlocks in irq_chip handlers with raw_spinlocks. MIPS: Octeon: Convert octeon_irq_msi_lock to raw spinlock. MIPS: Loongson: Remove pointless sample_lock from oprofile code. MIPS: SNI: Convert sni_rm200_i8259A_lock to raw spinlock. MIPS: i8259: Convert IRQ controller lock to raw spinlock. ...
Diffstat (limited to 'arch/mips/sni/rm200.c')
-rw-r--r--arch/mips/sni/rm200.c22
1 files changed, 11 insertions, 11 deletions
diff --git a/arch/mips/sni/rm200.c b/arch/mips/sni/rm200.c
index 31e2583ec622..90c558f7c0fa 100644
--- a/arch/mips/sni/rm200.c
+++ b/arch/mips/sni/rm200.c
@@ -132,7 +132,7 @@ device_initcall(snirm_setup_devinit);
* readb/writeb to access them
*/
-DEFINE_SPINLOCK(sni_rm200_i8259A_lock);
+static DEFINE_RAW_SPINLOCK(sni_rm200_i8259A_lock);
#define PIC_CMD 0x00
#define PIC_IMR 0x01
#define PIC_ISR PIC_CMD
@@ -161,13 +161,13 @@ static void sni_rm200_disable_8259A_irq(unsigned int irq)
irq -= RM200_I8259A_IRQ_BASE;
mask = 1 << irq;
- spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
+ raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
rm200_cached_irq_mask |= mask;
if (irq & 8)
writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
else
writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
- spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
+ raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
}
static void sni_rm200_enable_8259A_irq(unsigned int irq)
@@ -177,13 +177,13 @@ static void sni_rm200_enable_8259A_irq(unsigned int irq)
irq -= RM200_I8259A_IRQ_BASE;
mask = ~(1 << irq);
- spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
+ raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
rm200_cached_irq_mask &= mask;
if (irq & 8)
writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
else
writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
- spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
+ raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
}
static inline int sni_rm200_i8259A_irq_real(unsigned int irq)
@@ -216,7 +216,7 @@ void sni_rm200_mask_and_ack_8259A(unsigned int irq)
irq -= RM200_I8259A_IRQ_BASE;
irqmask = 1 << irq;
- spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
+ raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
/*
* Lightweight spurious IRQ detection. We do not want
* to overdo spurious IRQ handling - it's usually a sign
@@ -247,7 +247,7 @@ handle_real_irq:
writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
writeb(0x60+irq, rm200_pic_master + PIC_CMD);
}
- spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
+ raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
return;
spurious_8259A_irq:
@@ -298,7 +298,7 @@ static inline int sni_rm200_i8259_irq(void)
{
int irq;
- spin_lock(&sni_rm200_i8259A_lock);
+ raw_spin_lock(&sni_rm200_i8259A_lock);
/* Perform an interrupt acknowledge cycle on controller 1. */
writeb(0x0C, rm200_pic_master + PIC_CMD); /* prepare for poll */
@@ -325,7 +325,7 @@ static inline int sni_rm200_i8259_irq(void)
irq = -1;
}
- spin_unlock(&sni_rm200_i8259A_lock);
+ raw_spin_unlock(&sni_rm200_i8259A_lock);
return likely(irq >= 0) ? irq + RM200_I8259A_IRQ_BASE : irq;
}
@@ -334,7 +334,7 @@ void sni_rm200_init_8259A(void)
{
unsigned long flags;
- spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
+ raw_spin_lock_irqsave(&sni_rm200_i8259A_lock, flags);
writeb(0xff, rm200_pic_master + PIC_IMR);
writeb(0xff, rm200_pic_slave + PIC_IMR);
@@ -352,7 +352,7 @@ void sni_rm200_init_8259A(void)
writeb(cached_master_mask, rm200_pic_master + PIC_IMR);
writeb(cached_slave_mask, rm200_pic_slave + PIC_IMR);
- spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
+ raw_spin_unlock_irqrestore(&sni_rm200_i8259A_lock, flags);
}
/*
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