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| author | Jaecheol Lee <jc.lee@samsung.com> | 2012-02-02 12:31:01 +0900 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2012-03-10 22:30:27 -0800 |
| commit | d074de8ef5a8b241c129690014138fcadcd72bc4 (patch) | |
| tree | 9ea95f87e3f4cc63acb71dd18fe1ac29759da22b /arch/arm | |
| parent | a2b9676db08b3be717af16e333396a97eeee1745 (diff) | |
| download | talos-op-linux-d074de8ef5a8b241c129690014138fcadcd72bc4.tar.gz talos-op-linux-d074de8ef5a8b241c129690014138fcadcd72bc4.zip | |
ARM: EXYNOS: add clock registers for exynos4x12-cpufreq
Signed-off-by: Jaecheol Lee <jc.lee@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Diffstat (limited to 'arch/arm')
| -rw-r--r-- | arch/arm/mach-exynos/include/mach/regs-clock.h | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-exynos/include/mach/regs-clock.h b/arch/arm/mach-exynos/include/mach/regs-clock.h index 790f525d1557..b1a2aeb256fe 100644 --- a/arch/arm/mach-exynos/include/mach/regs-clock.h +++ b/arch/arm/mach-exynos/include/mach/regs-clock.h @@ -160,6 +160,15 @@ #define EXYNOS4_CLKDIV_CPU0_PCLKDBG_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_PCLKDBG_SHIFT) #define EXYNOS4_CLKDIV_CPU0_APLL_SHIFT (24) #define EXYNOS4_CLKDIV_CPU0_APLL_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_APLL_SHIFT) +#define EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT 28 +#define EXYNOS4_CLKDIV_CPU0_CORE2_MASK (0x7 << EXYNOS4_CLKDIV_CPU0_CORE2_SHIFT) + +#define EXYNOS4_CLKDIV_CPU1_COPY_SHIFT 0 +#define EXYNOS4_CLKDIV_CPU1_COPY_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_COPY_SHIFT) +#define EXYNOS4_CLKDIV_CPU1_HPM_SHIFT 4 +#define EXYNOS4_CLKDIV_CPU1_HPM_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_HPM_SHIFT) +#define EXYNOS4_CLKDIV_CPU1_CORES_SHIFT 8 +#define EXYNOS4_CLKDIV_CPU1_CORES_MASK (0x7 << EXYNOS4_CLKDIV_CPU1_CORES_SHIFT) #define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) #define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) |
