Merge tag 'tegra-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra into tegra/soc

From: Olof Johansson <olof@lixom.net>

SoC new development for tegra SoCs, mostly tegra30 core support.

It also includes one stray bugfix that was misapplied (should have been
in soc-drivers), but it went out to the stable branches before I noticed
so I've left it in.

* tag 'tegra-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/olof/tegra:
  ARM: tegra: Demote EMC clock inconsistency BUG to WARN
  ARM: tegra: Avoid compiling cpuidle code when not configured
  ARM: tegra: cpuidle driver for tegra
  ARM: tegra: assembler code for LP3
  ARM: tegra: definitions for flow controller
  ARM: tegra: initialize basic system clocks
  ARM: tegra: enable tegra30 clock framework
  ARM: tegra: implement basic tegra30 clock framework
  ARM: tegra: add support for new clock framework features
  ARM: tegra: add support for tegra30 interrupts

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

1 files changed, 25 insertions, 5 deletions

diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c
index ff9e6b6c0460..1976e934cdd9 100644
--- a/arch/arm/mach-tegra/tegra2_clocks.c
+++ b/arch/arm/mach-tegra/tegra2_clocks.c
@@ -1143,15 +1143,35 @@ static void tegra2_emc_clk_init(struct clk *c)
 
 static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate)
 {
-	long new_rate = rate;
+	long emc_rate;
+	long clk_rate;
 
-	new_rate = tegra_emc_round_rate(new_rate);
-	if (new_rate < 0)
+	/*
+	 * The slowest entry in the EMC clock table that is at least as
+	 * fast as rate.
+	 */
+	emc_rate = tegra_emc_round_rate(rate);
+	if (emc_rate < 0)
 		return c->max_rate;
 
-	BUG_ON(new_rate != tegra2_periph_clk_round_rate(c, new_rate));
+	/*
+	 * The fastest rate the PLL will generate that is at most the
+	 * requested rate.
+	 */
+	clk_rate = tegra2_periph_clk_round_rate(c, emc_rate);
+
+	/*
+	 * If this fails, and emc_rate > clk_rate, it's because the maximum
+	 * rate in the EMC tables is larger than the maximum rate of the EMC
+	 * clock. The EMC clock's max rate is the rate it was running when the
+	 * kernel booted. Such a mismatch is probably due to using the wrong
+	 * BCT, i.e. using a Tegra20 BCT with an EMC table written for Tegra25.
+	 */
+	WARN_ONCE(emc_rate != clk_rate,
+		"emc_rate %ld != clk_rate %ld",
+		emc_rate, clk_rate);
 
-	return new_rate;
+	return emc_rate;
 }
 
 static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate)