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| author | Linus Torvalds <torvalds@linux-foundation.org> | 2017-09-12 06:10:44 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2017-09-12 06:10:44 -0700 |
| commit | 8fac2f96ab86b0e14ec4e42851e21e9b518bdc55 (patch) | |
| tree | f7d45eb60cf6075f90263d9d2eaa796ce6c616b6 /arch/arm/mach-rockchip | |
| parent | 260d16580db018e3faeb1992c70c13bf00e726b8 (diff) | |
| parent | e558bdc21ae1f0db520eccd84015e17d8a589973 (diff) | |
| download | talos-op-linux-8fac2f96ab86b0e14ec4e42851e21e9b518bdc55.tar.gz talos-op-linux-8fac2f96ab86b0e14ec4e42851e21e9b518bdc55.zip | |
Merge branch 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm
Pull ARM updates from Russell King:
"Low priority fixes and updates for ARM:
- add some missing includes
- efficiency improvements in system call entry code when tracing is
enabled
- ensure ARMv6+ is always built as EABI
- export save_stack_trace_tsk()
- fix fatal signal handling during mm fault
- build translation table base address register from scratch
- appropriately align the .data section to a word boundary where we
rely on that data being word aligned"
* 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-arm:
ARM: 8691/1: Export save_stack_trace_tsk()
ARM: 8692/1: mm: abort uaccess retries upon fatal signal
ARM: 8690/1: lpae: build TTB control register value from scratch in v7_ttb_setup
ARM: align .data section
ARM: always enable AEABI for ARMv6+
ARM: avoid saving and restoring registers unnecessarily
ARM: move PC value into r9
ARM: obtain thread info structure later
ARM: use aliases for registers in entry-common
ARM: 8689/1: scu: add missing errno include
ARM: 8688/1: pm: add missing types include
Diffstat (limited to 'arch/arm/mach-rockchip')
| -rw-r--r-- | arch/arm/mach-rockchip/sleep.S | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-rockchip/sleep.S b/arch/arm/mach-rockchip/sleep.S index 2eec9a341f05..9927f06f52fe 100644 --- a/arch/arm/mach-rockchip/sleep.S +++ b/arch/arm/mach-rockchip/sleep.S @@ -23,7 +23,7 @@ * ddr to sram for system resumeing. * so it is ".data section". */ -.align + .align 2 ENTRY(rockchip_slp_cpu_resume) setmode PSR_I_BIT | PSR_F_BIT | SVC_MODE, r1 @ set svc, irqs off |
