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| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2009-03-19 12:39:58 +0000 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-03-19 12:39:58 +0000 |
| commit | 14b6848bc0134b8838d374c423df3edda9b1490e (patch) | |
| tree | 724dc912efe84f432d33a798502811c5f5295774 /arch/arm/mach-omap2/cm-regbits-34xx.h | |
| parent | 05d9881bc4c6f172997b7a59e4a1a95910c4ebd7 (diff) | |
| parent | 4da3782151300237db3abe070f716922889252e0 (diff) | |
| download | talos-op-linux-14b6848bc0134b8838d374c423df3edda9b1490e.tar.gz talos-op-linux-14b6848bc0134b8838d374c423df3edda9b1490e.zip | |
Merge branch 'omap-clks3' into devel
Conflicts:
arch/arm/mach-omap2/clock.c
Diffstat (limited to 'arch/arm/mach-omap2/cm-regbits-34xx.h')
| -rw-r--r-- | arch/arm/mach-omap2/cm-regbits-34xx.h | 121 |
1 files changed, 92 insertions, 29 deletions
diff --git a/arch/arm/mach-omap2/cm-regbits-34xx.h b/arch/arm/mach-omap2/cm-regbits-34xx.h index 219f5c8d9659..6f3f5a36aae6 100644 --- a/arch/arm/mach-omap2/cm-regbits-34xx.h +++ b/arch/arm/mach-omap2/cm-regbits-34xx.h @@ -183,31 +183,58 @@ #define OMAP3430ES2_EN_CPEFUSE_MASK (1 << 0) /* CM_IDLEST1_CORE specific bits */ -#define OMAP3430_ST_ICR (1 << 29) -#define OMAP3430_ST_AES2 (1 << 28) -#define OMAP3430_ST_SHA12 (1 << 27) -#define OMAP3430_ST_DES2 (1 << 26) -#define OMAP3430_ST_MSPRO (1 << 23) -#define OMAP3430_ST_HDQ (1 << 22) -#define OMAP3430ES1_ST_FAC (1 << 8) -#define OMAP3430ES1_ST_MAILBOXES (1 << 7) -#define OMAP3430_ST_OMAPCTRL (1 << 6) -#define OMAP3430_ST_SDMA (1 << 2) -#define OMAP3430_ST_SDRC (1 << 1) -#define OMAP3430_ST_SSI (1 << 0) +#define OMAP3430ES2_ST_MMC3_SHIFT 30 +#define OMAP3430ES2_ST_MMC3_MASK (1 << 30) +#define OMAP3430_ST_ICR_SHIFT 29 +#define OMAP3430_ST_ICR_MASK (1 << 29) +#define OMAP3430_ST_AES2_SHIFT 28 +#define OMAP3430_ST_AES2_MASK (1 << 28) +#define OMAP3430_ST_SHA12_SHIFT 27 +#define OMAP3430_ST_SHA12_MASK (1 << 27) +#define OMAP3430_ST_DES2_SHIFT 26 +#define OMAP3430_ST_DES2_MASK (1 << 26) +#define OMAP3430_ST_MSPRO_SHIFT 23 +#define OMAP3430_ST_MSPRO_MASK (1 << 23) +#define OMAP3430_ST_HDQ_SHIFT 22 +#define OMAP3430_ST_HDQ_MASK (1 << 22) +#define OMAP3430ES1_ST_FAC_SHIFT 8 +#define OMAP3430ES1_ST_FAC_MASK (1 << 8) +#define OMAP3430ES2_ST_SSI_IDLE_SHIFT 8 +#define OMAP3430ES2_ST_SSI_IDLE_MASK (1 << 8) +#define OMAP3430_ST_MAILBOXES_SHIFT 7 +#define OMAP3430_ST_MAILBOXES_MASK (1 << 7) +#define OMAP3430_ST_OMAPCTRL_SHIFT 6 +#define OMAP3430_ST_OMAPCTRL_MASK (1 << 6) +#define OMAP3430_ST_SDMA_SHIFT 2 +#define OMAP3430_ST_SDMA_MASK (1 << 2) +#define OMAP3430_ST_SDRC_SHIFT 1 +#define OMAP3430_ST_SDRC_MASK (1 << 1) +#define OMAP3430_ST_SSI_STDBY_SHIFT 0 +#define OMAP3430_ST_SSI_STDBY_MASK (1 << 0) /* CM_IDLEST2_CORE */ -#define OMAP3430_ST_PKA (1 << 4) -#define OMAP3430_ST_AES1 (1 << 3) -#define OMAP3430_ST_RNG (1 << 2) -#define OMAP3430_ST_SHA11 (1 << 1) -#define OMAP3430_ST_DES1 (1 << 0) +#define OMAP3430_ST_PKA_SHIFT 4 +#define OMAP3430_ST_PKA_MASK (1 << 4) +#define OMAP3430_ST_AES1_SHIFT 3 +#define OMAP3430_ST_AES1_MASK (1 << 3) +#define OMAP3430_ST_RNG_SHIFT 2 +#define OMAP3430_ST_RNG_MASK (1 << 2) +#define OMAP3430_ST_SHA11_SHIFT 1 +#define OMAP3430_ST_SHA11_MASK (1 << 1) +#define OMAP3430_ST_DES1_SHIFT 0 +#define OMAP3430_ST_DES1_MASK (1 << 0) /* CM_IDLEST3_CORE */ #define OMAP3430ES2_ST_USBTLL_SHIFT 2 #define OMAP3430ES2_ST_USBTLL_MASK (1 << 2) +#define OMAP3430ES2_ST_CPEFUSE_SHIFT 0 +#define OMAP3430ES2_ST_CPEFUSE_MASK (1 << 0) /* CM_AUTOIDLE1_CORE */ +#define OMAP3430ES2_AUTO_MMC3 (1 << 30) +#define OMAP3430ES2_AUTO_MMC3_SHIFT 30 +#define OMAP3430ES2_AUTO_ICR (1 << 29) +#define OMAP3430ES2_AUTO_ICR_SHIFT 29 #define OMAP3430_AUTO_AES2 (1 << 28) #define OMAP3430_AUTO_AES2_SHIFT 28 #define OMAP3430_AUTO_SHA12 (1 << 27) @@ -276,6 +303,9 @@ #define OMAP3430_AUTO_DES1_SHIFT 0 /* CM_AUTOIDLE3_CORE */ +#define OMAP3430ES2_AUTO_USBHOST (1 << 0) +#define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 +#define OMAP3430ES2_AUTO_USBTLL (1 << 2) #define OMAP3430ES2_AUTO_USBTLL_SHIFT 2 #define OMAP3430ES2_AUTO_USBTLL_MASK (1 << 2) @@ -332,8 +362,12 @@ #define OMAP3430ES1_CLKACTIVITY_GFX_MASK (1 << 0) /* CM_FCLKEN_SGX */ -#define OMAP3430ES2_EN_SGX_SHIFT 1 -#define OMAP3430ES2_EN_SGX_MASK (1 << 1) +#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_SHIFT 1 +#define OMAP3430ES2_CM_FCLKEN_SGX_EN_SGX_MASK (1 << 1) + +/* CM_ICLKEN_SGX */ +#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_SHIFT 0 +#define OMAP3430ES2_CM_ICLKEN_SGX_EN_SGX_MASK (1 << 0) /* CM_CLKSEL_SGX */ #define OMAP3430ES2_CLKSEL_SGX_SHIFT 0 @@ -349,6 +383,7 @@ /* CM_FCLKEN_WKUP specific bits */ #define OMAP3430ES2_EN_USIMOCP_SHIFT 9 +#define OMAP3430ES2_EN_USIMOCP_MASK (1 << 9) /* CM_ICLKEN_WKUP specific bits */ #define OMAP3430_EN_WDT1 (1 << 4) @@ -357,11 +392,18 @@ #define OMAP3430_EN_32KSYNC_SHIFT 2 /* CM_IDLEST_WKUP specific bits */ -#define OMAP3430_ST_WDT2 (1 << 5) -#define OMAP3430_ST_WDT1 (1 << 4) -#define OMAP3430_ST_32KSYNC (1 << 2) +#define OMAP3430ES2_ST_USIMOCP_SHIFT 9 +#define OMAP3430ES2_ST_USIMOCP_MASK (1 << 9) +#define OMAP3430_ST_WDT2_SHIFT 5 +#define OMAP3430_ST_WDT2_MASK (1 << 5) +#define OMAP3430_ST_WDT1_SHIFT 4 +#define OMAP3430_ST_WDT1_MASK (1 << 4) +#define OMAP3430_ST_32KSYNC_SHIFT 2 +#define OMAP3430_ST_32KSYNC_MASK (1 << 2) /* CM_AUTOIDLE_WKUP */ +#define OMAP3430ES2_AUTO_USIMOCP (1 << 9) +#define OMAP3430ES2_AUTO_USIMOCP_SHIFT 9 #define OMAP3430_AUTO_WDT2 (1 << 5) #define OMAP3430_AUTO_WDT2_SHIFT 5 #define OMAP3430_AUTO_WDT1 (1 << 4) @@ -426,6 +468,8 @@ #define OMAP3430_ST_CORE_CLK_MASK (1 << 0) /* CM_IDLEST2_CKGEN */ +#define OMAP3430ES2_ST_USIM_CLK_SHIFT 2 +#define OMAP3430ES2_ST_USIM_CLK_MASK (1 << 2) #define OMAP3430ES2_ST_120M_CLK_SHIFT 1 #define OMAP3430ES2_ST_120M_CLK_MASK (1 << 1) #define OMAP3430ES2_ST_PERIPH2_CLK_SHIFT 0 @@ -449,8 +493,12 @@ #define OMAP3430_CORE_DPLL_MULT_MASK (0x7ff << 16) #define OMAP3430_CORE_DPLL_DIV_SHIFT 8 #define OMAP3430_CORE_DPLL_DIV_MASK (0x7f << 8) -#define OMAP3430_SOURCE_54M (1 << 5) -#define OMAP3430_SOURCE_48M (1 << 3) +#define OMAP3430_SOURCE_96M_SHIFT 6 +#define OMAP3430_SOURCE_96M_MASK (1 << 6) +#define OMAP3430_SOURCE_54M_SHIFT 5 +#define OMAP3430_SOURCE_54M_MASK (1 << 5) +#define OMAP3430_SOURCE_48M_SHIFT 3 +#define OMAP3430_SOURCE_48M_MASK (1 << 3) /* CM_CLKSEL2_PLL */ #define OMAP3430_PERIPH_DPLL_MULT_SHIFT 8 @@ -493,7 +541,12 @@ #define OMAP3430_CM_ICLKEN_DSS_EN_DSS_SHIFT 0 /* CM_IDLEST_DSS */ -#define OMAP3430_ST_DSS (1 << 0) +#define OMAP3430ES2_ST_DSS_IDLE_SHIFT 1 +#define OMAP3430ES2_ST_DSS_IDLE_MASK (1 << 1) +#define OMAP3430ES2_ST_DSS_STDBY_SHIFT 0 +#define OMAP3430ES2_ST_DSS_STDBY_MASK (1 << 0) +#define OMAP3430ES1_ST_DSS_SHIFT 0 +#define OMAP3430ES1_ST_DSS_MASK (1 << 0) /* CM_AUTOIDLE_DSS */ #define OMAP3430_AUTO_DSS (1 << 0) @@ -516,6 +569,8 @@ #define OMAP3430_CLKACTIVITY_DSS_MASK (1 << 0) /* CM_FCLKEN_CAM specific bits */ +#define OMAP3430_EN_CSI2 (1 << 1) +#define OMAP3430_EN_CSI2_SHIFT 1 /* CM_ICLKEN_CAM specific bits */ @@ -545,10 +600,14 @@ /* CM_ICLKEN_PER specific bits */ /* CM_IDLEST_PER */ -#define OMAP3430_ST_WDT3 (1 << 12) -#define OMAP3430_ST_MCBSP4 (1 << 2) -#define OMAP3430_ST_MCBSP3 (1 << 1) -#define OMAP3430_ST_MCBSP2 (1 << 0) +#define OMAP3430_ST_WDT3_SHIFT 12 +#define OMAP3430_ST_WDT3_MASK (1 << 12) +#define OMAP3430_ST_MCBSP4_SHIFT 2 +#define OMAP3430_ST_MCBSP4_MASK (1 << 2) +#define OMAP3430_ST_MCBSP3_SHIFT 1 +#define OMAP3430_ST_MCBSP3_MASK (1 << 1) +#define OMAP3430_ST_MCBSP2_SHIFT 0 +#define OMAP3430_ST_MCBSP2_MASK (1 << 0) /* CM_AUTOIDLE_PER */ #define OMAP3430_AUTO_GPIO6 (1 << 17) @@ -676,6 +735,10 @@ #define OMAP3430ES2_EN_USBHOST_MASK (1 << 0) /* CM_IDLEST_USBHOST */ +#define OMAP3430ES2_ST_USBHOST_IDLE_SHIFT 1 +#define OMAP3430ES2_ST_USBHOST_IDLE_MASK (1 << 1) +#define OMAP3430ES2_ST_USBHOST_STDBY_SHIFT 0 +#define OMAP3430ES2_ST_USBHOST_STDBY_MASK (1 << 0) /* CM_AUTOIDLE_USBHOST */ #define OMAP3430ES2_AUTO_USBHOST_SHIFT 0 |
