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| author | Arnd Bergmann <arnd@arndb.de> | 2015-01-30 10:45:33 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2015-12-01 21:52:50 +0100 |
| commit | d8b2823e950cd9634eb4a01f563ee55afb39d549 (patch) | |
| tree | f9999497cd91d54b312911939828e98c2f90ebe2 /arch/arm/mach-ks8695/regs-pci.h | |
| parent | 100f9638fe7c291641418e33d08ff9a5b77803ac (diff) | |
| download | talos-op-linux-d8b2823e950cd9634eb4a01f563ee55afb39d549.tar.gz talos-op-linux-d8b2823e950cd9634eb4a01f563ee55afb39d549.zip | |
ARM: ks8695: make headers more local
Some header files are never included outside of a mach-ks8695
directory and do not need to be made visible in include/mach,
so let's just move them all down one level.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Diffstat (limited to 'arch/arm/mach-ks8695/regs-pci.h')
| -rw-r--r-- | arch/arm/mach-ks8695/regs-pci.h | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/arch/arm/mach-ks8695/regs-pci.h b/arch/arm/mach-ks8695/regs-pci.h new file mode 100644 index 000000000000..75a9db6edbd9 --- /dev/null +++ b/arch/arm/mach-ks8695/regs-pci.h @@ -0,0 +1,53 @@ +/* + * arch/arm/mach-ks8695/include/mach/regs-pci.h + * + * Copyright (C) 2006 Ben Dooks <ben@simtec.co.uk> + * Copyright (C) 2006 Simtec Electronics + * + * KS8695 - PCI bridge registers and bit definitions. + * + * This file is licensed under the terms of the GNU General Public + * License version 2. This program is licensed "as is" without any + * warranty of any kind, whether express or implied. + */ + +#define KS8695_PCI_OFFSET (0xF0000 + 0x2000) +#define KS8695_PCI_VA (KS8695_IO_VA + KS8695_PCI_OFFSET) +#define KS8695_PCI_PA (KS8695_IO_PA + KS8695_PCI_OFFSET) + + +#define KS8695_CRCFID (0x000) /* Configuration: Identification */ +#define KS8695_CRCFCS (0x004) /* Configuration: Command and Status */ +#define KS8695_CRCFRV (0x008) /* Configuration: Revision */ +#define KS8695_CRCFLT (0x00C) /* Configuration: Latency Timer */ +#define KS8695_CRCBMA (0x010) /* Configuration: Base Memory Address */ +#define KS8695_CRCSID (0x02C) /* Configuration: Subsystem ID */ +#define KS8695_CRCFIT (0x03C) /* Configuration: Interrupt */ +#define KS8695_PBCA (0x100) /* Bridge Configuration Address */ +#define KS8695_PBCD (0x104) /* Bridge Configuration Data */ +#define KS8695_PBM (0x200) /* Bridge Mode */ +#define KS8695_PBCS (0x204) /* Bridge Control and Status */ +#define KS8695_PMBA (0x208) /* Bridge Memory Base Address */ +#define KS8695_PMBAC (0x20C) /* Bridge Memory Base Address Control */ +#define KS8695_PMBAM (0x210) /* Bridge Memory Base Address Mask */ +#define KS8695_PMBAT (0x214) /* Bridge Memory Base Address Translation */ +#define KS8695_PIOBA (0x218) /* Bridge I/O Base Address */ +#define KS8695_PIOBAC (0x21C) /* Bridge I/O Base Address Control */ +#define KS8695_PIOBAM (0x220) /* Bridge I/O Base Address Mask */ +#define KS8695_PIOBAT (0x224) /* Bridge I/O Base Address Translation */ + + +/* Configuration: Identification */ + +/* Configuration: Command and Status */ + +/* Configuration: Revision */ + + + +#define CFRV_GUEST (1 << 23) + +#define PBCA_TYPE1 (1) +#define PBCA_ENABLE (1 << 31) + + |
