diff options
| author | Shawn Guo <shawn.guo@linaro.org> | 2011-07-07 00:37:41 +0800 |
|---|---|---|
| committer | Grant Likely <grant.likely@secretlab.ca> | 2011-07-08 12:38:12 -0600 |
| commit | e7fc6ae7446710a487510d212137a43289bbe90e (patch) | |
| tree | 6f040b47a383ed19afe48521f449dc0081fa47de /arch/arm/mach-imx/mm-imx21.c | |
| parent | fb1492186276ba52d99b58121b8a9a87f20cc9f3 (diff) | |
| download | talos-op-linux-e7fc6ae7446710a487510d212137a43289bbe90e.tar.gz talos-op-linux-e7fc6ae7446710a487510d212137a43289bbe90e.zip | |
gpio/mxc: get rid of the uses of cpu_is_mx()
The patch removes all the uses of cpu_is_mx(). Instead, it utilizes
platform_device_id to distinguish the different gpio types, IMX1_GPIO
on i.mx1, IMX21_GPIO on i.mx21 and i.mx27, IMX31_GPIO on all other
i.mx SoCs.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Diffstat (limited to 'arch/arm/mach-imx/mm-imx21.c')
| -rw-r--r-- | arch/arm/mach-imx/mm-imx21.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/arch/arm/mach-imx/mm-imx21.c b/arch/arm/mach-imx/mm-imx21.c index f0fb8bcce6f9..6d7d518686a5 100644 --- a/arch/arm/mach-imx/mm-imx21.c +++ b/arch/arm/mach-imx/mm-imx21.c @@ -76,10 +76,10 @@ void __init mx21_init_irq(void) void __init imx21_soc_init(void) { - mxc_register_gpio(0, MX21_GPIO1_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0); - mxc_register_gpio(1, MX21_GPIO2_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0); - mxc_register_gpio(2, MX21_GPIO3_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0); - mxc_register_gpio(3, MX21_GPIO4_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0); - mxc_register_gpio(4, MX21_GPIO5_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0); - mxc_register_gpio(5, MX21_GPIO6_BASE_ADDR, SZ_4K, MX21_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio", 0, MX21_GPIO1_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio", 1, MX21_GPIO2_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio", 2, MX21_GPIO3_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio", 3, MX21_GPIO4_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio", 4, MX21_GPIO5_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); + mxc_register_gpio("imx21-gpio", 5, MX21_GPIO6_BASE_ADDR, SZ_256, MX21_INT_GPIO, 0); } |
