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author | Arnd Bergmann <arnd@arndb.de> | 2019-02-15 17:39:08 +0100 |
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committer | Arnd Bergmann <arnd@arndb.de> | 2019-02-15 20:38:14 +0100 |
commit | ad75174f39f4729ee08412bc1d653dfe21a50754 (patch) | |
tree | 8d55825c2fbe2cd1e9726183fe1d16d04afe4c06 /arch/arm/mach-imx/mach-imx7ulp.c | |
parent | e62538ff9a4bedae7c10dcfbb41a9b82531281e1 (diff) | |
parent | 84a2ab25b12d69914c96dd12e762f7ff912f9735 (diff) | |
download | talos-op-linux-ad75174f39f4729ee08412bc1d653dfe21a50754.tar.gz talos-op-linux-ad75174f39f4729ee08412bc1d653dfe21a50754.zip |
Merge tag 'imx-soc-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/fixes
i.MX SoC changes for 5.1:
- Support cpuidle for i.MX7ULP, states WFI, WAIT and STOP get added.
- Support SoC revision detecting for i.MX7ULP by reading JTAG_ID
register from SIM module.
- Select PM and GPCv2 irqchip driver options for i.MX8 support, as they
are essential for building an i.MX8 based system.
- Skip build of ssi-fiq code if SND_SOC_IMX_PCM_FIQ is not enabled.
* tag 'imx-soc-5.1' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
arm64: imx8mq: select PM support
arm64: imx8mq: select GPCv2 irqchip driver
ARM: imx: add i.MX7ULP SoC revision support
ARM: imx: add i.MX7ULP cpuidle support
ARM: imx: don't build ssi-fiq if not required
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Diffstat (limited to 'arch/arm/mach-imx/mach-imx7ulp.c')
-rw-r--r-- | arch/arm/mach-imx/mach-imx7ulp.c | 46 |
1 files changed, 46 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/mach-imx7ulp.c b/arch/arm/mach-imx/mach-imx7ulp.c index 33937ebf66b5..11ac71aaf965 100644 --- a/arch/arm/mach-imx/mach-imx7ulp.c +++ b/arch/arm/mach-imx/mach-imx7ulp.c @@ -6,17 +6,57 @@ */ #include <linux/irqchip.h> +#include <linux/mfd/syscon.h> #include <linux/of_platform.h> +#include <linux/regmap.h> #include <asm/mach/arch.h> #include "common.h" +#include "cpuidle.h" #include "hardware.h" +#define SIM_JTAG_ID_REG 0x8c + +static void __init imx7ulp_set_revision(void) +{ + struct regmap *sim; + u32 revision; + + sim = syscon_regmap_lookup_by_compatible("fsl,imx7ulp-sim"); + if (IS_ERR(sim)) { + pr_warn("failed to find fsl,imx7ulp-sim regmap!\n"); + return; + } + + if (regmap_read(sim, SIM_JTAG_ID_REG, &revision)) { + pr_warn("failed to read sim regmap!\n"); + return; + } + + /* + * bit[31:28] of JTAG_ID register defines revision as below from B0: + * 0001 B0 + * 0010 B1 + */ + switch (revision >> 28) { + case 1: + imx_set_soc_revision(IMX_CHIP_REVISION_2_0); + break; + case 2: + imx_set_soc_revision(IMX_CHIP_REVISION_2_1); + break; + default: + imx_set_soc_revision(IMX_CHIP_REVISION_1_0); + break; + } +} + static void __init imx7ulp_init_machine(void) { imx7ulp_pm_init(); mxc_set_cpu_type(MXC_CPU_IMX7ULP); + imx7ulp_set_revision(); of_platform_default_populate(NULL, NULL, imx_soc_device_init()); } @@ -25,7 +65,13 @@ static const char *const imx7ulp_dt_compat[] __initconst = { NULL, }; +static void __init imx7ulp_init_late(void) +{ + imx7ulp_cpuidle_init(); +} + DT_MACHINE_START(IMX7ulp, "Freescale i.MX7ULP (Device Tree)") .init_machine = imx7ulp_init_machine, .dt_compat = imx7ulp_dt_compat, + .init_late = imx7ulp_init_late, MACHINE_END |