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| author | Dinh Nguyen <dinguyen@altera.com> | 2014-02-17 20:31:02 -0600 |
|---|---|---|
| committer | Dinh Nguyen <dinguyen@altera.com> | 2014-03-09 23:11:35 -0500 |
| commit | 9b931361ff0971d2639b1366f8b468c687fa942f (patch) | |
| tree | 7d38293deaeddd014219ddbb749d23a88f575d24 /arch/arm/boot/dts/socfpga_cyclone5.dtsi | |
| parent | f1ce1a99f289474cf047923981369d5ba140c125 (diff) | |
| download | talos-op-linux-9b931361ff0971d2639b1366f8b468c687fa942f.tar.gz talos-op-linux-9b931361ff0971d2639b1366f8b468c687fa942f.zip | |
dts: socfpga: Add support for SD/MMC on the SOCFPGA platform
Introduce "altr,socfpga-dw-mshc" to enable Altera's SOCFPGA platform
specific implementation of the dw_mmc driver.
Also add the "syscon" binding to the "altr,sys-mgr" node. The clock
driver can use the syscon driver to toggle the register for the SD/MMC
clock phase shift settings.
Finally, fix an indentation error for the sysmgr node.
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Acked-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Tested-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Chris Ball <chris@printf.net>
Diffstat (limited to 'arch/arm/boot/dts/socfpga_cyclone5.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/socfpga_cyclone5.dtsi | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/socfpga_cyclone5.dtsi b/arch/arm/boot/dts/socfpga_cyclone5.dtsi index a8716f6dbe2e..ca41b0ebf461 100644 --- a/arch/arm/boot/dts/socfpga_cyclone5.dtsi +++ b/arch/arm/boot/dts/socfpga_cyclone5.dtsi @@ -28,6 +28,17 @@ }; }; + dwmmc0@ff704000 { + num-slots = <1>; + supports-highspeed; + broken-cd; + + slot@0 { + reg = <0>; + bus-width = <4>; + }; + }; + ethernet@ff702000 { phy-mode = "rgmii"; phy-addr = <0xffffffff>; /* probe for phy addr */ |
