Merge tag 'intc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers

Merge "omap intc changes for v3.18 merge window" from Tony Lindgren:

Interrupt code related clean-up for omap2 and 3 to make
it ready to move to drivers/irqchip. Note that this series
does not yet move the interrupt code to drivers, that will
be posted separately as a follow-up series.

Note that this branch has a dependency to patches both
in fixes-v3.18-not-urgent and soc-for-v3.18 and is based on
a merge. Without doing the merge, off-idle would not work
properly for git bisect.

* tag 'intc-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (325 commits)
  arm: omap: intc: switch over to linear irq domain
  arm: omap: irq: get rid of ifdef hack
  arm: omap: irq: introduce omap_nr_pending
  arm: omap: irq: remove nr_irqs argument
  arm: omap: irq: remove unnecessary header
  arm: omap: irq: drop omap2_intc_handle_irq()
  arm: omap: irq: drop omap3_intc_handle_irq()
  arm: omap: irq: call set_handle_irq() from .init_irq
  arm: omap: irq: move some more code around
  arm: boot: dts: omap2/3/am33xx: drop ti,intc-size
  arm: omap: irq: drop ti,intc-size support
  arm: boot: dts: am33xx/omap3: fix intc compatible flag
  arm: omap: irq: use compatible flag to figure out number of IRQ lines
  arm: omap: irq: add specific compatibles for omap3 and am33xx devices
  arm: omap: irq: drop .handle_irq and .init_irq fields
  arm: omap: irq: use IRQCHIP_DECLARE macro
  arm: omap: irq: call set_handle_irq() from intc_of_init
  arm: omap: irq: make intc_of_init static
  arm: omap: irq: reorganize code a little bit
  arm: omap: irq: always define omap3 support
  ...

Signed-off-by: Olof Johansson <olof@lixom.net>

1 files changed, 8 insertions, 0 deletions

diff --git a/arch/arm/boot/dts/imx53-qsrb.dts b/arch/arm/boot/dts/imx53-qsrb.dts
index f1bbf9a32991..82d623d05915 100644
--- a/arch/arm/boot/dts/imx53-qsrb.dts
+++ b/arch/arm/boot/dts/imx53-qsrb.dts
@@ -28,6 +28,12 @@
 				MX53_PAD_CSI0_DAT9__I2C1_SCL      0x400001ec
 			>;
 		};
+
+		pinctrl_pmic: pmicgrp {
+			fsl,pins = <
+				MX53_PAD_CSI0_DAT5__GPIO5_23	0x1e4 /* IRQ */
+			>;
+		};
 	};
 };
 
@@ -38,6 +44,8 @@
 
 	pmic: mc34708@8 {
 		compatible = "fsl,mc34708";
+		pinctrl-names = "default";
+		pinctrl-0 = <&pinctrl_pmic>;
 		reg = <0x08>;
 		interrupt-parent = <&gpio5>;
 		interrupts = <23 0x8>;