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author | Bartosz Golaszewski <bgolaszewski@baylibre.com> | 2016-10-31 15:45:34 +0100 |
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committer | Sekhar Nori <nsekhar@ti.com> | 2016-11-14 17:18:34 +0530 |
commit | 62a8a73923edf97cdc4997a99065045743caddf1 (patch) | |
tree | 02a328bf6067eaa11326784f3e04fb0e3dbafab3 /Documentation/devicetree/bindings | |
parent | 1001354ca34179f3db924eb66672442a173147dc (diff) | |
download | talos-op-linux-62a8a73923edf97cdc4997a99065045743caddf1.tar.gz talos-op-linux-62a8a73923edf97cdc4997a99065045743caddf1.zip |
memory: davinci: add support for da8xx DDR2/mDDR controller
Create a new driver for the da8xx DDR2/mDDR controller and implement
support for writing to the Peripheral Bus Burst Priority Register.
Reviewed-by: Kevin Hilman <khilman@baylibre.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com>
[nsekhar@ti.com: subject line adjustment]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
Diffstat (limited to 'Documentation/devicetree/bindings')
-rw-r--r-- | Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt new file mode 100644 index 000000000000..ec1dd408d573 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt @@ -0,0 +1,20 @@ +* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory controller + +The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs features +a set of registers which allow to tweak the controller's behavior. + +Documentation: +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf + +Required properties: + +- compatible: "ti,da850-ddr-controller" - for da850 SoC based boards +- reg: a tuple containing the base address of the memory + controller and the size of the memory area to map + +Example for da850 shown below. + +ddrctl { + compatible = "ti,da850-ddr-controller"; + reg = <0xb0000000 0xe8>; +}; |