diff options
| author | Jesse Barnes <jbarnes@virtuousgeek.org> | 2011-10-13 10:08:34 -0700 |
|---|---|---|
| committer | Keith Packard <keithp@keithp.com> | 2011-10-20 23:21:58 -0700 |
| commit | a487928908226df493a3ce145ecf4bb39296714e (patch) | |
| tree | 8b967adcac68bff3383dbefab246ce7541f4b265 | |
| parent | 4c9c18c29347a8bfce1dcd28271bf782aab16639 (diff) | |
| download | talos-op-linux-a487928908226df493a3ce145ecf4bb39296714e.tar.gz talos-op-linux-a487928908226df493a3ce145ecf4bb39296714e.zip | |
drm/i915: remove transcoder PLL mashing from mode_set per specs
Belongs in PCH enable instead. The duplication is worrying and the
specs explicitly list transcoder select *after* actual PLL enable, which
doesn't occur until later.
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Reviewed-By: Eugeni Dodonov <eugeni.dodonov@intel.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
| -rw-r--r-- | drivers/gpu/drm/i915/intel_display.c | 25 |
1 files changed, 0 insertions, 25 deletions
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 921253cb4f85..981b1f1c04d8 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -5620,31 +5620,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, } } - /* enable transcoder DPLL */ - if (HAS_PCH_CPT(dev)) { - u32 transc_sel = intel_crtc->use_pll_a ? TRANSC_DPLLA_SEL : - TRANSC_DPLLB_SEL; - temp = I915_READ(PCH_DPLL_SEL); - switch (pipe) { - case 0: - temp |= TRANSA_DPLL_ENABLE | TRANSA_DPLLA_SEL; - break; - case 1: - temp |= TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL; - break; - case 2: - temp &= ~(TRANSC_DPLLB_SEL); - temp |= TRANSC_DPLL_ENABLE | transc_sel; - break; - default: - BUG(); - } - I915_WRITE(PCH_DPLL_SEL, temp); - - POSTING_READ(PCH_DPLL_SEL); - udelay(150); - } - /* The LVDS pin pair needs to be on before the DPLLs are enabled. * This is an exception to the general rule that mode_set doesn't turn * things on. |
