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authorGreg Kroah-Hartman <gregkh@suse.de>2012-01-26 11:15:18 -0800
committerGreg Kroah-Hartman <gregkh@suse.de>2012-01-26 11:15:18 -0800
commit8a74e9ffd97dc9de063de8c02ae32db79dd60436 (patch)
treef5cd7e7a069def779b0b5b01814e6682b5b4f9db
parentaf681cad3f79ad8f7bd6cb170b70990aeef74233 (diff)
downloadtalos-op-linux-8a74e9ffd97dc9de063de8c02ae32db79dd60436.tar.gz
talos-op-linux-8a74e9ffd97dc9de063de8c02ae32db79dd60436.zip
Revert "tty: serial: OMAP: ensure FIFO levels are set correctly in non-DMA mode"
This reverts commit 0a697b22252c9d7208b5fb3e9fbd124dd229f1d2 as Paul wants to rework it. Cc: Paul Walmsley <paul@pwsan.com> Cc: Tomi Valkeinen <tomi.valkeinen@ti.com> Cc: Govindraj Raja <govindraj.r@ti.com> Cc: Kevin Hilman <khilman@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
-rw-r--r--drivers/tty/serial/omap-serial.c35
1 files changed, 4 insertions, 31 deletions
diff --git a/drivers/tty/serial/omap-serial.c b/drivers/tty/serial/omap-serial.c
index ca54f038ab45..1c2426931484 100644
--- a/drivers/tty/serial/omap-serial.c
+++ b/drivers/tty/serial/omap-serial.c
@@ -46,18 +46,6 @@
#define DEFAULT_CLK_SPEED 48000000 /* 48Mhz*/
-/* SCR register bitmasks */
-#define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK (1 << 7)
-#define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK (1 << 6)
-
-/* FCR register bitmasks */
-#define OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT 6
-#define OMAP_UART_FCR_RX_FIFO_TRIG_MASK (0x3 << 6)
-#define OMAP_UART_FCR_TX_FIFO_TRIG_SHIFT 4
-
-/* TLR register bitmasks */
-#define OMAP_UART_TLR_TX_FIFO_TRIG_DMA_SHIFT 0
-
static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
/* Forward declaration of functions */
@@ -706,7 +694,6 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
unsigned char efr = 0;
unsigned long flags = 0;
unsigned int baud, quot;
- u32 tlr;
switch (termios->c_cflag & CSIZE) {
case CS5:
@@ -824,28 +811,14 @@ serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
up->mcr = serial_in(up, UART_MCR);
serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
/* FIFO ENABLE, DMA MODE */
-
- up->scr |= OMAP_UART_SCR_TX_TRIG_GRANU1_MASK;
- up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
+ serial_out(up, UART_FCR, up->fcr);
+ serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
if (up->use_dma) {
- tlr = 0;
- } else {
- up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
-
- /* Set receive FIFO threshold to 1 */
- up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
- up->fcr |= (0x1 << OMAP_UART_FCR_RX_FIFO_TRIG_SHIFT);
-
- /* Set TX FIFO threshold to "63" (actually 1) */
- up->fcr |= (0x3 << OMAP_UART_FCR_TX_FIFO_TRIG_SHIFT);
- tlr = (0xf << OMAP_UART_TLR_TX_FIFO_TRIG_DMA_SHIFT);
+ serial_out(up, UART_TI752_TLR, 0);
+ up->scr |= (UART_FCR_TRIGGER_4 | UART_FCR_TRIGGER_8);
}
- serial_out(up, UART_TI752_TLR, tlr);
- serial_out(up, UART_FCR, up->fcr);
- serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
-
serial_out(up, UART_OMAP_SCR, up->scr);
serial_out(up, UART_EFR, up->efr);
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