diff options
| author | Flora Cui <Flora.Cui@amd.com> | 2016-03-14 18:33:29 -0400 |
|---|---|---|
| committer | Alex Deucher <alexander.deucher@amd.com> | 2016-05-04 20:27:57 -0400 |
| commit | 2cc0c0b5cd4d07a65267c28a4f7b68134abff472 (patch) | |
| tree | 6f989d1e7fb5706e171c08881720ba8da8734bfc | |
| parent | a3ad7a9ad8ef2e87ffa7e65d6ce0e9928b4134e9 (diff) | |
| download | talos-op-linux-2cc0c0b5cd4d07a65267c28a4f7b68134abff472.tar.gz talos-op-linux-2cc0c0b5cd4d07a65267c28a4f7b68134abff472.zip | |
drm/amdgpu: change ELM/BAF to Polaris10/Polaris11
Adjust to preferred code names.
Signed-off-by: Flora Cui <Flora.Cui@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
35 files changed, 1454 insertions, 1269 deletions
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c index e0668173fc1a..837cdd2a6a2b 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.c @@ -681,8 +681,8 @@ static uint32_t fw_type_convert(struct cgs_device *cgs_device, uint32_t fw_type) result = AMDGPU_UCODE_ID_CP_MEC1; break; case CGS_UCODE_ID_CP_MEC_JT2: - if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_BAFFIN - || adev->asic_type == CHIP_ELLESMERE) + if (adev->asic_type == CHIP_TONGA || adev->asic_type == CHIP_POLARIS11 + || adev->asic_type == CHIP_POLARIS10) result = AMDGPU_UCODE_ID_CP_MEC2; else result = AMDGPU_UCODE_ID_CP_MEC1; @@ -742,17 +742,17 @@ static int amdgpu_cgs_get_firmware_info(struct cgs_device *cgs_device, case CHIP_FIJI: strcpy(fw_name, "amdgpu/fiji_smc.bin"); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: if (type == CGS_UCODE_ID_SMU) - strcpy(fw_name, "amdgpu/baffin_smc.bin"); + strcpy(fw_name, "amdgpu/polaris11_smc.bin"); else if (type == CGS_UCODE_ID_SMU_SK) - strcpy(fw_name, "amdgpu/baffin_smc_sk.bin"); + strcpy(fw_name, "amdgpu/polaris11_smc_sk.bin"); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: if (type == CGS_UCODE_ID_SMU) - strcpy(fw_name, "amdgpu/ellesmere_smc.bin"); + strcpy(fw_name, "amdgpu/polaris10_smc.bin"); else if (type == CGS_UCODE_ID_SMU_SK) - strcpy(fw_name, "amdgpu/ellesmere_smc_sk.bin"); + strcpy(fw_name, "amdgpu/polaris10_smc_sk.bin"); break; default: DRM_ERROR("SMC firmware not supported\n"); diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c index 52245c4c6d65..14e832fe83db 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_device.c @@ -59,8 +59,8 @@ static const char *amdgpu_asic_name[] = { "FIJI", "CARRIZO", "STONEY", - "ELLESMERE", - "BAFFIN", + "POLARIS10", + "POLARIS11", "LAST", }; @@ -1148,8 +1148,8 @@ static int amdgpu_early_init(struct amdgpu_device *adev) case CHIP_TOPAZ: case CHIP_TONGA: case CHIP_FIJI: - case CHIP_BAFFIN: - case CHIP_ELLESMERE: + case CHIP_POLARIS11: + case CHIP_POLARIS10: case CHIP_CARRIZO: case CHIP_STONEY: if (adev->asic_type == CHIP_CARRIZO || adev->asic_type == CHIP_STONEY) diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c index e11b1f2982d6..b48942a1e567 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c @@ -277,16 +277,16 @@ static const struct pci_device_id pciidlist[] = { {0x1002, 0x9877, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_CARRIZO|AMD_IS_APU}, /* stoney */ {0x1002, 0x98E4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_STONEY|AMD_IS_APU}, - /* Baffin */ - {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_BAFFIN}, - /* Ellesmere */ - {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE}, - {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_ELLESMERE}, + /* Polaris11 */ + {0x1002, 0x67E0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67E1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67E8, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67E9, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67EB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + {0x1002, 0x67FF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS11}, + /* Polaris10 */ + {0x1002, 0x67C0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, + {0x1002, 0x67DF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_POLARIS10}, {0, 0, 0} }; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c index ea2006a768eb..f315995e931e 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_powerplay.c @@ -99,10 +99,12 @@ static int amdgpu_pp_early_init(void *handle) #ifdef CONFIG_DRM_AMD_POWERPLAY switch (adev->asic_type) { + case CHIP_POLARIS11: + case CHIP_POLARIS10: + adev->pp_enabled = true; + break; case CHIP_TONGA: case CHIP_FIJI: - case CHIP_BAFFIN: - case CHIP_ELLESMERE: adev->pp_enabled = (amdgpu_powerplay == 0) ? false : true; break; case CHIP_CARRIZO: diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c index 9599bc6484b4..cf01137fe6e4 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c @@ -54,8 +54,8 @@ #define FIRMWARE_CARRIZO "amdgpu/carrizo_uvd.bin" #define FIRMWARE_FIJI "amdgpu/fiji_uvd.bin" #define FIRMWARE_STONEY "amdgpu/stoney_uvd.bin" -#define FIRMWARE_ELLESMERE "amdgpu/ellesmere_uvd.bin" -#define FIRMWARE_BAFFIN "amdgpu/baffin_uvd.bin" +#define FIRMWARE_POLARIS10 "amdgpu/polaris10_uvd.bin" +#define FIRMWARE_POLARIS11 "amdgpu/polaris11_uvd.bin" /** * amdgpu_uvd_cs_ctx - Command submission parser context @@ -87,8 +87,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA); MODULE_FIRMWARE(FIRMWARE_CARRIZO); MODULE_FIRMWARE(FIRMWARE_FIJI); MODULE_FIRMWARE(FIRMWARE_STONEY); -MODULE_FIRMWARE(FIRMWARE_ELLESMERE); -MODULE_FIRMWARE(FIRMWARE_BAFFIN); +MODULE_FIRMWARE(FIRMWARE_POLARIS10); +MODULE_FIRMWARE(FIRMWARE_POLARIS11); static void amdgpu_uvd_note_usage(struct amdgpu_device *adev); static void amdgpu_uvd_idle_work_handler(struct work_struct *work); @@ -135,11 +135,11 @@ int amdgpu_uvd_sw_init(struct amdgpu_device *adev) case CHIP_STONEY: fw_name = FIRMWARE_STONEY; break; - case CHIP_ELLESMERE: - fw_name = FIRMWARE_ELLESMERE; + case CHIP_POLARIS10: + fw_name = FIRMWARE_POLARIS10; break; - case CHIP_BAFFIN: - fw_name = FIRMWARE_BAFFIN; + case CHIP_POLARIS11: + fw_name = FIRMWARE_POLARIS11; break; default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c index 66d5f7fee485..80c1048f3324 100644 --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c @@ -50,8 +50,8 @@ #define FIRMWARE_CARRIZO "amdgpu/carrizo_vce.bin" #define FIRMWARE_FIJI "amdgpu/fiji_vce.bin" #define FIRMWARE_STONEY "amdgpu/stoney_vce.bin" -#define FIRMWARE_ELLESMERE "amdgpu/ellesmere_vce.bin" -#define FIRMWARE_BAFFIN "amdgpu/baffin_vce.bin" +#define FIRMWARE_POLARIS10 "amdgpu/polaris10_vce.bin" +#define FIRMWARE_POLARIS11 "amdgpu/polaris11_vce.bin" #ifdef CONFIG_DRM_AMDGPU_CIK MODULE_FIRMWARE(FIRMWARE_BONAIRE); @@ -64,8 +64,8 @@ MODULE_FIRMWARE(FIRMWARE_TONGA); MODULE_FIRMWARE(FIRMWARE_CARRIZO); MODULE_FIRMWARE(FIRMWARE_FIJI); MODULE_FIRMWARE(FIRMWARE_STONEY); -MODULE_FIRMWARE(FIRMWARE_ELLESMERE); -MODULE_FIRMWARE(FIRMWARE_BAFFIN); +MODULE_FIRMWARE(FIRMWARE_POLARIS10); +MODULE_FIRMWARE(FIRMWARE_POLARIS11); static void amdgpu_vce_idle_work_handler(struct work_struct *work); @@ -117,11 +117,11 @@ int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) case CHIP_STONEY: fw_name = FIRMWARE_STONEY; break; - case CHIP_ELLESMERE: - fw_name = FIRMWARE_ELLESMERE; + case CHIP_POLARIS10: + fw_name = FIRMWARE_POLARIS10; break; - case CHIP_BAFFIN: - fw_name = FIRMWARE_BAFFIN; + case CHIP_POLARIS11: + fw_name = FIRMWARE_POLARIS11; break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index 61afc5eab1b5..d28873c5f5b3 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -132,7 +132,7 @@ static const u32 stoney_golden_settings_a11[] = mmFBC_MISC, 0x1f311fff, 0x14302000, }; -static const u32 baffin_golden_settings_a11[] = +static const u32 polaris11_golden_settings_a11[] = { mmDCI_CLK_CNTL, 0x00000080, 0x00000000, mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, @@ -141,7 +141,7 @@ static const u32 baffin_golden_settings_a11[] = mmHDMI_CONTROL, 0x313f031f, 0x00000011, }; -static const u32 ellesmere_golden_settings_a11[] = +static const u32 polaris10_golden_settings_a11[] = { mmDCI_CLK_CNTL, 0x00000080, 0x00000000, mmFBC_DEBUG_COMP, 0x000000f0, 0x00000070, @@ -165,15 +165,15 @@ static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) stoney_golden_settings_a11, (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_program_register_sequence(adev, - baffin_golden_settings_a11, - (const u32)ARRAY_SIZE(baffin_golden_settings_a11)); + polaris11_golden_settings_a11, + (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, - ellesmere_golden_settings_a11, - (const u32)ARRAY_SIZE(ellesmere_golden_settings_a11)); + polaris10_golden_settings_a11, + (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); break; default: break; @@ -1611,10 +1611,10 @@ static int dce_v11_0_audio_init(struct amdgpu_device *adev) case CHIP_STONEY: adev->mode_info.audio.num_pins = 7; break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: adev->mode_info.audio.num_pins = 8; break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: adev->mode_info.audio.num_pins = 6; break; default: @@ -2411,8 +2411,8 @@ static u32 dce_v11_0_pick_pll(struct drm_crtc *crtc) u32 pll_in_use; int pll; - if ((adev->asic_type == CHIP_ELLESMERE) || - (adev->asic_type == CHIP_BAFFIN)) { + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(amdgpu_crtc->encoder); struct amdgpu_encoder_atom_dig *dig = amdgpu_encoder->enc_priv; @@ -2838,8 +2838,8 @@ static int dce_v11_0_crtc_mode_set(struct drm_crtc *crtc, if (!amdgpu_crtc->adjusted_clock) return -EINVAL; - if ((adev->asic_type == CHIP_ELLESMERE) || - (adev->asic_type == CHIP_BAFFIN)) { + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) { struct amdgpu_encoder *amdgpu_encoder = to_amdgpu_encoder(amdgpu_crtc->encoder); int encoder_mode = @@ -3004,12 +3004,12 @@ static int dce_v11_0_early_init(void *handle) adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 9; break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: adev->mode_info.num_crtc = 6; adev->mode_info.num_hpd = 6; adev->mode_info.num_dig = 6; break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: adev->mode_info.num_crtc = 5; adev->mode_info.num_hpd = 5; adev->mode_info.num_dig = 5; @@ -3116,8 +3116,8 @@ static int dce_v11_0_hw_init(void *handle) /* init dig PHYs, disp eng pll */ amdgpu_atombios_crtc_powergate_init(adev); amdgpu_atombios_encoder_init_dig(adev); - if ((adev->asic_type == CHIP_ELLESMERE) || - (adev->asic_type == CHIP_BAFFIN)) { + if ((adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) { amdgpu_atombios_crtc_set_dce_clock(adev, adev->clock.default_dispclk, DCE_CLOCK_TYPE_DISPCLK, ATOM_GCK_DFS); amdgpu_atombios_crtc_set_dce_clock(adev, 0, diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c index 651edc1b1a6d..6be83f183f16 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c @@ -52,7 +52,7 @@ #define TOPAZ_GB_ADDR_CONFIG_GOLDEN 0x22010001 #define CARRIZO_GB_ADDR_CONFIG_GOLDEN 0x22010001 -#define BAFFIN_GB_ADDR_CONFIG_GOLDEN 0x22011002 +#define POLARIS11_GB_ADDR_CONFIG_GOLDEN 0x22011002 #define TONGA_GB_ADDR_CONFIG_GOLDEN 0x22011003 #define ARRAY_MODE(x) ((x) << GB_TILE_MODE0__ARRAY_MODE__SHIFT) @@ -121,19 +121,19 @@ MODULE_FIRMWARE("amdgpu/fiji_mec.bin"); MODULE_FIRMWARE("amdgpu/fiji_mec2.bin"); MODULE_FIRMWARE("amdgpu/fiji_rlc.bin"); -MODULE_FIRMWARE("amdgpu/baffin_ce.bin"); -MODULE_FIRMWARE("amdgpu/baffin_pfp.bin"); -MODULE_FIRMWARE("amdgpu/baffin_me.bin"); -MODULE_FIRMWARE("amdgpu/baffin_mec.bin"); -MODULE_FIRMWARE("amdgpu/baffin_mec2.bin"); -MODULE_FIRMWARE("amdgpu/baffin_rlc.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_ce.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_pfp.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_me.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mec.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mec2.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_rlc.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_ce.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_pfp.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_me.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_mec.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_mec2.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_rlc.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_ce.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_pfp.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_me.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mec.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mec2.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_rlc.bin"); static const struct amdgpu_gds_reg_offset amdgpu_gds_reg_offset[] = { @@ -265,7 +265,7 @@ static const u32 tonga_mgcg_cgcg_init[] = mmCP_MEM_SLP_CNTL, 0x00000001, 0x00000001, }; -static const u32 golden_settings_baffin_a11[] = +static const u32 golden_settings_polaris11_a11[] = { mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, mmDB_DEBUG2, 0xf00fffff, 0x00000400, @@ -281,7 +281,7 @@ static const u32 golden_settings_baffin_a11[] = mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003210, }; -static const u32 baffin_golden_common_all[] = +static const u32 polaris11_golden_common_all[] = { mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, @@ -293,7 +293,7 @@ static const u32 baffin_golden_common_all[] = mmSPI_RESOURCE_RESERVE_EN_CU_1, 0xffffffff, 0x00007FAF, }; -static const u32 golden_settings_ellesmere_a11[] = +static const u32 golden_settings_polaris10_a11[] = { mmATC_MISC_CG, 0x000c0fc0, 0x000c0200, mmCB_HW_CONTROL_3, 0x000001ff, 0x00000040, @@ -311,7 +311,7 @@ static const u32 golden_settings_ellesmere_a11[] = mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000, }; -static const u32 ellesmere_golden_common_all[] = +static const u32 polaris10_golden_common_all[] = { mmGRBM_GFX_INDEX, 0xffffffff, 0xe0000000, mmPA_SC_RASTER_CONFIG, 0xffffffff, 0x16000012, @@ -674,21 +674,21 @@ static void gfx_v8_0_init_golden_registers(struct amdgpu_device *adev) tonga_golden_common_all, (const u32)ARRAY_SIZE(tonga_golden_common_all)); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_program_register_sequence(adev, - golden_settings_baffin_a11, - (const u32)ARRAY_SIZE(golden_settings_baffin_a11)); + golden_settings_polaris11_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); amdgpu_program_register_sequence(adev, - baffin_golden_common_all, - (const u32)ARRAY_SIZE(baffin_golden_common_all)); + polaris11_golden_common_all, + (const u32)ARRAY_SIZE(polaris11_golden_common_all)); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, - golden_settings_ellesmere_a11, - (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11)); + golden_settings_polaris10_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); amdgpu_program_register_sequence(adev, - ellesmere_golden_common_all, - (const u32)ARRAY_SIZE(ellesmere_golden_common_all)); + polaris10_golden_common_all, + (const u32)ARRAY_SIZE(polaris10_golden_common_all)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, @@ -859,11 +859,11 @@ static int gfx_v8_0_init_microcode(struct amdgpu_device *adev) case CHIP_FIJI: chip_name = "fiji"; break; - case CHIP_BAFFIN: - chip_name = "baffin"; + case CHIP_POLARIS11: + chip_name = "polaris11"; break; - case CHIP_ELLESMERE: - chip_name = "ellesmere"; + case CHIP_POLARIS10: + chip_name = "polaris10"; break; case CHIP_STONEY: chip_name = "stoney"; @@ -1092,11 +1092,11 @@ static void gfx_v8_0_get_csb_buffer(struct amdgpu_device *adev, PACKET3_SET_CONTEXT_REG_START); switch (adev->asic_type) { case CHIP_TONGA: - case CHIP_ELLESMERE: + case CHIP_POLARIS10: buffer[count++] = cpu_to_le32(0x16000012); buffer[count++] = cpu_to_le32(0x0000002A); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: buffer[count++] = cpu_to_le32(0x16000012); buffer[count++] = cpu_to_le32(0x00000000); break; @@ -1628,7 +1628,7 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; gb_addr_config = TONGA_GB_ADDR_CONFIG_GOLDEN; break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: ret = amdgpu_atombios_get_gfx_info(adev); if (ret) return ret; @@ -1640,9 +1640,9 @@ static int gfx_v8_0_gpu_early_init(struct amdgpu_device *adev) adev->gfx.config.sc_prim_fifo_size_backend = 0x100; adev->gfx.config.sc_hiz_tile_fifo_size = 0x30; adev->gfx.config.sc_earlyz_tile_fifo_size = 0x130; - gb_addr_config = BAFFIN_GB_ADDR_CONFIG_GOLDEN; + gb_addr_config = POLARIS11_GB_ADDR_CONFIG_GOLDEN; break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: ret = amdgpu_atombios_get_gfx_info(adev); if (ret) return ret; @@ -2551,7 +2551,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P4_16x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | @@ -2753,7 +2753,7 @@ static void gfx_v8_0_tiling_mode_table_init(struct amdgpu_device *adev) WREG32(mmGB_MACROTILE_MODE0 + reg_offset, mod2array[reg_offset]); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: modearray[0] = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) | PIPE_CONFIG(ADDR_SURF_P8_32x32_16x16) | TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | @@ -3658,7 +3658,7 @@ static void gfx_v8_0_enable_save_restore_machine(struct amdgpu_device *adev) WREG32(mmRLC_SRM_CNTL, data); } -static void baffin_init_power_gating(struct amdgpu_device *adev) +static void polaris11_init_power_gating(struct amdgpu_device *adev) { uint32_t data; @@ -3701,8 +3701,8 @@ static void gfx_v8_0_init_pg(struct amdgpu_device *adev) gfx_v8_0_init_save_restore_list(adev); gfx_v8_0_enable_save_restore_machine(adev); - if (adev->asic_type == CHIP_BAFFIN) - baffin_init_power_gating(adev); + if (adev->asic_type == CHIP_POLARIS11) + polaris11_init_power_gating(adev); } } @@ -3776,8 +3776,8 @@ static int gfx_v8_0_rlc_resume(struct amdgpu_device *adev) /* disable CG */ WREG32(mmRLC_CGCG_CGLS_CTRL, 0); - if (adev->asic_type == CHIP_BAFFIN || - adev->asic_type == CHIP_ELLESMERE) + if (adev->asic_type == CHIP_POLARIS11 || + adev->asic_type == CHIP_POLARIS10) WREG32(mmRLC_CGCG_CGLS_CTRL_3D, 0); /* disable PG */ @@ -3958,11 +3958,11 @@ static int gfx_v8_0_cp_gfx_start(struct amdgpu_device *adev) amdgpu_ring_write(ring, mmPA_SC_RASTER_CONFIG - PACKET3_SET_CONTEXT_REG_START); switch (adev->asic_type) { case CHIP_TONGA: - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_ring_write(ring, 0x16000012); amdgpu_ring_write(ring, 0x0000002A); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_ring_write(ring, 0x16000012); amdgpu_ring_write(ring, 0x00000000); break; @@ -4610,8 +4610,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) if ((adev->asic_type == CHIP_CARRIZO) || (adev->asic_type == CHIP_FIJI) || (adev->asic_type == CHIP_STONEY) || - (adev->asic_type == CHIP_BAFFIN) || - (adev->asic_type == CHIP_ELLESMERE)) { + (adev->asic_type == CHIP_POLARIS11) || + (adev->asic_type == CHIP_POLARIS10)) { WREG32(mmCP_MEC_DOORBELL_RANGE_LOWER, AMDGPU_DOORBELL_KIQ << 2); WREG32(mmCP_MEC_DOORBELL_RANGE_UPPER, @@ -4646,8 +4646,8 @@ static int gfx_v8_0_cp_compute_resume(struct amdgpu_device *adev) WREG32(mmCP_HQD_PERSISTENT_STATE, tmp); mqd->cp_hqd_persistent_state = tmp; if (adev->asic_type == CHIP_STONEY || - adev->asic_type == CHIP_BAFFIN || - adev->asic_type == CHIP_ELLESMERE) { + adev->asic_type == CHIP_POLARIS11 || + adev->asic_type == CHIP_POLARIS10) { tmp = RREG32(mmCP_ME1_PIPE3_INT_CNTL); tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE3_INT_CNTL, GENERIC2_INT_ENABLE, 1); WREG32(mmCP_ME1_PIPE3_INT_CNTL, tmp); @@ -5216,7 +5216,7 @@ static int gfx_v8_0_late_init(void *handle) return 0; } -static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, +static void polaris11_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, bool enable) { uint32_t data, temp; @@ -5242,7 +5242,7 @@ static void baffin_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev, } } -static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, +static void polaris11_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev, bool enable) { uint32_t data, temp; @@ -5263,7 +5263,7 @@ static void baffin_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev } } -static void baffin_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev, +static void polaris11_enable_gfx_quick_mg_power_gating(struct amdgpu_device *adev, bool enable) { uint32_t data, temp; @@ -5293,15 +5293,15 @@ static int gfx_v8_0_set_powergating_state(void *handle, return 0; switch (adev->asic_type) { - case CHIP_BAFFIN: - if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_SMG) - baffin_enable_gfx_static_mg_power_gating(adev, + case CHIP_POLARIS11: + if (adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) + polaris11_enable_gfx_static_mg_power_gating(adev, state == AMD_PG_STATE_GATE ? true : false); - else if (adev->pg_flags & AMDGPU_PG_SUPPORT_GFX_DMG) - baffin_enable_gfx_dynamic_mg_power_gating(adev, + else if (adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) + polaris11_enable_gfx_dynamic_mg_power_gating(adev, state == AMD_PG_STATE_GATE ? true : false); else - baffin_enable_gfx_quick_mg_power_gating(adev, + polaris11_enable_gfx_quick_mg_power_gating(adev, state == AMD_PG_STATE_GATE ? true : false); break; default: diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c index cf1f6680b55c..e6715ec2489f 100644 --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c @@ -43,8 +43,8 @@ static void gmc_v8_0_set_gart_funcs(struct amdgpu_device *adev); static void gmc_v8_0_set_irq_funcs(struct amdgpu_device *adev); MODULE_FIRMWARE("amdgpu/tonga_mc.bin"); -MODULE_FIRMWARE("amdgpu/baffin_mc.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_mc.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_mc.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_mc.bin"); static const u32 golden_settings_tonga_a11[] = { @@ -75,7 +75,7 @@ static const u32 fiji_mgcg_cgcg_init[] = mmMC_MEM_POWER_LS, 0xffffffff, 0x00000104 }; -static const u32 golden_settings_baffin_a11[] = +static const u32 golden_settings_polaris11_a11[] = { mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, mmVM_PRT_APERTURE1_LOW_ADDR, 0x0fffffff, 0x0fffffff, @@ -83,7 +83,7 @@ static const u32 golden_settings_baffin_a11[] = mmVM_PRT_APERTURE3_LOW_ADDR, 0x0fffffff, 0x0fffffff }; -static const u32 golden_settings_ellesmere_a11[] = +static const u32 golden_settings_polaris10_a11[] = { mmMC_ARB_WTM_GRPWT_RD, 0x00000003, 0x00000000, mmVM_PRT_APERTURE0_LOW_ADDR, 0x0fffffff, 0x0fffffff, @@ -122,15 +122,15 @@ static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_program_register_sequence(adev, - golden_settings_baffin_a11, - (const u32)ARRAY_SIZE(golden_settings_baffin_a11)); + golden_settings_polaris11_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, - golden_settings_ellesmere_a11, - (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11)); + golden_settings_polaris10_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, @@ -238,11 +238,11 @@ static int gmc_v8_0_init_microcode(struct amdgpu_device *adev) case CHIP_TONGA: chip_name = "tonga"; break; - case CHIP_BAFFIN: - chip_name = "baffin"; + case CHIP_POLARIS11: + chip_name = "polaris11"; break; - case CHIP_ELLESMERE: - chip_name = "ellesmere"; + case CHIP_POLARIS10: + chip_name = "polaris10"; break; case CHIP_FIJI: case CHIP_CARRIZO: diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c index 79e5fd018a11..1b5053f9b120 100644 --- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c @@ -56,10 +56,10 @@ MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma.bin"); MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin"); MODULE_FIRMWARE("amdgpu/stoney_sdma.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_sdma.bin"); -MODULE_FIRMWARE("amdgpu/ellesmere_sdma1.bin"); -MODULE_FIRMWARE("amdgpu/baffin_sdma.bin"); -MODULE_FIRMWARE("amdgpu/baffin_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin"); +MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin"); +MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin"); static const u32 sdma_offsets[SDMA_MAX_INSTANCE] = @@ -106,7 +106,7 @@ static const u32 fiji_mgcg_cgcg_init[] = mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100 }; -static const u32 golden_settings_baffin_a11[] = +static const u32 golden_settings_polaris11_a11[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100, @@ -118,7 +118,7 @@ static const u32 golden_settings_baffin_a11[] = mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100, }; -static const u32 golden_settings_ellesmere_a11[] = +static const u32 golden_settings_polaris10_a11[] = { mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007, mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000, @@ -203,15 +203,15 @@ static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11)); break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: amdgpu_program_register_sequence(adev, - golden_settings_baffin_a11, - (const u32)ARRAY_SIZE(golden_settings_baffin_a11)); + golden_settings_polaris11_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, - golden_settings_ellesmere_a11, - (const u32)ARRAY_SIZE(golden_settings_ellesmere_a11)); + golden_settings_polaris10_a11, + (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); break; case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, @@ -261,11 +261,11 @@ static int sdma_v3_0_init_microcode(struct amdgpu_device *adev) case CHIP_FIJI: chip_name = "fiji"; break; - case CHIP_BAFFIN: - chip_name = "baffin"; + case CHIP_POLARIS11: + chip_name = "polaris11"; break; - case CHIP_ELLESMERE: - chip_name = "ellesmere"; + case CHIP_POLARIS10: + chip_name = "polaris10"; break; case CHIP_CARRIZO: chip_name = "carrizo"; diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c index c12fd832c884..58342853b69c 100644 --- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c +++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c @@ -315,11 +315,11 @@ static unsigned vce_v3_0_get_harvest_config(struct amdgpu_device *adev) { u32 tmp; - /* Fiji, Stoney, Ellesmere, Baffin are single pipe */ + /* Fiji, Stoney, Polaris10, Polaris11 are single pipe */ if ((adev->asic_type == CHIP_FIJI) || (adev->asic_type == CHIP_STONEY) || - (adev->asic_type == CHIP_ELLESMERE) || - (adev->asic_type == CHIP_BAFFIN)) + (adev->asic_type == CHIP_POLARIS10) || + (adev->asic_type == CHIP_POLARIS11)) return AMDGPU_VCE_HARVEST_VCE1; /* Tonga and CZ are dual or single pipe */ diff --git a/drivers/gpu/drm/amd/amdgpu/vi.c b/drivers/gpu/drm/amd/amdgpu/vi.c index ae78bd41db7b..2c228d6c672e 100644 --- a/drivers/gpu/drm/amd/amdgpu/vi.c +++ b/drivers/gpu/drm/amd/amdgpu/vi.c @@ -276,8 +276,8 @@ static void vi_init_golden_registers(struct amdgpu_device *adev) stoney_mgcg_cgcg_init, (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); break; - case CHIP_BAFFIN: - case CHIP_ELLESMERE: + case CHIP_POLARIS11: + case CHIP_POLARIS10: default: break; } @@ -539,8 +539,8 @@ static int vi_read_register(struct amdgpu_device *adev, u32 se_num, break; case CHIP_FIJI: case CHIP_TONGA: - case CHIP_BAFFIN: - case CHIP_ELLESMERE: + case CHIP_POLARIS11: + case CHIP_POLARIS10: case CHIP_CARRIZO: case CHIP_STONEY: asic_register_table = cz_allowed_read_registers; @@ -911,7 +911,7 @@ static const struct amdgpu_ip_block_version fiji_ip_blocks[] = }, }; -static const struct amdgpu_ip_block_version baffin_ip_blocks[] = +static const struct amdgpu_ip_block_version polaris11_ip_blocks[] = { /* ORDER MATTERS! */ { @@ -1071,10 +1071,10 @@ int vi_set_ip_blocks(struct amdgpu_device *adev) adev->ip_blocks = tonga_ip_blocks; adev->num_ip_blocks = ARRAY_SIZE(tonga_ip_blocks); break; - case CHIP_BAFFIN: - case CHIP_ELLESMERE: - adev->ip_blocks = baffin_ip_blocks; - adev->num_ip_blocks = ARRAY_SIZE(baffin_ip_blocks); + case CHIP_POLARIS11: + case CHIP_POLARIS10: + adev->ip_blocks = polaris11_ip_blocks; + adev->num_ip_blocks = ARRAY_SIZE(polaris11_ip_blocks); break; case CHIP_CARRIZO: case CHIP_STONEY: @@ -1177,12 +1177,12 @@ static int vi_common_early_init(void *handle) adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x14; break; - case CHIP_BAFFIN: + case CHIP_POLARIS11: adev->cg_flags = 0; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x5A; break; - case CHIP_ELLESMERE: + case CHIP_POLARIS10: adev->cg_flags = 0; adev->pg_flags = 0; adev->external_rev_id = adev->rev_id + 0x50; diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h index 72858a06c2dd..e56d8a378570 100644 --- a/drivers/gpu/drm/amd/include/amd_shared.h +++ b/drivers/gpu/drm/amd/include/amd_shared.h @@ -48,8 +48,8 @@ enum amd_asic_type { CHIP_FIJI, CHIP_CARRIZO, CHIP_STONEY, - CHIP_ELLESMERE, - CHIP_BAFFIN, + CHIP_POLARIS10, + CHIP_POLARIS11, CHIP_LAST, }; diff --git a/drivers/gpu/drm/amd/include/atombios.h b/drivers/gpu/drm/amd/include/atombios.h index 296def32e45d..32f3e345de08 100644 --- a/drivers/gpu/drm/amd/include/atombios.h +++ b/drivers/gpu/drm/amd/include/atombios.h @@ -2061,7 +2061,7 @@ typedef struct _SET_DCE_CLOCK_PS_ALLOCATION_V1_1 #define SET_DCE_CLOCK_FLAG_DPREFCLK_BYPASS 0x01 #define SET_DCE_CLOCK_FLAG_ENABLE_PIXCLK 0x02 -// SetDCEClockTable input parameter for DCE11.2( ELM and BF ) and above +// SetDCEClockTable input parameter for DCE11.2( POLARIS10 and POLARIS11 ) and above typedef struct _SET_DCE_CLOCK_PARAMETERS_V2_1 { ULONG ulDCEClkFreq; // target DCE frequency in unit of 10KHZ, return real DISPCLK/DPREFCLK frequency. @@ -5494,7 +5494,7 @@ typedef struct _ATOM_ASIC_PROFILING_INFO_V3_4 ULONG ulReserved[8]; // Reserved for future ASIC }ATOM_ASIC_PROFILING_INFO_V3_4; -// for Ellemser/Baffin speed EVV algorithm +// for Polaris10/Polaris11 speed EVV algorithm typedef struct _ATOM_ASIC_PROFILING_INFO_V3_5 { ATOM_COMMON_TABLE_HEADER asHeader; @@ -5549,7 +5549,7 @@ typedef struct _ATOM_SCLK_FCW_RANGE_ENTRY_V1{ }ATOM_SCLK_FCW_RANGE_ENTRY_V1; -// SMU_InfoTable for Ellesmere/Baffin +// SMU_InfoTable for Polaris10/Polaris11 typedef struct _ATOM_SMU_INFO_V2_1 { ATOM_COMMON_TABLE_HEADER asHeader; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile index 5437ec0ac99b..f7ce4cb71346 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile @@ -9,8 +9,8 @@ HARDWARE_MGR = hwmgr.o processpptables.o functiontables.o \ tonga_hwmgr.o pppcielanes.o tonga_thermal.o\ fiji_powertune.o fiji_hwmgr.o tonga_clockpowergating.o \ fiji_clockpowergating.o fiji_thermal.o \ - ellesmere_hwmgr.o ellesmere_powertune.o ellesmere_thermal.o \ - ellesmere_clockpowergating.o + polaris10_hwmgr.o polaris10_powertune.o polaris10_thermal.o \ + polaris10_clockpowergating.o AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h deleted file mode 100644 index ba1187c84008..000000000000 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_dyn_defaults.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright 2015 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - */ - -#ifndef ELLESMERE_DYN_DEFAULTS_H -#define ELLESMERE_DYN_DEFAULTS_H - - -enum Ellesmeredpm_TrendDetection { - EllesmereAdpm_TrendDetection_AUTO, - EllesmereAdpm_TrendDetection_UP, - EllesmereAdpm_TrendDetection_DOWN -}; -typedef enum Ellesmeredpm_TrendDetection Ellesmeredpm_TrendDetection; - -/* We need to fill in the default values */ - - -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1 0x000400 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2 0xC00080 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3 0xC00200 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4 0xC01680 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5 0xC00033 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6 0xC00033 -#define PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7 0x3FFFC000 - - -#define PPELLESMERE_THERMALPROTECTCOUNTER_DFLT 0x200 -#define PPELLESMERE_STATICSCREENTHRESHOLDUNIT_DFLT 0 -#define PPELLESMERE_STATICSCREENTHRESHOLD_DFLT 0x00C8 -#define PPELLESMERE_GFXIDLECLOCKSTOPTHRESHOLD_DFLT 0x200 -#define PPELLESMERE_REFERENCEDIVIDER_DFLT 4 - -#define PPELLESMERE_ULVVOLTAGECHANGEDELAY_DFLT 1687 - -#define PPELLESMERE_CGULVPARAMETER_DFLT 0x00040035 -#define PPELLESMERE_CGULVCONTROL_DFLT 0x00007450 -#define PPELLESMERE_TARGETACTIVITY_DFLT 50 -#define PPELLESMERE_MCLK_TARGETACTIVITY_DFLT 10 - -#endif - diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c index 2c6819904017..7d69ed635bc2 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/hwmgr.c @@ -34,7 +34,7 @@ extern int cz_hwmgr_init(struct pp_hwmgr *hwmgr); extern int tonga_hwmgr_init(struct pp_hwmgr *hwmgr); extern int fiji_hwmgr_init(struct pp_hwmgr *hwmgr); -extern int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr); +extern int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr); int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) { @@ -68,9 +68,9 @@ int hwmgr_init(struct amd_pp_init *pp_init, struct pp_instance *handle) case CHIP_FIJI: fiji_hwmgr_init(hwmgr); break; - case CHIP_BAFFIN: - case CHIP_ELLESMERE: - ellesemere_hwmgr_init(hwmgr); + case CHIP_POLARIS11: + case CHIP_POLARIS10: + polaris10_hwmgr_init(hwmgr); break; default: return -EINVAL; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c index 93db8241a154..e362ddb37544 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.c @@ -21,9 +21,9 @@ * */ -#include "ellesmere_clockpowergating.h" +#include "polaris10_clockpowergating.h" -int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr) +int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr) { if (phm_cf_want_uvd_power_gating(hwmgr)) return smum_send_msg_to_smc(hwmgr->smumgr, @@ -31,7 +31,7 @@ int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr) return 0; } -int ellesmere_phm_powerup_uvd(struct pp_hwmgr *hwmgr) +int polaris10_phm_powerup_uvd(struct pp_hwmgr *hwmgr) { if (phm_cf_want_uvd_power_gating(hwmgr)) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, @@ -47,7 +47,7 @@ int ellesmere_phm_powerup_uvd(struct pp_hwmgr *hwmgr) return 0; } -int ellesmere_phm_powerdown_vce(struct pp_hwmgr *hwmgr) +int polaris10_phm_powerdown_vce(struct pp_hwmgr *hwmgr) { if (phm_cf_want_vce_power_gating(hwmgr)) return smum_send_msg_to_smc(hwmgr->smumgr, @@ -55,7 +55,7 @@ int ellesmere_phm_powerdown_vce(struct pp_hwmgr *hwmgr) return 0; } -int ellesmere_phm_powerup_vce(struct pp_hwmgr *hwmgr) +int polaris10_phm_powerup_vce(struct pp_hwmgr *hwmgr) { if (phm_cf_want_vce_power_gating(hwmgr)) return smum_send_msg_to_smc(hwmgr->smumgr, @@ -63,7 +63,7 @@ int ellesmere_phm_powerup_vce(struct pp_hwmgr *hwmgr) return 0; } -int ellesmere_phm_powerdown_samu(struct pp_hwmgr *hwmgr) +int polaris10_phm_powerdown_samu(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SamuPowerGating)) @@ -72,7 +72,7 @@ int ellesmere_phm_powerdown_samu(struct pp_hwmgr *hwmgr) return 0; } -int ellesmere_phm_powerup_samu(struct pp_hwmgr *hwmgr) +int polaris10_phm_powerup_samu(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SamuPowerGating)) @@ -81,24 +81,24 @@ int ellesmere_phm_powerup_samu(struct pp_hwmgr *hwmgr) return 0; } -int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr) +int polaris10_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); data->uvd_power_gated = false; data->vce_power_gated = false; data->samu_power_gated = false; - ellesmere_phm_powerup_uvd(hwmgr); - ellesmere_phm_powerup_vce(hwmgr); - ellesmere_phm_powerup_samu(hwmgr); + polaris10_phm_powerup_uvd(hwmgr); + polaris10_phm_powerup_vce(hwmgr); + polaris10_phm_powerup_samu(hwmgr); return 0; } -int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) +int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); if (data->uvd_power_gated == bgate) return 0; @@ -106,34 +106,34 @@ int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate) data->uvd_power_gated = bgate; if (bgate) { - ellesmere_update_uvd_dpm(hwmgr, true); - ellesmere_phm_powerdown_uvd(hwmgr); + polaris10_update_uvd_dpm(hwmgr, true); + polaris10_phm_powerdown_uvd(hwmgr); } else { - ellesmere_phm_powerup_uvd(hwmgr); - ellesmere_update_uvd_dpm(hwmgr, false); + polaris10_phm_powerup_uvd(hwmgr); + polaris10_update_uvd_dpm(hwmgr, false); } return 0; } -int ellesmere_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) +int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); if (data->vce_power_gated == bgate) return 0; if (bgate) - ellesmere_phm_powerdown_vce(hwmgr); + polaris10_phm_powerdown_vce(hwmgr); else - ellesmere_phm_powerup_vce(hwmgr); + polaris10_phm_powerup_vce(hwmgr); return 0; } -int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate) +int polaris10_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); if (data->samu_power_gated == bgate) return 0; @@ -141,17 +141,17 @@ int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate) data->samu_power_gated = bgate; if (bgate) { - ellesmere_update_samu_dpm(hwmgr, true); - ellesmere_phm_powerdown_samu(hwmgr); + polaris10_update_samu_dpm(hwmgr, true); + polaris10_phm_powerdown_samu(hwmgr); } else { - ellesmere_phm_powerup_samu(hwmgr); - ellesmere_update_samu_dpm(hwmgr, false); + polaris10_phm_powerup_samu(hwmgr); + polaris10_update_samu_dpm(hwmgr, false); } return 0; } -int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr, +int polaris10_phm_update_clock_gatings(struct pp_hwmgr *hwmgr, const uint32_t *msg_id) { PPSMC_Msg msg; @@ -399,11 +399,11 @@ int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr, return 0; } -/* This function is for Baffin only for now, +/* This function is for Polaris11 only for now, * Powerplay will only control the static per CU Power Gating. * Dynamic per CU Power Gating will be done in gfx. */ -int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable) +int polaris10_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable) { struct cgs_system_info sys_info = {0}; uint32_t active_cus; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h index b403e1112f04..88d68cb6e89d 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_clockpowergating.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_clockpowergating.h @@ -21,20 +21,20 @@ * */ -#ifndef _ELLESMERE_CLOCK_POWER_GATING_H_ -#define _ELLESMERE_CLOCK_POWER_GATING_H_ +#ifndef _POLARIS10_CLOCK_POWER_GATING_H_ +#define _POLARIS10_CLOCK_POWER_GATING_H_ -#include "ellesmere_hwmgr.h" +#include "polaris10_hwmgr.h" #include "pp_asicblocks.h" -int ellesmere_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); -int ellesmere_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); -int ellesmere_phm_powerdown_uvd(struct pp_hwmgr *hwmgr); -int ellesmere_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate); -int ellesmere_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate); -int ellesmere_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr); -int ellesmere_phm_update_clock_gatings(struct pp_hwmgr *hwmgr, +int polaris10_phm_powergate_vce(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_phm_powergate_uvd(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_phm_powerdown_uvd(struct pp_hwmgr *hwmgr); +int polaris10_phm_powergate_samu(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_phm_powergate_acp(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_phm_disable_clock_power_gating(struct pp_hwmgr *hwmgr); +int polaris10_phm_update_clock_gatings(struct pp_hwmgr *hwmgr, const uint32_t *msg_id); -int ellesmere_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable); +int polaris10_phm_enable_per_cu_power_gating(struct pp_hwmgr *hwmgr, bool enable); -#endif /* _ELLESMERE_CLOCK_POWER_GATING_H_ */ +#endif /* _POLARIS10_CLOCK_POWER_GATING_H_ */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h new file mode 100644 index 000000000000..f78ffd935cee --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_dyn_defaults.h @@ -0,0 +1,62 @@ +/* + * Copyright 2015 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ + +#ifndef POLARIS10_DYN_DEFAULTS_H +#define POLARIS10_DYN_DEFAULTS_H + + +enum Polaris10dpm_TrendDetection { + Polaris10Adpm_TrendDetection_AUTO, + Polaris10Adpm_TrendDetection_UP, + Polaris10Adpm_TrendDetection_DOWN +}; +typedef enum Polaris10dpm_TrendDetection Polaris10dpm_TrendDetection; + +/* We need to fill in the default values */ + + +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0 0x3FFFC102 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1 0x000400 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2 0xC00080 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3 0xC00200 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4 0xC01680 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5 0xC00033 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6 0xC00033 +#define PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7 0x3FFFC000 + + +#define PPPOLARIS10_THERMALPROTECTCOUNTER_DFLT 0x200 +#define PPPOLARIS10_STATICSCREENTHRESHOLDUNIT_DFLT 0 +#define PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT 0x00C8 +#define PPPOLARIS10_GFXIDLECLOCKSTOPTHRESHOLD_DFLT 0x200 +#define PPPOLARIS10_REFERENCEDIVIDER_DFLT 4 + +#define PPPOLARIS10_ULVVOLTAGECHANGEDELAY_DFLT 1687 + +#define PPPOLARIS10_CGULVPARAMETER_DFLT 0x00040035 +#define PPPOLARIS10_CGULVCONTROL_DFLT 0x00007450 +#define PPPOLARIS10_TARGETACTIVITY_DFLT 50 +#define PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT 10 + +#endif + diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c index 152d77d8d3fc..5080d672d899 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.c @@ -26,10 +26,10 @@ #include "linux/delay.h" #include "pp_acpi.h" #include "hwmgr.h" -#include "ellesmere_hwmgr.h" -#include "ellesmere_powertune.h" -#include "ellesmere_dyn_defaults.h" -#include "ellesmere_smumgr.h" +#include "polaris10_hwmgr.h" +#include "polaris10_powertune.h" +#include "polaris10_dyn_defaults.h" +#include "polaris10_smumgr.h" #include "pp_debug.h" #include "ppatomctrl.h" #include "atombios.h" @@ -57,8 +57,8 @@ #include "dce/dce_10_0_d.h" #include "dce/dce_10_0_sh_mask.h" -#include "ellesmere_thermal.h" -#include "ellesmere_clockpowergating.h" +#include "polaris10_thermal.h" +#include "polaris10_clockpowergating.h" #define MC_CG_ARB_FREQ_F0 0x0a #define MC_CG_ARB_FREQ_F1 0x0b @@ -98,15 +98,15 @@ #define TCLK (PCIE_BUS_CLK / 10) -uint16_t ellesmere_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0}, +uint16_t polaris10_clock_stretcher_lookup_table[2][4] = { {600, 1050, 3, 0}, {600, 1050, 6, 1} }; /* [FF, SS] type, [] 4 voltage ranges, and [Floor Freq, Boundary Freq, VID min , VID max] */ -uint32_t ellesmere_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} }, +uint32_t polaris10_clock_stretcher_ddt_table[2][4][4] = { { {265, 529, 120, 128}, {325, 650, 96, 119}, {430, 860, 32, 95}, {0, 0, 0, 31} }, { {275, 550, 104, 112}, {319, 638, 96, 103}, {360, 720, 64, 95}, {384, 768, 32, 63} } }; /* [Use_For_Low_freq] value, [0%, 5%, 10%, 7.14%, 14.28%, 20%] (coming from PWR_CKS_CNTL.stretch_amount reg spec) */ -uint8_t ellesmere_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5}, +uint8_t polaris10_clock_stretch_amount_conversion[2][6] = { {0, 1, 3, 2, 4, 5}, {0, 2, 4, 5, 6, 5} }; /** Values for the CG_THERMAL_CTRL::DPM_EVENT_SRC field. */ @@ -118,29 +118,29 @@ enum DPM_EVENT_SRC { DPM_EVENT_SRC_DIGITAL_OR_EXTERNAL = 4 }; -const unsigned long PhwEllesmere_Magic = (unsigned long)(PHM_VIslands_Magic); +const unsigned long PhwPolaris10_Magic = (unsigned long)(PHM_VIslands_Magic); -struct ellesmere_power_state *cast_phw_ellesmere_power_state( +struct polaris10_power_state *cast_phw_polaris10_power_state( struct pp_hw_power_state *hw_ps) { - PP_ASSERT_WITH_CODE((PhwEllesmere_Magic == hw_ps->magic), + PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic), "Invalid Powerstate Type!", return NULL); - return (struct ellesmere_power_state *)hw_ps; + return (struct polaris10_power_state *)hw_ps; } -const struct ellesmere_power_state *cast_const_phw_ellesmere_power_state( +const struct polaris10_power_state *cast_const_phw_polaris10_power_state( const struct pp_hw_power_state *hw_ps) { - PP_ASSERT_WITH_CODE((PhwEllesmere_Magic == hw_ps->magic), + PP_ASSERT_WITH_CODE((PhwPolaris10_Magic == hw_ps->magic), "Invalid Powerstate Type!", return NULL); - return (const struct ellesmere_power_state *)hw_ps; + return (const struct polaris10_power_state *)hw_ps; } -static bool ellesmere_is_dpm_running(struct pp_hwmgr *hwmgr) +static bool polaris10_is_dpm_running(struct pp_hwmgr *hwmgr) { return (1 == PHM_READ_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, FEATURE_STATUS, VOLTAGE_CONTROLLER_ON)) @@ -228,7 +228,7 @@ void phm_apply_dal_min_voltage_request(struct pp_hwmgr *hwmgr) * @param pHwMgr the address of the powerplay hardware manager. * @return always PP_Result_OK */ -int ellesmere_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) +int polaris10_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) { PP_ASSERT_WITH_CODE( (hwmgr->smumgr->smumgr_funcs->send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_Voltage_Cntl_Enable) == 0), @@ -244,12 +244,12 @@ int ellesmere_enable_smc_voltage_controller(struct pp_hwmgr *hwmgr) * * @param hwmgr the address of the powerplay hardware manager. */ -static bool ellesmere_voltage_control(const struct pp_hwmgr *hwmgr) +static bool polaris10_voltage_control(const struct pp_hwmgr *hwmgr) { - const struct ellesmere_hwmgr *data = - (const struct ellesmere_hwmgr *)(hwmgr->backend); + const struct polaris10_hwmgr *data = + (const struct polaris10_hwmgr *)(hwmgr->backend); - return (ELLESMERE_VOLTAGE_CONTROL_NONE != data->voltage_control); + return (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control); } /** @@ -258,7 +258,7 @@ static bool ellesmere_voltage_control(const struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_enable_voltage_control(struct pp_hwmgr *hwmgr) +static int polaris10_enable_voltage_control(struct pp_hwmgr *hwmgr) { /* enable voltage control */ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, @@ -273,21 +273,21 @@ static int ellesmere_enable_voltage_control(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_construct_voltage_tables(struct pp_hwmgr *hwmgr) +static int polaris10_construct_voltage_tables(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)hwmgr->pptable; int result; - if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { + if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { result = atomctrl_get_voltage_table_v3(hwmgr, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT, &(data->mvdd_voltage_table)); PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve MVDD table.", return result); - } else if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { + } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { result = phm_get_svi2_mvdd_voltage_table(&(data->mvdd_voltage_table), table_info->vdd_dep_on_mclk); PP_ASSERT_WITH_CODE((0 == result), @@ -295,14 +295,14 @@ static int ellesmere_construct_voltage_tables(struct pp_hwmgr *hwmgr) return result;); } - if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { + if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { result = atomctrl_get_voltage_table_v3(hwmgr, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT, &(data->vddci_voltage_table)); PP_ASSERT_WITH_CODE((0 == result), "Failed to retrieve VDDCI table.", return result); - } else if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { + } else if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { result = phm_get_svi2_vddci_voltage_table(&(data->vddci_voltage_table), table_info->vdd_dep_on_mclk); PP_ASSERT_WITH_CODE((0 == result), @@ -310,7 +310,7 @@ static int ellesmere_construct_voltage_tables(struct pp_hwmgr *hwmgr) return result); } - if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { + if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { result = phm_get_svi2_vdd_voltage_table(&(data->vddc_voltage_table), table_info->vddc_lookup_table); PP_ASSERT_WITH_CODE((0 == result), @@ -345,10 +345,10 @@ static int ellesmere_construct_voltage_tables(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_program_static_screen_threshold_parameters( +static int polaris10_program_static_screen_threshold_parameters( struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); /* Set static screen threshold unit */ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, @@ -368,7 +368,7 @@ static int ellesmere_program_static_screen_threshold_parameters( * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_enable_display_gap(struct pp_hwmgr *hwmgr) +static int polaris10_enable_display_gap(struct pp_hwmgr *hwmgr) { uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, @@ -392,9 +392,9 @@ static int ellesmere_enable_display_gap(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_program_voting_clients(struct pp_hwmgr *hwmgr) +static int polaris10_program_voting_clients(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); /* Clear reset for voting clients before enabling DPM */ PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, @@ -428,15 +428,15 @@ static int ellesmere_program_voting_clients(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_process_firmware_header(struct pp_hwmgr *hwmgr) +static int polaris10_process_firmware_header(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(hwmgr->smumgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(hwmgr->smumgr->backend); uint32_t tmp; int result; bool error = false; - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable), &tmp, data->sram_end); @@ -446,7 +446,7 @@ static int ellesmere_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters), &tmp, data->sram_end); @@ -458,7 +458,7 @@ static int ellesmere_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, mcRegisterTable), &tmp, data->sram_end); @@ -466,7 +466,7 @@ static int ellesmere_process_firmware_header(struct pp_hwmgr *hwmgr) if (!result) data->mc_reg_table_start = tmp; - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, FanTable), &tmp, data->sram_end); @@ -476,7 +476,7 @@ static int ellesmere_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, mcArbDramTimingTable), &tmp, data->sram_end); @@ -486,7 +486,7 @@ static int ellesmere_process_firmware_header(struct pp_hwmgr *hwmgr) error |= (0 != result); - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, Version), &tmp, data->sram_end); @@ -502,7 +502,7 @@ static int ellesmere_process_firmware_header(struct pp_hwmgr *hwmgr) /* Copy one arb setting to another and then switch the active set. * arb_src and arb_dest is one of the MC_CG_ARB_FREQ_Fx constants. */ -static int ellesmere_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, +static int polaris10_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, uint32_t arb_src, uint32_t arb_dest) { uint32_t mc_arb_dram_timing; @@ -555,15 +555,15 @@ static int ellesmere_copy_and_switch_arb_sets(struct pp_hwmgr *hwmgr, * @return always 0 * This function is to be called from the SetPowerState table. */ -static int ellesmere_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) +static int polaris10_initial_switch_from_arbf0_to_f1(struct pp_hwmgr *hwmgr) { - return ellesmere_copy_and_switch_arb_sets(hwmgr, + return polaris10_copy_and_switch_arb_sets(hwmgr, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1); } -static int ellesmere_setup_default_pcie_table(struct pp_hwmgr *hwmgr) +static int polaris10_setup_default_pcie_table(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; @@ -660,9 +660,9 @@ static int ellesmere_setup_default_pcie_table(struct pp_hwmgr *hwmgr) * on the power policy or external client requests, * such as UVD request, etc. */ -int ellesmere_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) +int polaris10_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); uint32_t i; @@ -725,11 +725,11 @@ int ellesmere_setup_default_dpm_tables(struct pp_hwmgr *hwmgr) } /* setup PCIE gen speed levels */ - ellesmere_setup_default_pcie_table(hwmgr); + polaris10_setup_default_pcie_table(hwmgr); /* save a copy of the default DPM table */ memcpy(&(data->golden_dpm_table), &(data->dpm_table), - sizeof(struct ellesmere_dpm_table)); + sizeof(struct polaris10_dpm_table)); return 0; } @@ -746,13 +746,13 @@ uint8_t convert_to_vid(uint16_t vddc) * @param *table The SMC DPM table structure to be populated. * @return 0 */ -static int ellesmere_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, +static int polaris10_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, SMU74_Discrete_DpmTable *table) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint32_t count, level; - if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { + if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { count = data->mvdd_voltage_table.count; if (count > SMU_MAX_SMIO_LEVELS) count = SMU_MAX_SMIO_LEVELS; @@ -773,15 +773,15 @@ static int ellesmere_populate_smc_mvdd_table(struct pp_hwmgr *hwmgr, return 0; } -static int ellesmere_populate_smc_vddci_table(struct pp_hwmgr *hwmgr, +static int polaris10_populate_smc_vddci_table(struct pp_hwmgr *hwmgr, struct SMU74_Discrete_DpmTable *table) { uint32_t count, level; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); count = data->vddci_voltage_table.count; - if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { + if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { if (count > SMU_MAX_SMIO_LEVELS) count = SMU_MAX_SMIO_LEVELS; for (level = 0; level < count; ++level) { @@ -805,12 +805,12 @@ static int ellesmere_populate_smc_vddci_table(struct pp_hwmgr *hwmgr, * @param table the SMC DPM table structure to be populated * @return always 0 */ -static int ellesmere_populate_cac_table(struct pp_hwmgr *hwmgr, +static int polaris10_populate_cac_table(struct pp_hwmgr *hwmgr, struct SMU74_Discrete_DpmTable *table) { uint32_t count; uint8_t index; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); struct phm_ppt_v1_voltage_lookup_table *lookup_table = @@ -839,20 +839,20 @@ static int ellesmere_populate_cac_table(struct pp_hwmgr *hwmgr, * @return always 0 */ -int ellesmere_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, +int polaris10_populate_smc_voltage_tables(struct pp_hwmgr *hwmgr, struct SMU74_Discrete_DpmTable *table) { - ellesmere_populate_smc_vddci_table(hwmgr, table); - ellesmere_populate_smc_mvdd_table(hwmgr, table); - ellesmere_populate_cac_table(hwmgr, table); + polaris10_populate_smc_vddci_table(hwmgr, table); + polaris10_populate_smc_mvdd_table(hwmgr, table); + polaris10_populate_cac_table(hwmgr, table); return 0; } -static int ellesmere_populate_ulv_level(struct pp_hwmgr *hwmgr, +static int polaris10_populate_ulv_level(struct pp_hwmgr *hwmgr, struct SMU74_Discrete_Ulv *state) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -872,17 +872,17 @@ static int ellesmere_populate_ulv_level(struct pp_hwmgr *hwmgr, return 0; } -static int ellesmere_populate_ulv_state(struct pp_hwmgr *hwmgr, +static int polaris10_populate_ulv_state(struct pp_hwmgr *hwmgr, struct SMU74_Discrete_DpmTable *table) { - return ellesmere_populate_ulv_level(hwmgr, &table->Ulv); + return polaris10_populate_ulv_level(hwmgr, &table->Ulv); } -static int ellesmere_populate_smc_link_level(struct pp_hwmgr *hwmgr, +static int polaris10_populate_smc_link_level(struct pp_hwmgr *hwmgr, struct SMU74_Discrete_DpmTable *table) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_dpm_table *dpm_table = &data->dpm_table; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_dpm_table *dpm_table = &data->dpm_table; int i; /* Index (dpm_table->pcie_speed_table.count) @@ -906,7 +906,7 @@ static int ellesmere_populate_smc_link_level(struct pp_hwmgr *hwmgr, return 0; } -static uint32_t ellesemere_get_xclk(struct pp_hwmgr *hwmgr) +static uint32_t polaris10_get_xclk(struct pp_hwmgr *hwmgr) { uint32_t reference_clock, tmp; struct cgs_display_info info = {0}; @@ -937,10 +937,10 @@ static uint32_t ellesemere_get_xclk(struct pp_hwmgr *hwmgr) * @param clock the engine clock to use to populate the structure * @param sclk the SMC SCLK structure to be populated */ -static int ellesmere_calculate_sclk_params(struct pp_hwmgr *hwmgr, +static int polaris10_calculate_sclk_params(struct pp_hwmgr *hwmgr, uint32_t clock, SMU_SclkSetting *sclk_setting) { - const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); const SMU74_Discrete_DpmTable *table = &(data->smc_state_table); struct pp_atomctrl_clock_dividers_ai dividers; @@ -968,7 +968,7 @@ static int ellesmere_calculate_sclk_params(struct pp_hwmgr *hwmgr, return result; } - ref_clock = ellesemere_get_xclk(hwmgr); + ref_clock = polaris10_get_xclk(hwmgr); for (i = 0; i < NUM_SCLK_RANGE; i++) { if (clock > data->range_table[i].trans_lower_frequency @@ -1001,13 +1001,13 @@ static int ellesmere_calculate_sclk_params(struct pp_hwmgr *hwmgr, return 0; } -static int ellesmere_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, +static int polaris10_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, struct phm_ppt_v1_clock_voltage_dependency_table *dep_table, uint32_t clock, SMU_VoltageLevel *voltage, uint32_t *mvdd) { uint32_t i; uint16_t vddci; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); *voltage = *mvdd = 0; @@ -1020,7 +1020,7 @@ static int ellesmere_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, if (dep_table->entries[i].clk >= clock) { *voltage |= (dep_table->entries[i].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; - if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->vddci_control) + if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control) *voltage |= (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT; else if (dep_table->entries[i].vddci) @@ -1033,7 +1033,7 @@ static int ellesmere_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; } - if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control) + if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE; else if (dep_table->entries[i].mvdd) @@ -1048,7 +1048,7 @@ static int ellesmere_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, /* sclk is bigger than max sclk in the dependence table */ *voltage |= (dep_table->entries[i - 1].vddc * VOLTAGE_SCALE) << VDDC_SHIFT; - if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->vddci_control) + if (POLARIS10_VOLTAGE_CONTROL_NONE == data->vddci_control) *voltage |= (data->vbios_boot_state.vddci_bootup_value * VOLTAGE_SCALE) << VDDCI_SHIFT; else if (dep_table->entries[i-1].vddci) { @@ -1058,7 +1058,7 @@ static int ellesmere_get_dependency_volt_by_clk(struct pp_hwmgr *hwmgr, *voltage |= (vddci * VOLTAGE_SCALE) << VDDCI_SHIFT; } - if (ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control) + if (POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) *mvdd = data->vbios_boot_state.mvdd_bootup_value * VOLTAGE_SCALE; else if (dep_table->entries[i].mvdd) *mvdd = (uint32_t) dep_table->entries[i - 1].mvdd * VOLTAGE_SCALE; @@ -1075,14 +1075,14 @@ sclkFcwRange_t Range_Table[NUM_SCLK_RANGE] = { {VCO_2_4, POSTDIV_DIV_BY_16, 75, {VCO_2_4, POSTDIV_DIV_BY_2, 75, 160, 108}, {VCO_3_6, POSTDIV_DIV_BY_2, 112, 216, 160} }; -static void ellesmere_get_sclk_range_table(struct pp_hwmgr *hwmgr) +static void polaris10_get_sclk_range_table(struct pp_hwmgr *hwmgr) { uint32_t i, ref_clk; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); SMU74_Discrete_DpmTable *table = &(data->smc_state_table); struct pp_atom_ctrl_sclk_range_table range_table_from_vbios = { { {0} } }; - ref_clk = ellesemere_get_xclk(hwmgr); + ref_clk = polaris10_get_xclk(hwmgr); if (0 == atomctrl_get_smc_sclk_range_table(hwmgr, &range_table_from_vbios)) { for (i = 0; i < NUM_SCLK_RANGE; i++) { @@ -1126,22 +1126,22 @@ static void ellesmere_get_sclk_range_table(struct pp_hwmgr *hwmgr) * @param sclk the SMC SCLK structure to be populated */ -static int ellesmere_populate_single_graphic_level(struct pp_hwmgr *hwmgr, +static int polaris10_populate_single_graphic_level(struct pp_hwmgr *hwmgr, uint32_t clock, uint16_t sclk_al_threshold, struct SMU74_Discrete_GraphicsLevel *level) { int result, i, temp; /* PP_Clocks minClocks; */ uint32_t mvdd; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); SMU_SclkSetting curr_sclk_setting = { 0 }; - result = ellesmere_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting); + result = polaris10_calculate_sclk_params(hwmgr, clock, &curr_sclk_setting); /* populate graphics levels */ - result = ellesmere_get_dependency_volt_by_clk(hwmgr, + result = polaris10_get_dependency_volt_by_clk(hwmgr, table_info->vdd_dep_on_sclk, clock, &level->MinVoltage, &mvdd); @@ -1171,7 +1171,7 @@ static int ellesmere_populate_single_graphic_level(struct pp_hwmgr *hwmgr, level->DeepSleepDivId = PhwFiji_GetSleepDividerIdFromClock(hwmgr, clock, minClocks.engineClockInSR); */ PP_ASSERT_WITH_CODE((clock >= 2500), "Engine clock can't satisfy stutter requirement!", return 0); - for (i = ELLESMERE_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { + for (i = POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) { temp = clock / (1UL << i); if (temp >= 2500 || i == 0) @@ -1212,10 +1212,10 @@ static int ellesmere_populate_single_graphic_level(struct pp_hwmgr *hwmgr, * * @param hwmgr the address of the hardware manager */ -static int ellesmere_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) +static int polaris10_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_dpm_table *dpm_table = &data->dpm_table; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_dpm_table *dpm_table = &data->dpm_table; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); struct phm_ppt_v1_pcie_table *pcie_table = table_info->pcie_table; @@ -1233,11 +1233,11 @@ static int ellesmere_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) mid_pcie_level_enabled = 0, count = 0; - ellesmere_get_sclk_range_table(hwmgr); + polaris10_get_sclk_range_table(hwmgr); for (i = 0; i < dpm_table->sclk_table.count; i++) { - result = ellesmere_populate_single_graphic_level(hwmgr, + result = polaris10_populate_single_graphic_level(hwmgr, dpm_table->sclk_table.dpm_levels[i].value, (uint16_t)data->activity_target[i], &(data->smc_state_table.GraphicsLevel[i])); @@ -1296,16 +1296,16 @@ static int ellesmere_populate_all_graphic_levels(struct pp_hwmgr *hwmgr) levels[1].pcieDpmLevel = mid_pcie_level_enabled; } /* level count will send to smc once at init smc table and never change */ - result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, + result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, (uint32_t)array_size, data->sram_end); return result; } -static int ellesmere_populate_single_memory_level(struct pp_hwmgr *hwmgr, +static int polaris10_populate_single_memory_level(struct pp_hwmgr *hwmgr, uint32_t clock, struct SMU74_Discrete_MemoryLevel *mem_level) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); int result = 0; @@ -1314,7 +1314,7 @@ static int ellesmere_populate_single_memory_level(struct pp_hwmgr *hwmgr, cgs_get_active_displays_info(hwmgr->device, &info); if (table_info->vdd_dep_on_mclk) { - result = ellesmere_get_dependency_volt_by_clk(hwmgr, + result = polaris10_get_dependency_volt_by_clk(hwmgr, table_info->vdd_dep_on_mclk, clock, &mem_level->MinVoltage, &mem_level->MinMvdd); PP_ASSERT_WITH_CODE((0 == result), @@ -1356,10 +1356,10 @@ static int ellesmere_populate_single_memory_level(struct pp_hwmgr *hwmgr, * * @param hwmgr the address of the hardware manager */ -static int ellesmere_populate_all_memory_levels(struct pp_hwmgr *hwmgr) +static int polaris10_populate_all_memory_levels(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_dpm_table *dpm_table = &data->dpm_table; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_dpm_table *dpm_table = &data->dpm_table; int result; /* populate MCLK dpm table to SMU7 */ uint32_t array = data->dpm_table_start + @@ -1374,7 +1374,7 @@ static int ellesmere_populate_all_memory_levels(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE((0 != dpm_table->mclk_table.dpm_levels[i].value), "can not populate memory level as memory clock is zero", return -EINVAL); - result = ellesmere_populate_single_memory_level(hwmgr, + result = polaris10_populate_single_memory_level(hwmgr, dpm_table->mclk_table.dpm_levels[i].value, &levels[i]); if (result) @@ -1401,7 +1401,7 @@ static int ellesmere_populate_all_memory_levels(struct pp_hwmgr *hwmgr) PPSMC_DISPLAY_WATERMARK_HIGH; /* level count will send to smc once at init smc table and never change */ - result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, + result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, array, (uint8_t *)levels, (uint32_t)array_size, data->sram_end); return result; @@ -1414,15 +1414,15 @@ static int ellesmere_populate_all_memory_levels(struct pp_hwmgr *hwmgr) * @param mclk the MCLK value to be used in the decision if MVDD should be high or low. * @param voltage the SMC VOLTAGE structure to be populated */ -int ellesmere_populate_mvdd_value(struct pp_hwmgr *hwmgr, +int polaris10_populate_mvdd_value(struct pp_hwmgr *hwmgr, uint32_t mclk, SMIO_Pattern *smio_pat) { - const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); uint32_t i = 0; - if (ELLESMERE_VOLTAGE_CONTROL_NONE != data->mvdd_control) { + if (POLARIS10_VOLTAGE_CONTROL_NONE != data->mvdd_control) { /* find mvdd value which clock is more than request */ for (i = 0; i < table_info->vdd_dep_on_mclk->count; i++) { if (mclk <= table_info->vdd_dep_on_mclk->entries[i].clk) { @@ -1439,12 +1439,12 @@ int ellesmere_populate_mvdd_value(struct pp_hwmgr *hwmgr, return 0; } -static int ellesmere_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, +static int polaris10_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, SMU74_Discrete_DpmTable *table) { int result = 0; uint32_t sclk_frequency; - const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); SMIO_Pattern vol_level; @@ -1457,7 +1457,7 @@ static int ellesmere_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, /* Get MinVoltage and Frequency from DPM0, * already converted to SMC_UL */ sclk_frequency = data->dpm_table.sclk_table.dpm_levels[0].value; - result = ellesmere_get_dependency_volt_by_clk(hwmgr, + result = polaris10_get_dependency_volt_by_clk(hwmgr, table_info->vdd_dep_on_sclk, table->ACPILevel.SclkFrequency, &table->ACPILevel.MinVoltage, &mvdd); @@ -1470,7 +1470,7 @@ static int ellesmere_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, data->vbios_boot_state.vddc_bootup_value * VOLTAGE_SCALE; } - result = ellesmere_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting)); + result = polaris10_calculate_sclk_params(hwmgr, sclk_frequency, &(table->ACPILevel.SclkSetting)); PP_ASSERT_WITH_CODE(result == 0, "Error retrieving Engine Clock dividers from VBIOS.", return result); table->ACPILevel.DeepSleepDivId = 0; @@ -1497,7 +1497,7 @@ static int ellesmere_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, /* Get MinVoltage and Frequency from DPM0, already converted to SMC_UL */ table->MemoryACPILevel.MclkFrequency = data->dpm_table.mclk_table.dpm_levels[0].value; - result = ellesmere_get_dependency_volt_by_clk(hwmgr, + result = polaris10_get_dependency_volt_by_clk(hwmgr, table_info->vdd_dep_on_mclk, table->MemoryACPILevel.MclkFrequency, &table->MemoryACPILevel.MinVoltage, &mvdd); @@ -1513,17 +1513,17 @@ static int ellesmere_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, } us_mvdd = 0; - if ((ELLESMERE_VOLTAGE_CONTROL_NONE == data->mvdd_control) || + if ((POLARIS10_VOLTAGE_CONTROL_NONE == data->mvdd_control) || (data->mclk_dpm_key_disabled)) us_mvdd = data->vbios_boot_state.mvdd_bootup_value; else { - if (!ellesmere_populate_mvdd_value(hwmgr, + if (!polaris10_populate_mvdd_value(hwmgr, data->dpm_table.mclk_table.dpm_levels[0].value, &vol_level)) us_mvdd = vol_level.Voltage; } - if (0 == ellesmere_populate_mvdd_value(hwmgr, 0, &vol_level)) + if (0 == polaris10_populate_mvdd_value(hwmgr, 0, &vol_level)) table->MemoryACPILevel.MinMvdd = PP_HOST_TO_SMC_UL(vol_level.Voltage); else table->MemoryACPILevel.MinMvdd = 0; @@ -1544,7 +1544,7 @@ static int ellesmere_populate_smc_acpi_level(struct pp_hwmgr *hwmgr, return result; } -static int ellesmere_populate_smc_vce_level(struct pp_hwmgr *hwmgr, +static int polaris10_populate_smc_vce_level(struct pp_hwmgr *hwmgr, SMU74_Discrete_DpmTable *table) { int result = -EINVAL; @@ -1554,7 +1554,7 @@ static int ellesmere_populate_smc_vce_level(struct pp_hwmgr *hwmgr, (struct phm_ppt_v1_information *)(hwmgr->pptable); struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = table_info->mm_dep_table; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); table->VceLevelCount = (uint8_t)(mm_table->count); table->VceBootLevel = 0; @@ -1583,7 +1583,7 @@ static int ellesmere_populate_smc_vce_level(struct pp_hwmgr *hwmgr, return result; } -static int ellesmere_populate_smc_samu_level(struct pp_hwmgr *hwmgr, +static int polaris10_populate_smc_samu_level(struct pp_hwmgr *hwmgr, SMU74_Discrete_DpmTable *table) { int result = -EINVAL; @@ -1593,7 +1593,7 @@ static int ellesmere_populate_smc_samu_level(struct pp_hwmgr *hwmgr, (struct phm_ppt_v1_information *)(hwmgr->pptable); struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = table_info->mm_dep_table; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); table->SamuBootLevel = 0; table->SamuLevelCount = (uint8_t)(mm_table->count); @@ -1621,7 +1621,7 @@ static int ellesmere_populate_smc_samu_level(struct pp_hwmgr *hwmgr, return result; } -static int ellesmere_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, +static int polaris10_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, int32_t eng_clock, int32_t mem_clock, SMU74_Discrete_MCArbDramTimingTableEntry *arb_regs) { @@ -1647,16 +1647,16 @@ static int ellesmere_populate_memory_timing_parameters(struct pp_hwmgr *hwmgr, return 0; } -static int ellesmere_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) +static int polaris10_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct SMU74_Discrete_MCArbDramTimingTable arb_regs; uint32_t i, j; int result = 0; for (i = 0; i < data->dpm_table.sclk_table.count; i++) { for (j = 0; j < data->dpm_table.mclk_table.count; j++) { - result = ellesmere_populate_memory_timing_parameters(hwmgr, + result = polaris10_populate_memory_timing_parameters(hwmgr, data->dpm_table.sclk_table.dpm_levels[i].value, data->dpm_table.mclk_table.dpm_levels[j].value, &arb_regs.entries[i][j]); @@ -1667,7 +1667,7 @@ static int ellesmere_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) } } - result = ellesmere_copy_bytes_to_smc( + result = polaris10_copy_bytes_to_smc( hwmgr->smumgr, data->arb_table_start, (uint8_t *)&arb_regs, @@ -1676,7 +1676,7 @@ static int ellesmere_program_memory_timing_parameters(struct pp_hwmgr *hwmgr) return result; } -static int ellesmere_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, +static int polaris10_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, struct SMU74_Discrete_DpmTable *table) { int result = -EINVAL; @@ -1686,7 +1686,7 @@ static int ellesmere_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, (struct phm_ppt_v1_information *)(hwmgr->pptable); struct phm_ppt_v1_mm_clock_voltage_dependency_table *mm_table = table_info->mm_dep_table; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); table->UvdLevelCount = (uint8_t)(mm_table->count); table->UvdBootLevel = 0; @@ -1723,11 +1723,11 @@ static int ellesmere_populate_smc_uvd_level(struct pp_hwmgr *hwmgr, return result; } -static int ellesmere_populate_smc_boot_level(struct pp_hwmgr *hwmgr, +static int polaris10_populate_smc_boot_level(struct pp_hwmgr *hwmgr, struct SMU74_Discrete_DpmTable *table) { int result = 0; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); table->GraphicsBootLevel = 0; table->MemoryBootLevel = 0; @@ -1756,9 +1756,9 @@ static int ellesmere_populate_smc_boot_level(struct pp_hwmgr *hwmgr, } -static int ellesmere_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) +static int polaris10_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); uint8_t count, level; @@ -1785,12 +1785,12 @@ static int ellesmere_populate_smc_initailial_state(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) +static int polaris10_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) { uint32_t ro, efuse, efuse2, clock_freq, volt_without_cks, volt_with_cks, value; uint16_t clock_freq_u16; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint8_t type, i, j, cks_setting, stretch_amount, stretch_amount2, volt_offset = 0; struct phm_ppt_v1_information *table_info = @@ -1865,28 +1865,28 @@ static int ellesmere_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) ixPWR_CKS_CNTL); value &= 0xFFC2FF87; data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq = - ellesmere_clock_stretcher_lookup_table[stretch_amount2][0]; + polaris10_clock_stretcher_lookup_table[stretch_amount2][0]; data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq = - ellesmere_clock_stretcher_lookup_table[stretch_amount2][1]; + polaris10_clock_stretcher_lookup_table[stretch_amount2][1]; clock_freq_u16 = (uint16_t)(PP_SMC_TO_HOST_UL(data->smc_state_table. GraphicsLevel[data->smc_state_table.GraphicsDpmLevelCount - 1].SclkSetting.SclkFrequency) / 100); - if (ellesmere_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16 - && ellesmere_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) { + if (polaris10_clock_stretcher_lookup_table[stretch_amount2][0] < clock_freq_u16 + && polaris10_clock_stretcher_lookup_table[stretch_amount2][1] > clock_freq_u16) { /* Program PWR_CKS_CNTL. CKS_USE_FOR_LOW_FREQ */ - value |= (ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]) << 16; + value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 16; /* Program PWR_CKS_CNTL. CKS_LDO_REFSEL */ - value |= (ellesmere_clock_stretcher_lookup_table[stretch_amount2][2]) << 18; + value |= (polaris10_clock_stretcher_lookup_table[stretch_amount2][2]) << 18; /* Program PWR_CKS_CNTL. CKS_STRETCH_AMOUNT */ - value |= (ellesmere_clock_stretch_amount_conversion - [ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]] + value |= (polaris10_clock_stretch_amount_conversion + [polaris10_clock_stretcher_lookup_table[stretch_amount2][3]] [stretch_amount]) << 3; } CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].minFreq); CONVERT_FROM_HOST_TO_SMC_US(data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].maxFreq); data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting = - ellesmere_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F; + polaris10_clock_stretcher_lookup_table[stretch_amount2][2] & 0x7F; data->smc_state_table.CKS_LOOKUPTable.CKS_LOOKUPTableEntry[0].setting |= - (ellesmere_clock_stretcher_lookup_table[stretch_amount2][3]) << 7; + (polaris10_clock_stretcher_lookup_table[stretch_amount2][3]) << 7; cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixPWR_CKS_CNTL, value); @@ -1897,9 +1897,9 @@ static int ellesmere_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) * in the last row of Clock Stretcher Voltage Table. */ data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].minVID = - (uint8_t) ellesmere_clock_stretcher_ddt_table[type][i][2]; + (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][2]; data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].maxVID = - (uint8_t) ellesmere_clock_stretcher_ddt_table[type][i][3]; + (uint8_t) polaris10_clock_stretcher_ddt_table[type][i][3]; /* Loop through each SCLK and check the frequency * to see if it lies within the frequency for clock stretcher. */ @@ -1912,9 +1912,9 @@ static int ellesmere_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) * and it's in 10Khz unit, * as opposed to Data table, which is in Mhz unit. */ - if (clock_freq >= (ellesmere_clock_stretcher_ddt_table[type][i][0]) * 100) { + if (clock_freq >= (polaris10_clock_stretcher_ddt_table[type][i][0]) * 100) { cks_setting |= 0x2; - if (clock_freq < (ellesmere_clock_stretcher_ddt_table[type][i][1]) * 100) + if (clock_freq < (polaris10_clock_stretcher_ddt_table[type][i][1]) * 100) cks_setting |= 0x1; } data->smc_state_table.ClockStretcherDataTable.ClockStretcherDataTableEntry[i].setting @@ -1938,17 +1938,17 @@ static int ellesmere_populate_clock_stretcher_data_table(struct pp_hwmgr *hwmgr) * @param table the SMC DPM table structure to be populated * @return always 0 */ -static int ellesmere_populate_vr_config(struct pp_hwmgr *hwmgr, +static int polaris10_populate_vr_config(struct pp_hwmgr *hwmgr, struct SMU74_Discrete_DpmTable *table) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint16_t config; config = VR_MERGED_WITH_VDDC; table->VRConfig |= (config << VRCONF_VDDGFX_SHIFT); /* Set Vddc Voltage Controller */ - if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { + if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->voltage_control) { config = VR_SVI2_PLANE_1; table->VRConfig |= config; } else { @@ -1957,10 +1957,10 @@ static int ellesmere_populate_vr_config(struct pp_hwmgr *hwmgr, ); } /* Set Vddci Voltage Controller */ - if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { + if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->vddci_control) { config = VR_SVI2_PLANE_2; /* only in merged mode */ table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); - } else if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { + } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->vddci_control) { config = VR_SMIO_PATTERN_1; table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); } else { @@ -1968,10 +1968,10 @@ static int ellesmere_populate_vr_config(struct pp_hwmgr *hwmgr, table->VRConfig |= (config << VRCONF_VDDCI_SHIFT); } /* Set Mvdd Voltage Controller */ - if (ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { + if (POLARIS10_VOLTAGE_CONTROL_BY_SVID2 == data->mvdd_control) { config = VR_SVI2_PLANE_2; table->VRConfig |= (config << VRCONF_MVDD_SHIFT); - } else if (ELLESMERE_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { + } else if (POLARIS10_VOLTAGE_CONTROL_BY_GPIO == data->mvdd_control) { config = VR_SMIO_PATTERN_2; table->VRConfig |= (config << VRCONF_MVDD_SHIFT); } else { @@ -1988,24 +1988,24 @@ static int ellesmere_populate_vr_config(struct pp_hwmgr *hwmgr, * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr) +static int polaris10_init_smc_table(struct pp_hwmgr *hwmgr) { int result; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); struct SMU74_Discrete_DpmTable *table = &(data->smc_state_table); - const struct ellesmere_ulv_parm *ulv = &(data->ulv); + const struct polaris10_ulv_parm *ulv = &(data->ulv); uint8_t i; struct pp_atomctrl_gpio_pin_assignment gpio_pin; pp_atomctrl_clock_dividers_vi dividers; - result = ellesmere_setup_default_dpm_tables(hwmgr); + result = polaris10_setup_default_dpm_tables(hwmgr); PP_ASSERT_WITH_CODE(0 == result, "Failed to setup default DPM tables!", return result); - if (ELLESMERE_VOLTAGE_CONTROL_NONE != data->voltage_control) - ellesmere_populate_smc_voltage_tables(hwmgr, table); + if (POLARIS10_VOLTAGE_CONTROL_NONE != data->voltage_control) + polaris10_populate_smc_voltage_tables(hwmgr, table); if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_AutomaticDCTransition)) @@ -2019,34 +2019,34 @@ static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr) table->SystemFlags |= PPSMC_SYSTEMFLAG_GDDR5; if (ulv->ulv_supported && table_info->us_ulv_voltage_offset) { - result = ellesmere_populate_ulv_state(hwmgr, table); + result = polaris10_populate_ulv_state(hwmgr, table); PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize ULV state!", return result); cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, - ixCG_ULV_PARAMETER, PPELLESMERE_CGULVPARAMETER_DFLT); + ixCG_ULV_PARAMETER, PPPOLARIS10_CGULVPARAMETER_DFLT); } - result = ellesmere_populate_smc_link_level(hwmgr, table); + result = polaris10_populate_smc_link_level(hwmgr, table); PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Link Level!", return result); - result = ellesmere_populate_all_graphic_levels(hwmgr); + result = polaris10_populate_all_graphic_levels(hwmgr); PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Graphics Level!", return result); - result = ellesmere_populate_all_memory_levels(hwmgr); + result = polaris10_populate_all_memory_levels(hwmgr); PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Memory Level!", return result); - result = ellesmere_populate_smc_acpi_level(hwmgr, table); + result = polaris10_populate_smc_acpi_level(hwmgr, table); PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize ACPI Level!", return result); - result = ellesmere_populate_smc_vce_level(hwmgr, table); + result = polaris10_populate_smc_vce_level(hwmgr, table); PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize VCE Level!", return result); - result = ellesmere_populate_smc_samu_level(hwmgr, table); + result = polaris10_populate_smc_samu_level(hwmgr, table); PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize SAMU Level!", return result); @@ -2054,29 +2054,29 @@ static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr) * (the other states are just copies of the boot state) we only * need to populate the ARB settings for the initial state. */ - result = ellesmere_program_memory_timing_parameters(hwmgr); + result = polaris10_program_memory_timing_parameters(hwmgr); PP_ASSERT_WITH_CODE(0 == result, "Failed to Write ARB settings for the initial state.", return result); - result = ellesmere_populate_smc_uvd_level(hwmgr, table); + result = polaris10_populate_smc_uvd_level(hwmgr, table); PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize UVD Level!", return result); - result = ellesmere_populate_smc_boot_level(hwmgr, table); + result = polaris10_populate_smc_boot_level(hwmgr, table); PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot Level!", return result); - result = ellesmere_populate_smc_initailial_state(hwmgr); + result = polaris10_populate_smc_initailial_state(hwmgr); PP_ASSERT_WITH_CODE(0 == result, "Failed to initialize Boot State!", return result); - result = ellesmere_populate_bapm_parameters_in_dpm_table(hwmgr); + result = polaris10_populate_bapm_parameters_in_dpm_table(hwmgr); PP_ASSERT_WITH_CODE(0 == result, "Failed to populate BAPM Parameters!", return result); if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ClockStretcher)) { - result = ellesmere_populate_clock_stretcher_data_table(hwmgr); + result = polaris10_populate_clock_stretcher_data_table(hwmgr); PP_ASSERT_WITH_CODE(0 == result, "Failed to populate Clock Stretcher Data Table!", return result); @@ -2089,10 +2089,10 @@ static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr) table->ThermalInterval = 1; table->TemperatureLimitHigh = table_info->cac_dtp_table->usTargetOperatingTemp * - ELLESMERE_Q88_FORMAT_CONVERSION_UNIT; + POLARIS10_Q88_FORMAT_CONVERSION_UNIT; table->TemperatureLimitLow = (table_info->cac_dtp_table->usTargetOperatingTemp - 1) * - ELLESMERE_Q88_FORMAT_CONVERSION_UNIT; + POLARIS10_Q88_FORMAT_CONVERSION_UNIT; table->MemoryVoltageChangeEnable = 1; table->MemoryInterval = 1; table->VoltageResponseTime = 0; @@ -2101,7 +2101,7 @@ static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr) table->PCIeBootLinkLevel = 0; table->PCIeGenInterval = 1; - result = ellesmere_populate_vr_config(hwmgr, table); + result = polaris10_populate_vr_config(hwmgr, table); PP_ASSERT_WITH_CODE(0 == result, "Failed to populate VRConfig setting!", return result); @@ -2111,7 +2111,7 @@ static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr) if (atomctrl_get_pp_assign_pin(hwmgr, VDDC_VRHOT_GPIO_PINID, &gpio_pin)) { table->VRHotGpio = gpio_pin.uc_gpio_pin_bit_shift; } else { - table->VRHotGpio = ELLESMERE_UNUSED_GPIO_PIN; + table->VRHotGpio = POLARIS10_UNUSED_GPIO_PIN; phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot); } @@ -2122,7 +2122,7 @@ static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr) phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_AutomaticDCTransition); } else { - table->AcDcGpio = ELLESMERE_UNUSED_GPIO_PIN; + table->AcDcGpio = POLARIS10_UNUSED_GPIO_PIN; phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_AutomaticDCTransition); } @@ -2179,7 +2179,7 @@ static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr) CONVERT_FROM_HOST_TO_SMC_US(table->PhaseResponseTime); /* Upload all dpm data to SMC memory.(dpm level, dpm level count etc) */ - result = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, + result = polaris10_copy_bytes_to_smc(hwmgr->smumgr, data->dpm_table_start + offsetof(SMU74_Discrete_DpmTable, SystemFlags), (uint8_t *)&(table->SystemFlags), @@ -2197,9 +2197,9 @@ static int ellesmere_init_smc_table(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_init_arb_table_index(struct pp_hwmgr *hwmgr) +static int polaris10_init_arb_table_index(struct pp_hwmgr *hwmgr) { - const struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + const struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint32_t tmp; int result; @@ -2211,7 +2211,7 @@ static int ellesmere_init_arb_table_index(struct pp_hwmgr *hwmgr) * In reality this field should not be in that structure * but in a soft register. */ - result = ellesmere_read_smc_sram_dword(hwmgr->smumgr, + result = polaris10_read_smc_sram_dword(hwmgr->smumgr, data->arb_table_start, &tmp, data->sram_end); if (result) @@ -2220,11 +2220,11 @@ static int ellesmere_init_arb_table_index(struct pp_hwmgr *hwmgr) tmp &= 0x00FFFFFF; tmp |= ((uint32_t)MC_CG_ARB_FREQ_F1) << 24; - return ellesmere_write_smc_sram_dword(hwmgr->smumgr, + return polaris10_write_smc_sram_dword(hwmgr->smumgr, data->arb_table_start, tmp, data->sram_end); } -static int ellesmere_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) +static int polaris10_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_RegulatorHot)) @@ -2234,17 +2234,17 @@ static int ellesmere_enable_vrhot_gpio_interrupt(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_enable_sclk_control(struct pp_hwmgr *hwmgr) +static int polaris10_enable_sclk_control(struct pp_hwmgr *hwmgr) { PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, 0); return 0; } -static int ellesmere_enable_ulv(struct pp_hwmgr *hwmgr) +static int polaris10_enable_ulv(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_ulv_parm *ulv = &(data->ulv); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_ulv_parm *ulv = &(data->ulv); if (ulv->ulv_supported) return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_EnableULV); @@ -2252,7 +2252,7 @@ static int ellesmere_enable_ulv(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) +static int polaris10_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) { if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { @@ -2272,9 +2272,9 @@ static int ellesmere_enable_deep_sleep_master_switch(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) +static int polaris10_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); /* enable SCLK dpm */ if (!data->sclk_dpm_key_disabled) @@ -2307,9 +2307,9 @@ static int ellesmere_enable_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_start_dpm(struct pp_hwmgr *hwmgr) +static int polaris10_start_dpm(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); /*enable general power management */ @@ -2336,7 +2336,7 @@ static int ellesmere_start_dpm(struct pp_hwmgr *hwmgr) return -1); */ - if (ellesmere_enable_sclk_mclk_dpm(hwmgr)) { + if (polaris10_enable_sclk_mclk_dpm(hwmgr)) { printk(KERN_ERR "Failed to enable Sclk DPM and Mclk DPM!"); return -1; } @@ -2358,7 +2358,7 @@ static int ellesmere_start_dpm(struct pp_hwmgr *hwmgr) return 0; } -static void ellesmere_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) +static void polaris10_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sources) { bool protection; enum DPM_EVENT_SRC src; @@ -2398,46 +2398,46 @@ static void ellesmere_set_dpm_event_sources(struct pp_hwmgr *hwmgr, uint32_t sou THERMAL_PROTECTION_DIS, 1); } -static int ellesmere_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, +static int polaris10_enable_auto_throttle_source(struct pp_hwmgr *hwmgr, PHM_AutoThrottleSource source) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); if (!(data->active_auto_throttle_sources & (1 << source))) { data->active_auto_throttle_sources |= 1 << source; - ellesmere_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); + polaris10_set_dpm_event_sources(hwmgr, data->active_auto_throttle_sources); } return 0; } -static int ellesmere_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) +static int polaris10_enable_thermal_auto_throttle(struct pp_hwmgr *hwmgr) { - return ellesmere_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); + return polaris10_enable_auto_throttle_source(hwmgr, PHM_AutoThrottleSource_Thermal); } -int ellesmere_pcie_performance_request(struct pp_hwmgr *hwmgr) +int polaris10_pcie_performance_request(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); data->pcie_performance_request = true; return 0; } -int ellesmere_enable_dpm_tasks(struct pp_hwmgr *hwmgr) +int polaris10_enable_dpm_tasks(struct pp_hwmgr *hwmgr) { int tmp_result, result = 0; - tmp_result = (!ellesmere_is_dpm_running(hwmgr)) ? 0 : -1; + tmp_result = (!polaris10_is_dpm_running(hwmgr)) ? 0 : -1; PP_ASSERT_WITH_CODE(result == 0, "DPM is already running right now, no need to enable DPM!", return 0); - if (ellesmere_voltage_control(hwmgr)) { - tmp_result = ellesmere_enable_voltage_control(hwmgr); + if (polaris10_voltage_control(hwmgr)) { + tmp_result = polaris10_enable_voltage_control(hwmgr); PP_ASSERT_WITH_CODE(tmp_result == 0, "Failed to enable voltage control!", result = tmp_result); - tmp_result = ellesmere_construct_voltage_tables(hwmgr); + tmp_result = polaris10_construct_voltage_tables(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to contruct voltage tables!", result = tmp_result); @@ -2453,116 +2453,116 @@ int ellesmere_enable_dpm_tasks(struct pp_hwmgr *hwmgr) PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, 0); - tmp_result = ellesmere_program_static_screen_threshold_parameters(hwmgr); + tmp_result = polaris10_program_static_screen_threshold_parameters(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program static screen threshold parameters!", result = tmp_result); - tmp_result = ellesmere_enable_display_gap(hwmgr); + tmp_result = polaris10_enable_display_gap(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to enable display gap!", result = tmp_result); - tmp_result = ellesmere_program_voting_clients(hwmgr); + tmp_result = polaris10_program_voting_clients(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program voting clients!", result = tmp_result); - tmp_result = ellesmere_process_firmware_header(hwmgr); + tmp_result = polaris10_process_firmware_header(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to process firmware header!", result = tmp_result); - tmp_result = ellesmere_initial_switch_from_arbf0_to_f1(hwmgr); + tmp_result = polaris10_initial_switch_from_arbf0_to_f1(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to initialize switch from ArbF0 to F1!", result = tmp_result); - tmp_result = ellesmere_init_smc_table(hwmgr); + tmp_result = polaris10_init_smc_table(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to initialize SMC table!", result = tmp_result); - tmp_result = ellesmere_init_arb_table_index(hwmgr); + tmp_result = polaris10_init_arb_table_index(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to initialize ARB table index!", result = tmp_result); - tmp_result = ellesmere_populate_pm_fuses(hwmgr); + tmp_result = polaris10_populate_pm_fuses(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate PM fuses!", result = tmp_result); - tmp_result = ellesmere_enable_vrhot_gpio_interrupt(hwmgr); + tmp_result = polaris10_enable_vrhot_gpio_interrupt(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to enable VR hot GPIO interrupt!", result = tmp_result); - tmp_result = ellesmere_enable_sclk_control(hwmgr); + tmp_result = polaris10_enable_sclk_control(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to enable SCLK control!", result = tmp_result); - tmp_result = ellesmere_enable_smc_voltage_controller(hwmgr); + tmp_result = polaris10_enable_smc_voltage_controller(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to enable voltage control!", result = tmp_result); - tmp_result = ellesmere_enable_ulv(hwmgr); + tmp_result = polaris10_enable_ulv(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to enable ULV!", result = tmp_result); - tmp_result = ellesmere_enable_deep_sleep_master_switch(hwmgr); + tmp_result = polaris10_enable_deep_sleep_master_switch(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to enable deep sleep master switch!", result = tmp_result); - tmp_result = ellesmere_start_dpm(hwmgr); + tmp_result = polaris10_start_dpm(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to start DPM!", result = tmp_result); - tmp_result = ellesmere_enable_smc_cac(hwmgr); + tmp_result = polaris10_enable_smc_cac(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to enable SMC CAC!", result = tmp_result); - tmp_result = ellesmere_enable_power_containment(hwmgr); + tmp_result = polaris10_enable_power_containment(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to enable power containment!", result = tmp_result); - tmp_result = ellesmere_power_control_set_level(hwmgr); + tmp_result = polaris10_power_control_set_level(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to power control set level!", result = tmp_result); - tmp_result = ellesmere_enable_thermal_auto_throttle(hwmgr); + tmp_result = polaris10_enable_thermal_auto_throttle(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to enable thermal auto throttle!", result = tmp_result); - tmp_result = ellesmere_pcie_performance_request(hwmgr); + tmp_result = polaris10_pcie_performance_request(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to enable thermal auto throttle!", result = tmp_result); return result; } -int ellesmere_disable_dpm_tasks(struct pp_hwmgr *hwmgr) +int polaris10_disable_dpm_tasks(struct pp_hwmgr *hwmgr) { return 0; } -int ellesmere_reset_asic_tasks(struct pp_hwmgr *hwmgr) +int polaris10_reset_asic_tasks(struct pp_hwmgr *hwmgr) { return 0; } -int ellesmere_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) +int polaris10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr) { return phm_hwmgr_backend_fini(hwmgr); } -int ellesmere_set_features_platform_caps(struct pp_hwmgr *hwmgr) +int polaris10_set_features_platform_caps(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep); - if (data->mvdd_control == ELLESMERE_VOLTAGE_CONTROL_NONE) + if (data->mvdd_control == POLARIS10_VOLTAGE_CONTROL_NONE) phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_EnableMVDDControl); - if (data->vddci_control == ELLESMERE_VOLTAGE_CONTROL_NONE) + if (data->vddci_control == POLARIS10_VOLTAGE_CONTROL_NONE) phm_cap_unset(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ControlVDDCI); @@ -2607,11 +2607,11 @@ int ellesmere_set_features_platform_caps(struct pp_hwmgr *hwmgr) return 0; } -static void ellesmere_init_dpm_defaults(struct pp_hwmgr *hwmgr) +static void polaris10_init_dpm_defaults(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); - ellesmere_initialize_power_tune_defaults(hwmgr); + polaris10_initialize_power_tune_defaults(hwmgr); data->pcie_gen_performance.max = PP_PCIEGen1; data->pcie_gen_performance.min = PP_PCIEGen3; @@ -2629,9 +2629,9 @@ static void ellesmere_init_dpm_defaults(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_get_evv_voltages(struct pp_hwmgr *hwmgr) +static int polaris10_get_evv_voltages(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint16_t vv_id; uint16_t vddc = 0; uint16_t i, j; @@ -2642,7 +2642,7 @@ static int ellesmere_get_evv_voltages(struct pp_hwmgr *hwmgr) table_info->vdd_dep_on_sclk; int result; - for (i = 0; i < ELLESMERE_MAX_LEAKAGE_COUNT; i++) { + for (i = 0; i < POLARIS10_MAX_LEAKAGE_COUNT; i++) { vv_id = ATOM_VIRTUAL_VOLTAGE_ID0 + i; if (!phm_get_sclk_for_voltage_evv(hwmgr, table_info->vddc_lookup_table, vv_id, &sclk)) { @@ -2687,8 +2687,8 @@ static int ellesmere_get_evv_voltages(struct pp_hwmgr *hwmgr) * @param pointer to changing voltage * @param pointer to leakage table */ -static void ellesmere_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, - uint16_t *voltage, struct ellesmere_leakage_voltage *leakage_table) +static void polaris10_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, + uint16_t *voltage, struct polaris10_leakage_voltage *leakage_table) { uint32_t index; @@ -2714,32 +2714,32 @@ static void ellesmere_patch_with_vdd_leakage(struct pp_hwmgr *hwmgr, * @param pointer to leakage table * @return always 0 */ -static int ellesmere_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, +static int polaris10_patch_lookup_table_with_leakage(struct pp_hwmgr *hwmgr, phm_ppt_v1_voltage_lookup_table *lookup_table, - struct ellesmere_leakage_voltage *leakage_table) + struct polaris10_leakage_voltage *leakage_table) { uint32_t i; for (i = 0; i < lookup_table->count; i++) - ellesmere_patch_with_vdd_leakage(hwmgr, + polaris10_patch_with_vdd_leakage(hwmgr, &lookup_table->entries[i].us_vdd, leakage_table); return 0; } -static int ellesmere_patch_clock_voltage_limits_with_vddc_leakage( - struct pp_hwmgr *hwmgr, struct ellesmere_leakage_voltage *leakage_table, +static int polaris10_patch_clock_voltage_limits_with_vddc_leakage( + struct pp_hwmgr *hwmgr, struct polaris10_leakage_voltage *leakage_table, uint16_t *vddc) { struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); - ellesmere_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); + polaris10_patch_with_vdd_leakage(hwmgr, (uint16_t *)vddc, leakage_table); hwmgr->dyn_state.max_clock_voltage_on_dc.vddc = table_info->max_clock_voltage_on_dc.vddc; return 0; } -static int ellesmere_patch_voltage_dependency_tables_with_lookup_table( +static int polaris10_patch_voltage_dependency_tables_with_lookup_table( struct pp_hwmgr *hwmgr) { uint8_t entryId; @@ -2776,19 +2776,19 @@ static int ellesmere_patch_voltage_dependency_tables_with_lookup_table( } -static int ellesmere_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) +static int polaris10_calc_voltage_dependency_tables(struct pp_hwmgr *hwmgr) { /* Need to determine if we need calculated voltage. */ return 0; } -static int ellesmere_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) +static int polaris10_calc_mm_voltage_dependency_table(struct pp_hwmgr *hwmgr) { /* Need to determine if we need calculated voltage from mm table. */ return 0; } -static int ellesmere_sort_lookup_table(struct pp_hwmgr *hwmgr, +static int polaris10_sort_lookup_table(struct pp_hwmgr *hwmgr, struct phm_ppt_v1_voltage_lookup_table *lookup_table) { uint32_t table_size, i, j; @@ -2813,44 +2813,44 @@ static int ellesmere_sort_lookup_table(struct pp_hwmgr *hwmgr, return 0; } -static int ellesmere_complete_dependency_tables(struct pp_hwmgr *hwmgr) +static int polaris10_complete_dependency_tables(struct pp_hwmgr *hwmgr) { int result = 0; int tmp_result; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); - tmp_result = ellesmere_patch_lookup_table_with_leakage(hwmgr, + tmp_result = polaris10_patch_lookup_table_with_leakage(hwmgr, table_info->vddc_lookup_table, &(data->vddc_leakage)); if (tmp_result) result = tmp_result; - tmp_result = ellesmere_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, + tmp_result = polaris10_patch_clock_voltage_limits_with_vddc_leakage(hwmgr, &(data->vddc_leakage), &table_info->max_clock_voltage_on_dc.vddc); if (tmp_result) result = tmp_result; - tmp_result = ellesmere_patch_voltage_dependency_tables_with_lookup_table(hwmgr); + tmp_result = polaris10_patch_voltage_dependency_tables_with_lookup_table(hwmgr); if (tmp_result) result = tmp_result; - tmp_result = ellesmere_calc_voltage_dependency_tables(hwmgr); + tmp_result = polaris10_calc_voltage_dependency_tables(hwmgr); if (tmp_result) result = tmp_result; - tmp_result = ellesmere_calc_mm_voltage_dependency_table(hwmgr); + tmp_result = polaris10_calc_mm_voltage_dependency_table(hwmgr); if (tmp_result) result = tmp_result; - tmp_result = ellesmere_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); + tmp_result = polaris10_sort_lookup_table(hwmgr, table_info->vddc_lookup_table); if (tmp_result) result = tmp_result; return result; } -static int ellesmere_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) +static int polaris10_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) { struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -2886,9 +2886,9 @@ static int ellesmere_set_private_data_based_on_pptable(struct pp_hwmgr *hwmgr) return 0; } -int ellesmere_hwmgr_backend_init(struct pp_hwmgr *hwmgr) +int polaris10_hwmgr_backend_init(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct pp_atomctrl_gpio_pin_assignment gpio_pin_assignment; uint32_t temp_reg; int result; @@ -2897,38 +2897,38 @@ int ellesmere_hwmgr_backend_init(struct pp_hwmgr *hwmgr) data->sram_end = SMC_RAM_END; data->disable_dpm_mask = 0xFF; - data->static_screen_threshold = PPELLESMERE_STATICSCREENTHRESHOLD_DFLT; - data->static_screen_threshold_unit = PPELLESMERE_STATICSCREENTHRESHOLD_DFLT; - data->activity_target[0] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[1] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[2] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[3] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[4] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[5] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[6] = PPELLESMERE_TARGETACTIVITY_DFLT; - data->activity_target[7] = PPELLESMERE_TARGETACTIVITY_DFLT; - - data->voting_rights_clients0 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT0; - data->voting_rights_clients1 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT1; - data->voting_rights_clients2 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT2; - data->voting_rights_clients3 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT3; - data->voting_rights_clients4 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT4; - data->voting_rights_clients5 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT5; - data->voting_rights_clients6 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT6; - data->voting_rights_clients7 = PPELLESMERE_VOTINGRIGHTSCLIENTS_DFLT7; + data->static_screen_threshold = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT; + data->static_screen_threshold_unit = PPPOLARIS10_STATICSCREENTHRESHOLD_DFLT; + data->activity_target[0] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[1] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[2] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[3] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[4] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[5] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[6] = PPPOLARIS10_TARGETACTIVITY_DFLT; + data->activity_target[7] = PPPOLARIS10_TARGETACTIVITY_DFLT; + + data->voting_rights_clients0 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT0; + data->voting_rights_clients1 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT1; + data->voting_rights_clients2 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT2; + data->voting_rights_clients3 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT3; + data->voting_rights_clients4 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT4; + data->voting_rights_clients5 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT5; + data->voting_rights_clients6 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT6; + data->voting_rights_clients7 = PPPOLARIS10_VOTINGRIGHTSCLIENTS_DFLT7; data->vddc_vddci_delta = VDDC_VDDCI_DELTA; - data->mclk_activity_target = PPELLESMERE_MCLK_TARGETACTIVITY_DFLT; + data->mclk_activity_target = PPPOLARIS10_MCLK_TARGETACTIVITY_DFLT; /* need to set voltage control types before EVV patching */ - data->voltage_control = ELLESMERE_VOLTAGE_CONTROL_NONE; - data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_NONE; - data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_NONE; + data->voltage_control = POLARIS10_VOLTAGE_CONTROL_NONE; + data->vddci_control = POLARIS10_VOLTAGE_CONTROL_NONE; + data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_NONE; if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, VOLTAGE_TYPE_VDDC, VOLTAGE_OBJ_SVID2)) - data->voltage_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2; + data->voltage_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2; phm_cap_set(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DynamicPatchPowerState); @@ -2937,36 +2937,36 @@ int ellesmere_hwmgr_backend_init(struct pp_hwmgr *hwmgr) PHM_PlatformCaps_EnableMVDDControl)) { if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_GPIO_LUT)) - data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_BY_GPIO; + data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO; else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, VOLTAGE_TYPE_MVDDC, VOLTAGE_OBJ_SVID2)) - data->mvdd_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2; + data->mvdd_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2; } if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ControlVDDCI)) { if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_GPIO_LUT)) - data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_BY_GPIO; + data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_GPIO; else if (atomctrl_is_voltage_controled_by_gpio_v3(hwmgr, VOLTAGE_TYPE_VDDCI, VOLTAGE_OBJ_SVID2)) - data->vddci_control = ELLESMERE_VOLTAGE_CONTROL_BY_SVID2; + data->vddci_control = POLARIS10_VOLTAGE_CONTROL_BY_SVID2; } - ellesmere_set_features_platform_caps(hwmgr); + polaris10_set_features_platform_caps(hwmgr); - ellesmere_init_dpm_defaults(hwmgr); + polaris10_init_dpm_defaults(hwmgr); /* Get leakage voltage based on leakage ID. */ - result = ellesmere_get_evv_voltages(hwmgr); + result = polaris10_get_evv_voltages(hwmgr); if (result) { printk("Get EVV Voltage Failed. Abort Driver loading!\n"); return -1; } - ellesmere_complete_dependency_tables(hwmgr); - ellesmere_set_private_data_based_on_pptable(hwmgr); + polaris10_complete_dependency_tables(hwmgr); + polaris10_set_private_data_based_on_pptable(hwmgr); /* Initalize Dynamic State Adjustment Rule Settings */ result = phm_initializa_dynamic_state_adjustment_rule_settings(hwmgr); @@ -2977,7 +2977,7 @@ int ellesmere_hwmgr_backend_init(struct pp_hwmgr *hwmgr) data->is_tlu_enabled = 0; hwmgr->platform_descriptor.hardwareActivityPerformanceLevels = - ELLESMERE_MAX_HARDWARE_POWERLEVELS; + POLARIS10_MAX_HARDWARE_POWERLEVELS; hwmgr->platform_descriptor.hardwarePerformanceLevels = 2; hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50; hwmgr->platform_descriptor.vbiosInterruptId = 0x20000400; /* IRQ_SOURCE1_SW_INT */ @@ -3030,15 +3030,15 @@ int ellesmere_hwmgr_backend_init(struct pp_hwmgr *hwmgr) data->pcie_lane_cap = (uint32_t)sys_info.value; } else { /* Ignore return value in here, we are cleaning up a mess. */ - ellesmere_hwmgr_backend_fini(hwmgr); + polaris10_hwmgr_backend_fini(hwmgr); } return 0; } -static int ellesmere_force_dpm_highest(struct pp_hwmgr *hwmgr) +static int polaris10_force_dpm_highest(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint32_t level, tmp; if (!data->pcie_dpm_key_disabled) { @@ -3085,9 +3085,9 @@ static int ellesmere_force_dpm_highest(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) +static int polaris10_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); phm_apply_dal_min_voltage_request(hwmgr); @@ -3108,11 +3108,11 @@ static int ellesmere_upload_dpm_level_enable_mask(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_unforce_dpm_levels(struct pp_hwmgr *hwmgr) +static int polaris10_unforce_dpm_levels(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); - if (!ellesmere_is_dpm_running(hwmgr)) + if (!polaris10_is_dpm_running(hwmgr)) return -EINVAL; if (!data->pcie_dpm_key_disabled) { @@ -3120,13 +3120,13 @@ static int ellesmere_unforce_dpm_levels(struct pp_hwmgr *hwmgr) PPSMC_MSG_PCIeDPM_UnForceLevel); } - return ellesmere_upload_dpm_level_enable_mask(hwmgr); + return polaris10_upload_dpm_level_enable_mask(hwmgr); } -static int ellesmere_force_dpm_lowest(struct pp_hwmgr *hwmgr) +static int polaris10_force_dpm_lowest(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = - (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = + (struct polaris10_hwmgr *)(hwmgr->backend); uint32_t level; if (!data->sclk_dpm_key_disabled) @@ -3162,24 +3162,24 @@ static int ellesmere_force_dpm_lowest(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_force_dpm_level(struct pp_hwmgr *hwmgr, +static int polaris10_force_dpm_level(struct pp_hwmgr *hwmgr, enum amd_dpm_forced_level level) { int ret = 0; switch (level) { case AMD_DPM_FORCED_LEVEL_HIGH: - ret = ellesmere_force_dpm_highest(hwmgr); + ret = polaris10_force_dpm_highest(hwmgr); if (ret) return ret; break; case AMD_DPM_FORCED_LEVEL_LOW: - ret = ellesmere_force_dpm_lowest(hwmgr); + ret = polaris10_force_dpm_lowest(hwmgr); if (ret) return ret; break; case AMD_DPM_FORCED_LEVEL_AUTO: - ret = ellesmere_unforce_dpm_levels(hwmgr); + ret = polaris10_unforce_dpm_levels(hwmgr); if (ret) return ret; break; @@ -3192,19 +3192,19 @@ static int ellesmere_force_dpm_level(struct pp_hwmgr *hwmgr, return ret; } -static int ellesmere_get_power_state_size(struct pp_hwmgr *hwmgr) +static int polaris10_get_power_state_size(struct pp_hwmgr *hwmgr) { - return sizeof(struct ellesmere_power_state); + return sizeof(struct polaris10_power_state); } -static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, +static int polaris10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, struct pp_power_state *request_ps, const struct pp_power_state *current_ps) { - struct ellesmere_power_state *ellesmere_ps = - cast_phw_ellesmere_power_state(&request_ps->hardware); + struct polaris10_power_state *polaris10_ps = + cast_phw_polaris10_power_state(&request_ps->hardware); uint32_t sclk; uint32_t mclk; struct PP_Clocks minimum_clocks = {0}; @@ -3213,7 +3213,7 @@ static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, struct cgs_display_info info = {0}; const struct phm_clock_and_voltage_limits *max_limits; uint32_t i; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); int32_t count; @@ -3222,7 +3222,7 @@ static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, data->battery_state = (PP_StateUILabel_Battery == request_ps->classification.ui_label); - PP_ASSERT_WITH_CODE(ellesmere_ps->performance_level_count == 2, + PP_ASSERT_WITH_CODE(polaris10_ps->performance_level_count == 2, "VI should always have 2 performance levels", ); @@ -3232,16 +3232,16 @@ static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, /* Cap clock DPM tables at DC MAX if it is in DC. */ if (PP_PowerSource_DC == hwmgr->power_source) { - for (i = 0; i < ellesmere_ps->performance_level_count; i++) { - if (ellesmere_ps->performance_levels[i].memory_clock > max_limits->mclk) - ellesmere_ps->performance_levels[i].memory_clock = max_limits->mclk; - if (ellesmere_ps->performance_levels[i].engine_clock > max_limits->sclk) - ellesmere_ps->performance_levels[i].engine_clock = max_limits->sclk; + for (i = 0; i < polaris10_ps->performance_level_count; i++) { + if (polaris10_ps->performance_levels[i].memory_clock > max_limits->mclk) + polaris10_ps->performance_levels[i].memory_clock = max_limits->mclk; + if (polaris10_ps->performance_levels[i].engine_clock > max_limits->sclk) + polaris10_ps->performance_levels[i].engine_clock = max_limits->sclk; } } - ellesmere_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk; - ellesmere_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk; + polaris10_ps->vce_clks.evclk = hwmgr->vce_arbiter.evclk; + polaris10_ps->vce_clks.ecclk = hwmgr->vce_arbiter.ecclk; cgs_get_active_displays_info(hwmgr->device, &info); @@ -3279,7 +3279,7 @@ static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, if (minimum_clocks.memoryClock < hwmgr->gfx_arbiter.mclk) minimum_clocks.memoryClock = hwmgr->gfx_arbiter.mclk; - ellesmere_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; + polaris10_ps->sclk_threshold = hwmgr->gfx_arbiter.sclk_threshold; if (0 != hwmgr->gfx_arbiter.sclk_over_drive) { PP_ASSERT_WITH_CODE((hwmgr->gfx_arbiter.sclk_over_drive <= @@ -3289,7 +3289,7 @@ static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, hwmgr->platform_descriptor.overdriveLimit.engineClock); if (hwmgr->gfx_arbiter.sclk_over_drive >= hwmgr->gfx_arbiter.sclk) - ellesmere_ps->performance_levels[1].engine_clock = + polaris10_ps->performance_levels[1].engine_clock = hwmgr->gfx_arbiter.sclk_over_drive; } @@ -3301,7 +3301,7 @@ static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, hwmgr->platform_descriptor.overdriveLimit.memoryClock); if (hwmgr->gfx_arbiter.mclk_over_drive >= hwmgr->gfx_arbiter.mclk) - ellesmere_ps->performance_levels[1].memory_clock = + polaris10_ps->performance_levels[1].memory_clock = hwmgr->gfx_arbiter.mclk_over_drive; } @@ -3312,12 +3312,12 @@ static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, disable_mclk_switching = (1 < info.display_count) || disable_mclk_switching_for_frame_lock; - sclk = ellesmere_ps->performance_levels[0].engine_clock; - mclk = ellesmere_ps->performance_levels[0].memory_clock; + sclk = polaris10_ps->performance_levels[0].engine_clock; + mclk = polaris10_ps->performance_levels[0].memory_clock; if (disable_mclk_switching) - mclk = ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count - 1].memory_clock; + mclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].memory_clock; if (sclk < minimum_clocks.engineClock) sclk = (minimum_clocks.engineClock > max_limits->sclk) ? @@ -3327,45 +3327,45 @@ static int ellesmere_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, mclk = (minimum_clocks.memoryClock > max_limits->mclk) ? max_limits->mclk : minimum_clocks.memoryClock; - ellesmere_ps->performance_levels[0].engine_clock = sclk; - ellesmere_ps->performance_levels[0].memory_clock = mclk; + polaris10_ps->performance_levels[0].engine_clock = sclk; + polaris10_ps->performance_levels[0].memory_clock = mclk; - ellesmere_ps->performance_levels[1].engine_clock = - (ellesmere_ps->performance_levels[1].engine_clock >= - ellesmere_ps->performance_levels[0].engine_clock) ? - ellesmere_ps->performance_levels[1].engine_clock : - ellesmere_ps->performance_levels[0].engine_clock; + polaris10_ps->performance_levels[1].engine_clock = + (polaris10_ps->performance_levels[1].engine_clock >= + polaris10_ps->performance_levels[0].engine_clock) ? + polaris10_ps->performance_levels[1].engine_clock : + polaris10_ps->performance_levels[0].engine_clock; if (disable_mclk_switching) { - if (mclk < ellesmere_ps->performance_levels[1].memory_clock) - mclk = ellesmere_ps->performance_levels[1].memory_clock; + if (mclk < polaris10_ps->performance_levels[1].memory_clock) + mclk = polaris10_ps->performance_levels[1].memory_clock; - ellesmere_ps->performance_levels[0].memory_clock = mclk; - ellesmere_ps->performance_levels[1].memory_clock = mclk; + polaris10_ps->performance_levels[0].memory_clock = mclk; + polaris10_ps->performance_levels[1].memory_clock = mclk; } else { - if (ellesmere_ps->performance_levels[1].memory_clock < - ellesmere_ps->performance_levels[0].memory_clock) - ellesmere_ps->performance_levels[1].memory_clock = - ellesmere_ps->performance_levels[0].memory_clock; + if (polaris10_ps->performance_levels[1].memory_clock < + polaris10_ps->performance_levels[0].memory_clock) + polaris10_ps->performance_levels[1].memory_clock = + polaris10_ps->performance_levels[0].memory_clock; } if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) { - for (i = 0; i < ellesmere_ps->performance_level_count; i++) { - ellesmere_ps->performance_levels[i].engine_clock = stable_pstate_sclk; - ellesmere_ps->performance_levels[i].memory_clock = stable_pstate_mclk; - ellesmere_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; - ellesmere_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; + for (i = 0; i < polaris10_ps->performance_level_count; i++) { + polaris10_ps->performance_levels[i].engine_clock = stable_pstate_sclk; + polaris10_ps->performance_levels[i].memory_clock = stable_pstate_mclk; + polaris10_ps->performance_levels[i].pcie_gen = data->pcie_gen_performance.max; + polaris10_ps->performance_levels[i].pcie_lane = data->pcie_gen_performance.max; } } return 0; } -static int ellesmere_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) +static int polaris10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) { struct pp_power_state *ps; - struct ellesmere_power_state *ellesmere_ps; + struct polaris10_power_state *polaris10_ps; if (hwmgr == NULL) return -EINVAL; @@ -3375,19 +3375,19 @@ static int ellesmere_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low) if (ps == NULL) return -EINVAL; - ellesmere_ps = cast_phw_ellesmere_power_state(&ps->hardware); + polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware); if (low) - return ellesmere_ps->performance_levels[0].memory_clock; + return polaris10_ps->performance_levels[0].memory_clock; else - return ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count-1].memory_clock; + return polaris10_ps->performance_levels + [polaris10_ps->performance_level_count-1].memory_clock; } -static int ellesmere_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) +static int polaris10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) { struct pp_power_state *ps; - struct ellesmere_power_state *ellesmere_ps; + struct polaris10_power_state *polaris10_ps; if (hwmgr == NULL) return -EINVAL; @@ -3397,20 +3397,20 @@ static int ellesmere_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low) if (ps == NULL) return -EINVAL; - ellesmere_ps = cast_phw_ellesmere_power_state(&ps->hardware); + polaris10_ps = cast_phw_polaris10_power_state(&ps->hardware); if (low) - return ellesmere_ps->performance_levels[0].engine_clock; + return polaris10_ps->performance_levels[0].engine_clock; else - return ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count-1].engine_clock; + return polaris10_ps->performance_levels + [polaris10_ps->performance_level_count-1].engine_clock; } -static int ellesmere_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, +static int polaris10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, struct pp_hw_power_state *hw_ps) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_power_state *ps = (struct ellesmere_power_state *)hw_ps; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_power_state *ps = (struct polaris10_power_state *)hw_ps; ATOM_FIRMWARE_INFO_V2_2 *fw_info; uint16_t size; uint8_t frev, crev; @@ -3452,14 +3452,14 @@ static int ellesmere_dpm_patch_boot_state(struct pp_hwmgr *hwmgr, return 0; } -static int ellesmere_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, +static int polaris10_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, void *state, struct pp_power_state *power_state, void *pp_table, uint32_t classification_flag) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_power_state *ellesmere_power_state = - (struct ellesmere_power_state *)(&(power_state->hardware)); - struct ellesmere_performance_level *performance_level; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_power_state *polaris10_power_state = + (struct polaris10_power_state *)(&(power_state->hardware)); + struct polaris10_performance_level *performance_level; ATOM_Tonga_State *state_entry = (ATOM_Tonga_State *)state; ATOM_Tonga_POWERPLAYTABLE *powerplay_table = (ATOM_Tonga_POWERPLAYTABLE *)pp_table; @@ -3501,16 +3501,16 @@ static int ellesmere_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, power_state->temperatures.min = 0; power_state->temperatures.max = 0; - performance_level = &(ellesmere_power_state->performance_levels - [ellesmere_power_state->performance_level_count++]); + performance_level = &(polaris10_power_state->performance_levels + [polaris10_power_state->performance_level_count++]); PP_ASSERT_WITH_CODE( - (ellesmere_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS), + (polaris10_power_state->performance_level_count < SMU74_MAX_LEVELS_GRAPHICS), "Performance levels exceeds SMC limit!", return -1); PP_ASSERT_WITH_CODE( - (ellesmere_power_state->performance_level_count <= + (polaris10_power_state->performance_level_count <= hwmgr->platform_descriptor.hardwareActivityPerformanceLevels), "Performance levels exceeds Driver limit!", return -1); @@ -3525,8 +3525,8 @@ static int ellesmere_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, performance_level->pcie_lane = get_pcie_lane_support(data->pcie_lane_cap, state_entry->ucPCIELaneHigh); - performance_level = &(ellesmere_power_state->performance_levels - [ellesmere_power_state->performance_level_count++]); + performance_level = &(polaris10_power_state->performance_levels + [polaris10_power_state->performance_level_count++]); performance_level->memory_clock = mclk_dep_table->entries [state_entry->ucMemoryClockIndexHigh].ulMclk; performance_level->engine_clock = sclk_dep_table->entries @@ -3539,12 +3539,12 @@ static int ellesmere_get_pp_table_entry_callback_func(struct pp_hwmgr *hwmgr, return 0; } -static int ellesmere_get_pp_table_entry(struct pp_hwmgr *hwmgr, +static int polaris10_get_pp_table_entry(struct pp_hwmgr *hwmgr, unsigned long entry_index, struct pp_power_state *state) { int result; - struct ellesmere_power_state *ps; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_power_state *ps; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); struct phm_ppt_v1_clock_voltage_dependency_table *dep_mclk_table = @@ -3552,10 +3552,10 @@ static int ellesmere_get_pp_table_entry(struct pp_hwmgr *hwmgr, state->hardware.magic = PHM_VIslands_Magic; - ps = (struct ellesmere_power_state *)(&state->hardware); + ps = (struct polaris10_power_state *)(&state->hardware); result = tonga_get_powerplay_table_entry(hwmgr, entry_index, state, - ellesmere_get_pp_table_entry_callback_func); + polaris10_get_pp_table_entry_callback_func); /* This is the earliest time we have all the dependency table and the VBIOS boot state * as PP_Tables_GetPowerPlayTableEntry retrieves the VBIOS boot state @@ -3644,7 +3644,7 @@ static int ellesmere_get_pp_table_entry(struct pp_hwmgr *hwmgr, } static void -ellesmere_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) +polaris10_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file *m) { uint32_t sclk, mclk; @@ -3659,19 +3659,19 @@ ellesmere_print_current_perforce_level(struct pp_hwmgr *hwmgr, struct seq_file * mclk / 100, sclk / 100); } -static int ellesmere_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) +static int polaris10_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, const void *input) { const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; - const struct ellesmere_power_state *ellesmere_ps = - cast_const_phw_ellesmere_power_state(states->pnew_state); - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); - uint32_t sclk = ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count - 1].engine_clock; - struct ellesmere_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); - uint32_t mclk = ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count - 1].memory_clock; + const struct polaris10_power_state *polaris10_ps = + cast_const_phw_polaris10_power_state(states->pnew_state); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); + uint32_t sclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].engine_clock; + struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); + uint32_t mclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].memory_clock; struct PP_Clocks min_clocks = {0}; uint32_t i; struct cgs_display_info info = {0}; @@ -3689,7 +3689,9 @@ static int ellesmere_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, /* TODO: Check SCLK in DAL's minimum clocks * in case DeepSleep divider update is required. */ - if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR) + if (data->display_timing.min_clock_in_sr != min_clocks.engineClockInSR && + (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK || + data->display_timing.min_clock_in_sr >= POLARIS10_MINIMUM_ENGINE_CLOCK)) data->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; } @@ -3709,16 +3711,16 @@ static int ellesmere_find_dpm_states_clocks_in_dpm_table(struct pp_hwmgr *hwmgr, return 0; } -static uint16_t ellesmere_get_maximum_link_speed(struct pp_hwmgr *hwmgr, - const struct ellesmere_power_state *ellesmere_ps) +static uint16_t polaris10_get_maximum_link_speed(struct pp_hwmgr *hwmgr, + const struct polaris10_power_state *polaris10_ps) { uint32_t i; uint32_t sclk, max_sclk = 0; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_dpm_table *dpm_table = &data->dpm_table; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_dpm_table *dpm_table = &data->dpm_table; - for (i = 0; i < ellesmere_ps->performance_level_count; i++) { - sclk = ellesmere_ps->performance_levels[i].engine_clock; + for (i = 0; i < polaris10_ps->performance_level_count; i++) { + sclk = polaris10_ps->performance_levels[i].engine_clock; if (max_sclk < sclk) max_sclk = sclk; } @@ -3734,22 +3736,22 @@ static uint16_t ellesmere_get_maximum_link_speed(struct pp_hwmgr *hwmgr, return 0; } -static int ellesmere_request_link_speed_change_before_state_change( +static int polaris10_request_link_speed_change_before_state_change( struct pp_hwmgr *hwmgr, const void *input) { const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - const struct ellesmere_power_state *ellesmere_nps = - cast_const_phw_ellesmere_power_state(states->pnew_state); - const struct ellesmere_power_state *ellesmere_cps = - cast_const_phw_ellesmere_power_state(states->pcurrent_state); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_power_state *polaris10_nps = + cast_const_phw_polaris10_power_state(states->pnew_state); + const struct polaris10_power_state *polaris10_cps = + cast_const_phw_polaris10_power_state(states->pcurrent_state); - uint16_t target_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_nps); + uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_nps); uint16_t current_link_speed; if (data->force_pcie_gen == PP_PCIEGenInvalid) - current_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_cps); + current_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_cps); else current_link_speed = data->force_pcie_gen; @@ -3779,9 +3781,9 @@ static int ellesmere_request_link_speed_change_before_state_change( return 0; } -static int ellesmere_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) +static int polaris10_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); if (0 == data->need_update_smu7_dpm_table) return 0; @@ -3789,7 +3791,7 @@ static int ellesmere_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) if ((0 == data->sclk_dpm_key_disabled) && (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { - PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr), + PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), "Trying to freeze SCLK DPM when DPM is disabled", ); PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, @@ -3801,7 +3803,7 @@ static int ellesmere_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) if ((0 == data->mclk_dpm_key_disabled) && (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { - PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr), + PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), "Trying to freeze MCLK DPM when DPM is disabled", ); PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, @@ -3813,22 +3815,22 @@ static int ellesmere_freeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_populate_and_upload_sclk_mclk_dpm_levels( +static int polaris10_populate_and_upload_sclk_mclk_dpm_levels( struct pp_hwmgr *hwmgr, const void *input) { int result = 0; const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; - const struct ellesmere_power_state *ellesmere_ps = - cast_const_phw_ellesmere_power_state(states->pnew_state); - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - uint32_t sclk = ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count - 1].engine_clock; - uint32_t mclk = ellesmere_ps->performance_levels - [ellesmere_ps->performance_level_count - 1].memory_clock; - struct ellesmere_dpm_table *dpm_table = &data->dpm_table; - - struct ellesmere_dpm_table *golden_dpm_table = &data->golden_dpm_table; + const struct polaris10_power_state *polaris10_ps = + cast_const_phw_polaris10_power_state(states->pnew_state); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + uint32_t sclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].engine_clock; + uint32_t mclk = polaris10_ps->performance_levels + [polaris10_ps->performance_level_count - 1].memory_clock; + struct polaris10_dpm_table *dpm_table = &data->dpm_table; + + struct polaris10_dpm_table *golden_dpm_table = &data->golden_dpm_table; uint32_t dpm_count, clock_percent; uint32_t i; @@ -3924,7 +3926,7 @@ static int ellesmere_populate_and_upload_sclk_mclk_dpm_levels( if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK)) { - result = ellesmere_populate_all_graphic_levels(hwmgr); + result = polaris10_populate_all_graphic_levels(hwmgr); PP_ASSERT_WITH_CODE((0 == result), "Failed to populate SCLK during PopulateNewDPMClocksStates Function!", return result); @@ -3933,7 +3935,7 @@ static int ellesmere_populate_and_upload_sclk_mclk_dpm_levels( if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK + DPMTABLE_UPDATE_MCLK)) { /*populate MCLK dpm table to SMU7 */ - result = ellesmere_populate_all_memory_levels(hwmgr); + result = polaris10_populate_all_memory_levels(hwmgr); PP_ASSERT_WITH_CODE((0 == result), "Failed to populate MCLK during PopulateNewDPMClocksStates Function!", return result); @@ -3942,12 +3944,12 @@ static int ellesmere_populate_and_upload_sclk_mclk_dpm_levels( return result; } -static int ellesmere_trim_single_dpm_states(struct pp_hwmgr *hwmgr, - struct ellesmere_single_dpm_table *dpm_table, +static int polaris10_trim_single_dpm_states(struct pp_hwmgr *hwmgr, + struct polaris10_single_dpm_table *dpm_table, uint32_t low_limit, uint32_t high_limit) { uint32_t i; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); for (i = 0; i < dpm_table->count; i++) { if ((dpm_table->dpm_levels[i].value < low_limit) @@ -3962,43 +3964,43 @@ static int ellesmere_trim_single_dpm_states(struct pp_hwmgr *hwmgr, return 0; } -static int ellesmere_trim_dpm_states(struct pp_hwmgr *hwmgr, - const struct ellesmere_power_state *ellesmere_ps) +static int polaris10_trim_dpm_states(struct pp_hwmgr *hwmgr, + const struct polaris10_power_state *polaris10_ps) { int result = 0; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint32_t high_limit_count; - PP_ASSERT_WITH_CODE((ellesmere_ps->performance_level_count >= 1), + PP_ASSERT_WITH_CODE((polaris10_ps->performance_level_count >= 1), "power state did not have any performance level", return -1); - high_limit_count = (1 == ellesmere_ps->performance_level_count) ? 0 : 1; + high_limit_count = (1 == polaris10_ps->performance_level_count) ? 0 : 1; - ellesmere_trim_single_dpm_states(hwmgr, + polaris10_trim_single_dpm_states(hwmgr, &(data->dpm_table.sclk_table), - ellesmere_ps->performance_levels[0].engine_clock, - ellesmere_ps->performance_levels[high_limit_count].engine_clock); + polaris10_ps->performance_levels[0].engine_clock, + polaris10_ps->performance_levels[high_limit_count].engine_clock); - ellesmere_trim_single_dpm_states(hwmgr, + polaris10_trim_single_dpm_states(hwmgr, &(data->dpm_table.mclk_table), - ellesmere_ps->performance_levels[0].memory_clock, - ellesmere_ps->performance_levels[high_limit_count].memory_clock); + polaris10_ps->performance_levels[0].memory_clock, + polaris10_ps->performance_levels[high_limit_count].memory_clock); return result; } -static int ellesmere_generate_dpm_level_enable_mask( +static int polaris10_generate_dpm_level_enable_mask( struct pp_hwmgr *hwmgr, const void *input) { int result; const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - const struct ellesmere_power_state *ellesmere_ps = - cast_const_phw_ellesmere_power_state(states->pnew_state); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_power_state *polaris10_ps = + cast_const_phw_polaris10_power_state(states->pnew_state); - result = ellesmere_trim_dpm_states(hwmgr, ellesmere_ps); + result = polaris10_trim_dpm_states(hwmgr, polaris10_ps); if (result) return result; @@ -4012,30 +4014,30 @@ static int ellesmere_generate_dpm_level_enable_mask( return 0; } -int ellesmere_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) +int polaris10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable) { return smum_send_msg_to_smc(hwmgr->smumgr, enable ? PPSMC_MSG_UVDDPM_Enable : PPSMC_MSG_UVDDPM_Disable); } -int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) +int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable) { return smum_send_msg_to_smc(hwmgr->smumgr, enable? PPSMC_MSG_VCEDPM_Enable : PPSMC_MSG_VCEDPM_Disable); } -int ellesmere_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable) +int polaris10_enable_disable_samu_dpm(struct pp_hwmgr *hwmgr, bool enable) { return smum_send_msg_to_smc(hwmgr->smumgr, enable? PPSMC_MSG_SAMUDPM_Enable : PPSMC_MSG_SAMUDPM_Disable); } -int ellesmere_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) +int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint32_t mm_boot_level_offset, mm_boot_level_value; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -4065,25 +4067,25 @@ int ellesmere_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate) (uint32_t)(1 << data->smc_state_table.UvdBootLevel)); } - return ellesmere_enable_disable_uvd_dpm(hwmgr, !bgate); + return polaris10_enable_disable_uvd_dpm(hwmgr, !bgate); } -static int ellesmere_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) +static int polaris10_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) { const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - const struct ellesmere_power_state *ellesmere_nps = - cast_const_phw_ellesmere_power_state(states->pnew_state); - const struct ellesmere_power_state *ellesmere_cps = - cast_const_phw_ellesmere_power_state(states->pcurrent_state); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_power_state *polaris10_nps = + cast_const_phw_polaris10_power_state(states->pnew_state); + const struct polaris10_power_state *polaris10_cps = + cast_const_phw_polaris10_power_state(states->pcurrent_state); uint32_t mm_boot_level_offset, mm_boot_level_value; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); - if (ellesmere_nps->vce_clks.evclk > 0 && - (ellesmere_cps == NULL || ellesmere_cps->vce_clks.evclk == 0)) { + if (polaris10_nps->vce_clks.evclk > 0 && + (polaris10_cps == NULL || polaris10_cps->vce_clks.evclk == 0)) { data->smc_state_table.VceBootLevel = (uint8_t) (table_info->mm_dep_table->count - 1); @@ -4104,19 +4106,19 @@ static int ellesmere_update_vce_dpm(struct pp_hwmgr *hwmgr, const void *input) PPSMC_MSG_VCEDPM_SetEnabledMask, (uint32_t)1 << data->smc_state_table.VceBootLevel); - ellesmere_enable_disable_vce_dpm(hwmgr, true); - } else if (ellesmere_nps->vce_clks.evclk == 0 && - ellesmere_cps != NULL && - ellesmere_cps->vce_clks.evclk > 0) - ellesmere_enable_disable_vce_dpm(hwmgr, false); + polaris10_enable_disable_vce_dpm(hwmgr, true); + } else if (polaris10_nps->vce_clks.evclk == 0 && + polaris10_cps != NULL && + polaris10_cps->vce_clks.evclk > 0) + polaris10_enable_disable_vce_dpm(hwmgr, false); } return 0; } -int ellesmere_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate) +int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint32_t mm_boot_level_offset, mm_boot_level_value; struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -4142,12 +4144,12 @@ int ellesmere_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate) (uint32_t)(1 << data->smc_state_table.SamuBootLevel)); } - return ellesmere_enable_disable_samu_dpm(hwmgr, !bgate); + return polaris10_enable_disable_samu_dpm(hwmgr, !bgate); } -static int ellesmere_update_sclk_threshold(struct pp_hwmgr *hwmgr) +static int polaris10_update_sclk_threshold(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); int result = 0; uint32_t low_sclk_interrupt_threshold = 0; @@ -4163,7 +4165,7 @@ static int ellesmere_update_sclk_threshold(struct pp_hwmgr *hwmgr) CONVERT_FROM_HOST_TO_SMC_UL(low_sclk_interrupt_threshold); - result = ellesmere_copy_bytes_to_smc( + result = polaris10_copy_bytes_to_smc( hwmgr->smumgr, data->dpm_table_start + offsetof(SMU74_Discrete_DpmTable, @@ -4176,20 +4178,20 @@ static int ellesmere_update_sclk_threshold(struct pp_hwmgr *hwmgr) return result; } -static int ellesmere_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) +static int polaris10_program_mem_timing_parameters(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); if (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_OD_UPDATE_MCLK)) - return ellesmere_program_memory_timing_parameters(hwmgr); + return polaris10_program_memory_timing_parameters(hwmgr); return 0; } -static int ellesmere_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) +static int polaris10_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); if (0 == data->need_update_smu7_dpm_table) return 0; @@ -4198,7 +4200,7 @@ static int ellesmere_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) (data->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK + DPMTABLE_UPDATE_SCLK))) { - PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr), + PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), "Trying to Unfreeze SCLK DPM when DPM is disabled", ); PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, @@ -4210,7 +4212,7 @@ static int ellesmere_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) if ((0 == data->mclk_dpm_key_disabled) && (data->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { - PP_ASSERT_WITH_CODE(true == ellesmere_is_dpm_running(hwmgr), + PP_ASSERT_WITH_CODE(true == polaris10_is_dpm_running(hwmgr), "Trying to Unfreeze MCLK DPM when DPM is disabled", ); PP_ASSERT_WITH_CODE(0 == smum_send_msg_to_smc(hwmgr->smumgr, @@ -4224,15 +4226,15 @@ static int ellesmere_unfreeze_sclk_mclk_dpm(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_notify_link_speed_change_after_state_change( +static int polaris10_notify_link_speed_change_after_state_change( struct pp_hwmgr *hwmgr, const void *input) { const struct phm_set_power_state_input *states = (const struct phm_set_power_state_input *)input; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - const struct ellesmere_power_state *ellesmere_ps = - cast_const_phw_ellesmere_power_state(states->pnew_state); - uint16_t target_link_speed = ellesmere_get_maximum_link_speed(hwmgr, ellesmere_ps); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + const struct polaris10_power_state *polaris10_ps = + cast_const_phw_polaris10_power_state(states->pnew_state); + uint16_t target_link_speed = polaris10_get_maximum_link_speed(hwmgr, polaris10_ps); uint8_t request; if (data->pspp_notify_required) { @@ -4258,12 +4260,12 @@ static int ellesmere_notify_link_speed_change_after_state_change( return 0; } -static int ellesmere_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) +static int polaris10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input) { int tmp_result, result = 0; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); - tmp_result = ellesmere_find_dpm_states_clocks_in_dpm_table(hwmgr, input); + tmp_result = polaris10_find_dpm_states_clocks_in_dpm_table(hwmgr, input); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to find DPM states clocks in DPM table!", result = tmp_result); @@ -4271,47 +4273,47 @@ static int ellesmere_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *i if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) { tmp_result = - ellesmere_request_link_speed_change_before_state_change(hwmgr, input); + polaris10_request_link_speed_change_before_state_change(hwmgr, input); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to request link speed change before state change!", result = tmp_result); } - tmp_result = ellesmere_freeze_sclk_mclk_dpm(hwmgr); + tmp_result = polaris10_freeze_sclk_mclk_dpm(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to freeze SCLK MCLK DPM!", result = tmp_result); - tmp_result = ellesmere_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); + tmp_result = polaris10_populate_and_upload_sclk_mclk_dpm_levels(hwmgr, input); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to populate and upload SCLK MCLK DPM levels!", result = tmp_result); - tmp_result = ellesmere_generate_dpm_level_enable_mask(hwmgr, input); + tmp_result = polaris10_generate_dpm_level_enable_mask(hwmgr, input); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to generate DPM level enabled mask!", result = tmp_result); - tmp_result = ellesmere_update_vce_dpm(hwmgr, input); + tmp_result = polaris10_update_vce_dpm(hwmgr, input); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update VCE DPM!", result = tmp_result); - tmp_result = ellesmere_update_sclk_threshold(hwmgr); + tmp_result = polaris10_update_sclk_threshold(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to update SCLK threshold!", result = tmp_result); - tmp_result = ellesmere_program_mem_timing_parameters(hwmgr); + tmp_result = polaris10_program_mem_timing_parameters(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to program memory timing parameters!", result = tmp_result); - tmp_result = ellesmere_unfreeze_sclk_mclk_dpm(hwmgr); + tmp_result = polaris10_unfreeze_sclk_mclk_dpm(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to unfreeze SCLK MCLK DPM!", result = tmp_result); - tmp_result = ellesmere_upload_dpm_level_enable_mask(hwmgr); + tmp_result = polaris10_upload_dpm_level_enable_mask(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to upload DPM level enabled mask!", result = tmp_result); @@ -4319,7 +4321,7 @@ static int ellesmere_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *i if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PCIEPerformanceRequest)) { tmp_result = - ellesmere_notify_link_speed_change_after_state_change(hwmgr, input); + polaris10_notify_link_speed_change_after_state_change(hwmgr, input); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to notify link speed change after state change!", result = tmp_result); @@ -4328,7 +4330,7 @@ static int ellesmere_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *i return result; } -static int ellesmere_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) +static int polaris10_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_pwm) { hwmgr->thermal_controller. advanceFanControlParameters.usMaxFanPWM = us_max_fan_pwm; @@ -4340,14 +4342,14 @@ static int ellesmere_set_max_fan_pwm_output(struct pp_hwmgr *hwmgr, uint16_t us_ PPSMC_MSG_SetFanPwmMax, us_max_fan_pwm); } -int ellesmere_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) +int polaris10_notify_smc_display_change(struct pp_hwmgr *hwmgr, bool has_display) { PPSMC_Msg msg = has_display ? (PPSMC_Msg)PPSMC_HasDisplay : (PPSMC_Msg)PPSMC_NoDisplay; return (smum_send_msg_to_smc(hwmgr->smumgr, msg) == 0) ? 0 : -1; } -int ellesmere_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) +int polaris10_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwmgr) { uint32_t num_active_displays = 0; struct cgs_display_info info = {0}; @@ -4358,9 +4360,9 @@ int ellesmere_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwm num_active_displays = info.display_count; if (num_active_displays > 1) /* to do && (pHwMgr->pPECI->displayConfiguration.bMultiMonitorInSync != TRUE)) */ - ellesmere_notify_smc_display_change(hwmgr, false); + polaris10_notify_smc_display_change(hwmgr, false); else - ellesmere_notify_smc_display_change(hwmgr, true); + polaris10_notify_smc_display_change(hwmgr, true); return 0; } @@ -4371,9 +4373,9 @@ int ellesmere_notify_smc_display_config_after_ps_adjustment(struct pp_hwmgr *hwm * @param hwmgr the address of the powerplay hardware manager. * @return always OK */ -int ellesmere_program_display_gap(struct pp_hwmgr *hwmgr) +int polaris10_program_display_gap(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint32_t num_active_displays = 0; uint32_t display_gap = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_DISPLAY_GAP_CNTL); uint32_t display_gap2; @@ -4409,16 +4411,15 @@ int ellesmere_program_display_gap(struct pp_hwmgr *hwmgr) cgs_write_ind_register(hwmgr->device, CGS_IND_REG__SMC, data->soft_regs_start + offsetof(SMU74_SoftRegisters, VBlankTimeout), (frame_time_in_us - pre_vbi_time_in_us)); - if (num_active_displays == 1) - ellesmere_notify_smc_display_change(hwmgr, true); + polaris10_notify_smc_display_change(hwmgr, num_active_displays != 0); return 0; } -int ellesmere_display_configuration_changed_task(struct pp_hwmgr *hwmgr) +int polaris10_display_configuration_changed_task(struct pp_hwmgr *hwmgr) { - return ellesmere_program_display_gap(hwmgr); + return polaris10_program_display_gap(hwmgr); } /** @@ -4428,7 +4429,7 @@ int ellesmere_display_configuration_changed_task(struct pp_hwmgr *hwmgr) * @param usMaxFanRpm: max operating fan RPM value. * @return The response that came from the SMC. */ -static int ellesmere_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm) +static int polaris10_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_max_fan_rpm) { hwmgr->thermal_controller. advanceFanControlParameters.usMaxFanRPM = us_max_fan_rpm; @@ -4440,15 +4441,15 @@ static int ellesmere_set_max_fan_rpm_output(struct pp_hwmgr *hwmgr, uint16_t us_ PPSMC_MSG_SetFanRpmMax, us_max_fan_rpm); } -int ellesmere_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, +int polaris10_register_internal_thermal_interrupt(struct pp_hwmgr *hwmgr, const void *thermal_interrupt_info) { return 0; } -bool ellesmere_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) +bool polaris10_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); bool is_update_required = false; struct cgs_display_info info = {0, 0, NULL}; @@ -4459,14 +4460,16 @@ bool ellesmere_check_smc_update_required_for_display_configuration(struct pp_hwm /* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) { cgs_get_min_clock_settings(hwmgr->device, &min_clocks); - if (min_clocks.engineClockInSR != data->display_timing.minClockInSR) + if (min_clocks.engineClockInSR != data->display_timing.minClockInSR && + (min_clocks.engineClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK || + data->display_timing.minClockInSR >= POLARIS10_MINIMUM_ENGINE_CLOCK)) is_update_required = true; */ return is_update_required; } -static inline bool ellesmere_are_power_levels_equal(const struct ellesmere_performance_level *pl1, - const struct ellesmere_performance_level *pl2) +static inline bool polaris10_are_power_levels_equal(const struct polaris10_performance_level *pl1, + const struct polaris10_performance_level *pl2) { return ((pl1->memory_clock == pl2->memory_clock) && (pl1->engine_clock == pl2->engine_clock) && @@ -4474,10 +4477,10 @@ static inline bool ellesmere_are_power_levels_equal(const struct ellesmere_perfo (pl1->pcie_lane == pl2->pcie_lane)); } -int ellesmere_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) +int polaris10_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal) { - const struct ellesmere_power_state *psa = cast_const_phw_ellesmere_power_state(pstate1); - const struct ellesmere_power_state *psb = cast_const_phw_ellesmere_power_state(pstate2); + const struct polaris10_power_state *psa = cast_const_phw_polaris10_power_state(pstate1); + const struct polaris10_power_state *psb = cast_const_phw_polaris10_power_state(pstate2); int i; if (pstate1 == NULL || pstate2 == NULL || equal == NULL) @@ -4490,7 +4493,7 @@ int ellesmere_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_powe } for (i = 0; i < psa->performance_level_count; i++) { - if (!ellesmere_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { + if (!polaris10_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) { /* If we have found even one performance level pair that is different the states are different. */ *equal = false; return 0; @@ -4505,9 +4508,9 @@ int ellesmere_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_powe return 0; } -int ellesmere_upload_mc_firmware(struct pp_hwmgr *hwmgr) +int polaris10_upload_mc_firmware(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint32_t vbios_version; @@ -4527,7 +4530,7 @@ int ellesmere_upload_mc_firmware(struct pp_hwmgr *hwmgr) * PPMCME_FirmwareDescriptorEntry *pfd = NULL; pfd = &tonga_mcmeFirmware; if (0 == PHM_READ_FIELD(hwmgr->device, MC_SEQ_SUP_CNTL, RUN)) - ellesmere_load_mc_microcode(hwmgr, pfd->dpmThreshold, + polaris10_load_mc_microcode(hwmgr, pfd->dpmThreshold, pfd->cfgArray, pfd->cfgSize, pfd->ioDebugArray, pfd->ioDebugSize, pfd->ucodeArray, pfd->ucodeSize); */ @@ -4540,9 +4543,9 @@ int ellesmere_upload_mc_firmware(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_read_clock_registers(struct pp_hwmgr *hwmgr) +static int polaris10_read_clock_registers(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); data->clock_registers.vCG_SPLL_FUNC_CNTL = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__SMC, ixCG_SPLL_FUNC_CNTL) @@ -4565,9 +4568,9 @@ static int ellesmere_read_clock_registers(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_get_memory_type(struct pp_hwmgr *hwmgr) +static int polaris10_get_memory_type(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint32_t temp; temp = cgs_read_register(hwmgr->device, mmMC_SEQ_MISC0); @@ -4585,7 +4588,7 @@ static int ellesmere_get_memory_type(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_enable_acpi_power_management(struct pp_hwmgr *hwmgr) +static int polaris10_enable_acpi_power_management(struct pp_hwmgr *hwmgr) { PHM_WRITE_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, GENERAL_PWRMGT, STATIC_PM_EN, 1); @@ -4599,9 +4602,9 @@ static int ellesmere_enable_acpi_power_management(struct pp_hwmgr *hwmgr) * @param hwmgr the address of the powerplay hardware manager. * @return always 0 */ -static int ellesmere_init_power_gate_state(struct pp_hwmgr *hwmgr) +static int polaris10_init_power_gate_state(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); data->uvd_power_gated = false; data->vce_power_gated = false; @@ -4610,33 +4613,33 @@ static int ellesmere_init_power_gate_state(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_init_sclk_threshold(struct pp_hwmgr *hwmgr) +static int polaris10_init_sclk_threshold(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); data->low_sclk_interrupt_threshold = 0; return 0; } -int ellesmere_setup_asic_task(struct pp_hwmgr *hwmgr) +int polaris10_setup_asic_task(struct pp_hwmgr *hwmgr) { int tmp_result, result = 0; - ellesmere_upload_mc_firmware(hwmgr); + polaris10_upload_mc_firmware(hwmgr); - tmp_result = ellesmere_read_clock_registers(hwmgr); + tmp_result = polaris10_read_clock_registers(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to read clock registers!", result = tmp_result); - tmp_result = ellesmere_get_memory_type(hwmgr); + tmp_result = polaris10_get_memory_type(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to get memory type!", result = tmp_result); - tmp_result = ellesmere_enable_acpi_power_management(hwmgr); + tmp_result = polaris10_enable_acpi_power_management(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to enable ACPI power management!", result = tmp_result); - tmp_result = ellesmere_init_power_gate_state(hwmgr); + tmp_result = polaris10_init_power_gate_state(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to init power gate state!", result = tmp_result); @@ -4644,68 +4647,198 @@ int ellesmere_setup_asic_task(struct pp_hwmgr *hwmgr) PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to get MC microcode version!", result = tmp_result); - tmp_result = ellesmere_init_sclk_threshold(hwmgr); + tmp_result = polaris10_init_sclk_threshold(hwmgr); PP_ASSERT_WITH_CODE((0 == tmp_result), "Failed to init sclk threshold!", result = tmp_result); return result; } -static const struct pp_hwmgr_func ellesmere_hwmgr_funcs = { - .backend_init = &ellesmere_hwmgr_backend_init, - .backend_fini = &ellesmere_hwmgr_backend_fini, - .asic_setup = &ellesmere_setup_asic_task, - .dynamic_state_management_enable = &ellesmere_enable_dpm_tasks, - .apply_state_adjust_rules = ellesmere_apply_state_adjust_rules, - .force_dpm_level = &ellesmere_force_dpm_level, - .power_state_set = ellesmere_set_power_state_tasks, - .get_power_state_size = ellesmere_get_power_state_size, - .get_mclk = ellesmere_dpm_get_mclk, - .get_sclk = ellesmere_dpm_get_sclk, - .patch_boot_state = ellesmere_dpm_patch_boot_state, - .get_pp_table_entry = ellesmere_get_pp_table_entry, +static int polaris10_get_pp_table(struct pp_hwmgr *hwmgr, char **table) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + *table = (char *)&data->smc_state_table; + + return sizeof(struct SMU74_Discrete_DpmTable); +} + +static int polaris10_set_pp_table(struct pp_hwmgr *hwmgr, const char *buf, size_t size) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + void *table = (void *)&data->smc_state_table; + + memcpy(table, buf, size); + + return 0; +} + +static int polaris10_force_clock_level(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, int level) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + + if (hwmgr->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) + return -EINVAL; + + switch (type) { + case PP_SCLK: + if (!data->sclk_dpm_key_disabled) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_SCLKDPM_SetEnabledMask, + (1 << level)); + break; + case PP_MCLK: + if (!data->mclk_dpm_key_disabled) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_MCLKDPM_SetEnabledMask, + (1 << level)); + break; + case PP_PCIE: + if (!data->pcie_dpm_key_disabled) + smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, + PPSMC_MSG_PCIeDPM_ForceLevel, + (1 << level)); + break; + default: + break; + } + + return 0; +} + +static uint16_t polaris10_get_current_pcie_speed(struct pp_hwmgr *hwmgr) +{ + uint32_t speedCntl = 0; + + /* mmPCIE_PORT_INDEX rename as mmPCIE_INDEX */ + speedCntl = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__PCIE, + ixPCIE_LC_SPEED_CNTL); + return((uint16_t)PHM_GET_FIELD(speedCntl, + PCIE_LC_SPEED_CNTL, LC_CURRENT_DATA_RATE)); +} + +static int polaris10_print_clock_levels(struct pp_hwmgr *hwmgr, + enum pp_clock_type type, char *buf) +{ + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_single_dpm_table *sclk_table = &(data->dpm_table.sclk_table); + struct polaris10_single_dpm_table *mclk_table = &(data->dpm_table.mclk_table); + struct polaris10_single_dpm_table *pcie_table = &(data->dpm_table.pcie_speed_table); + int i, now, size = 0; + uint32_t clock, pcie_speed; + + switch (type) { + case PP_SCLK: + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetSclkFrequency); + clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); + + for (i = 0; i < sclk_table->count; i++) { + if (clock > sclk_table->dpm_levels[i].value) + continue; + break; + } + now = i; + + for (i = 0; i < sclk_table->count; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, sclk_table->dpm_levels[i].value / 100, + (i == now) ? "*" : ""); + break; + case PP_MCLK: + smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_MSG_API_GetMclkFrequency); + clock = cgs_read_register(hwmgr->device, mmSMC_MSG_ARG_0); + + for (i = 0; i < mclk_table->count; i++) { + if (clock > mclk_table->dpm_levels[i].value) + continue; + break; + } + now = i; + + for (i = 0; i < mclk_table->count; i++) + size += sprintf(buf + size, "%d: %uMhz %s\n", + i, mclk_table->dpm_levels[i].value / 100, + (i == now) ? "*" : ""); + break; + case PP_PCIE: + pcie_speed = polaris10_get_current_pcie_speed(hwmgr); + for (i = 0; i < pcie_table->count; i++) { + if (pcie_speed != pcie_table->dpm_levels[i].value) + continue; + break; + } + now = i; + + for (i = 0; i < pcie_table->count; i++) + size += sprintf(buf + size, "%d: %s %s\n", i, + (pcie_table->dpm_levels[i].value == 0) ? "2.5GB, x8" : + (pcie_table->dpm_levels[i].value == 1) ? "5.0GB, x16" : + (pcie_table->dpm_levels[i].value == 2) ? "8.0GB, x16" : "", + (i == now) ? "*" : ""); + break; + default: + break; + } + return size; +} + +static const struct pp_hwmgr_func polaris10_hwmgr_funcs = { + .backend_init = &polaris10_hwmgr_backend_init, + .backend_fini = &polaris10_hwmgr_backend_fini, + .asic_setup = &polaris10_setup_asic_task, + .dynamic_state_management_enable = &polaris10_enable_dpm_tasks, + .apply_state_adjust_rules = polaris10_apply_state_adjust_rules, + .force_dpm_level = &polaris10_force_dpm_level, + .power_state_set = polaris10_set_power_state_tasks, + .get_power_state_size = polaris10_get_power_state_size, + .get_mclk = polaris10_dpm_get_mclk, + .get_sclk = polaris10_dpm_get_sclk, + .patch_boot_state = polaris10_dpm_patch_boot_state, + .get_pp_table_entry = polaris10_get_pp_table_entry, .get_num_of_pp_table_entries = tonga_get_number_of_powerplay_table_entries, - .print_current_perforce_level = ellesmere_print_current_perforce_level, - .powerdown_uvd = ellesmere_phm_powerdown_uvd, - .powergate_uvd = ellesmere_phm_powergate_uvd, - .powergate_vce = ellesmere_phm_powergate_vce, - .disable_clock_power_gating = ellesmere_phm_disable_clock_power_gating, - .update_clock_gatings = ellesmere_phm_update_clock_gatings, - .notify_smc_display_config_after_ps_adjustment = ellesmere_notify_smc_display_config_after_ps_adjustment, - .display_config_changed = ellesmere_display_configuration_changed_task, - .set_max_fan_pwm_output = ellesmere_set_max_fan_pwm_output, - .set_max_fan_rpm_output = ellesmere_set_max_fan_rpm_output, - .get_temperature = ellesmere_thermal_get_temperature, - .stop_thermal_controller = ellesmere_thermal_stop_thermal_controller, - .get_fan_speed_info = ellesmere_fan_ctrl_get_fan_speed_info, - .get_fan_speed_percent = ellesmere_fan_ctrl_get_fan_speed_percent, - .set_fan_speed_percent = ellesmere_fan_ctrl_set_fan_speed_percent, - .reset_fan_speed_to_default = ellesmere_fan_ctrl_reset_fan_speed_to_default, - .get_fan_speed_rpm = ellesmere_fan_ctrl_get_fan_speed_rpm, - .set_fan_speed_rpm = ellesmere_fan_ctrl_set_fan_speed_rpm, - .uninitialize_thermal_controller = ellesmere_thermal_ctrl_uninitialize_thermal_controller, - .register_internal_thermal_interrupt = ellesmere_register_internal_thermal_interrupt, - .check_smc_update_required_for_display_configuration = ellesmere_check_smc_update_required_for_display_configuration, - .check_states_equal = ellesmere_check_states_equal, - .get_pp_table = ellesmere_get_pp_table, - .set_pp_table = ellesmere_set_pp_table, - .force_clock_level = ellesmere_force_clock_level, - .print_clock_levels = ellesmere_print_clock_levels, - .enable_per_cu_power_gating = ellesmere_phm_enable_per_cu_power_gating, + .print_current_perforce_level = polaris10_print_current_perforce_level, + .powerdown_uvd = polaris10_phm_powerdown_uvd, + .powergate_uvd = polaris10_phm_powergate_uvd, + .powergate_vce = polaris10_phm_powergate_vce, + .disable_clock_power_gating = polaris10_phm_disable_clock_power_gating, + .update_clock_gatings = polaris10_phm_update_clock_gatings, + .notify_smc_display_config_after_ps_adjustment = polaris10_notify_smc_display_config_after_ps_adjustment, + .display_config_changed = polaris10_display_configuration_changed_task, + .set_max_fan_pwm_output = polaris10_set_max_fan_pwm_output, + .set_max_fan_rpm_output = polaris10_set_max_fan_rpm_output, + .get_temperature = polaris10_thermal_get_temperature, + .stop_thermal_controller = polaris10_thermal_stop_thermal_controller, + .get_fan_speed_info = polaris10_fan_ctrl_get_fan_speed_info, + .get_fan_speed_percent = polaris10_fan_ctrl_get_fan_speed_percent, + .set_fan_speed_percent = polaris10_fan_ctrl_set_fan_speed_percent, + .reset_fan_speed_to_default = polaris10_fan_ctrl_reset_fan_speed_to_default, + .get_fan_speed_rpm = polaris10_fan_ctrl_get_fan_speed_rpm, + .set_fan_speed_rpm = polaris10_fan_ctrl_set_fan_speed_rpm, + .uninitialize_thermal_controller = polaris10_thermal_ctrl_uninitialize_thermal_controller, + .register_internal_thermal_interrupt = polaris10_register_internal_thermal_interrupt, + .check_smc_update_required_for_display_configuration = polaris10_check_smc_update_required_for_display_configuration, + .check_states_equal = polaris10_check_states_equal, + .get_pp_table = polaris10_get_pp_table, + .set_pp_table = polaris10_set_pp_table, + .force_clock_level = polaris10_force_clock_level, + .print_clock_levels = polaris10_print_clock_levels, + .enable_per_cu_power_gating = polaris10_phm_enable_per_cu_power_gating, }; -int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr) +int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data; + struct polaris10_hwmgr *data; - data = kzalloc (sizeof(struct ellesmere_hwmgr), GFP_KERNEL); + data = kzalloc (sizeof(struct polaris10_hwmgr), GFP_KERNEL); if (data == NULL) return -ENOMEM; hwmgr->backend = data; - hwmgr->hwmgr_func = &ellesmere_hwmgr_funcs; + hwmgr->hwmgr_func = &polaris10_hwmgr_funcs; hwmgr->pptable_func = &tonga_pptable_funcs; - pp_ellesmere_thermal_initialize(hwmgr); + pp_polaris10_thermal_initialize(hwmgr); return 0; } diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h index dd6c60bb7513..2507404fd51e 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_hwmgr.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_hwmgr.h @@ -21,81 +21,81 @@ * */ -#ifndef ELLESMERE_HWMGR_H -#define ELLESMERE_HWMGR_H +#ifndef POLARIS10_HWMGR_H +#define POLARIS10_HWMGR_H #include "hwmgr.h" #include "smu74.h" #include "smu74_discrete.h" #include "ppatomctrl.h" -#include "ellesmere_ppsmc.h" -#include "ellesmere_powertune.h" +#include "polaris10_ppsmc.h" +#include "polaris10_powertune.h" -#define ELLESMERE_MAX_HARDWARE_POWERLEVELS 2 +#define POLARIS10_MAX_HARDWARE_POWERLEVELS 2 -#define ELLESMERE_VOLTAGE_CONTROL_NONE 0x0 -#define ELLESMERE_VOLTAGE_CONTROL_BY_GPIO 0x1 -#define ELLESMERE_VOLTAGE_CONTROL_BY_SVID2 0x2 -#define ELLESMERE_VOLTAGE_CONTROL_MERGED 0x3 +#define POLARIS10_VOLTAGE_CONTROL_NONE 0x0 +#define POLARIS10_VOLTAGE_CONTROL_BY_GPIO 0x1 +#define POLARIS10_VOLTAGE_CONTROL_BY_SVID2 0x2 +#define POLARIS10_VOLTAGE_CONTROL_MERGED 0x3 #define DPMTABLE_OD_UPDATE_SCLK 0x00000001 #define DPMTABLE_OD_UPDATE_MCLK 0x00000002 #define DPMTABLE_UPDATE_SCLK 0x00000004 #define DPMTABLE_UPDATE_MCLK 0x00000008 -struct ellesmere_performance_level { +struct polaris10_performance_level { uint32_t memory_clock; uint32_t engine_clock; uint16_t pcie_gen; uint16_t pcie_lane; }; -struct ellesmere_uvd_clocks { +struct polaris10_uvd_clocks { uint32_t vclk; uint32_t dclk; }; -struct ellesmere_vce_clocks { +struct polaris10_vce_clocks { uint32_t evclk; uint32_t ecclk; }; -struct ellesmere_power_state { +struct polaris10_power_state { uint32_t magic; - struct ellesmere_uvd_clocks uvd_clks; - struct ellesmere_vce_clocks vce_clks; + struct polaris10_uvd_clocks uvd_clks; + struct polaris10_vce_clocks vce_clks; uint32_t sam_clk; uint16_t performance_level_count; bool dc_compatible; uint32_t sclk_threshold; - struct ellesmere_performance_level performance_levels[ELLESMERE_MAX_HARDWARE_POWERLEVELS]; + struct polaris10_performance_level performance_levels[POLARIS10_MAX_HARDWARE_POWERLEVELS]; }; -struct ellesmere_dpm_level { +struct polaris10_dpm_level { bool enabled; uint32_t value; uint32_t param1; }; -#define ELLESMERE_MAX_DEEPSLEEP_DIVIDER_ID 5 +#define POLARIS10_MAX_DEEPSLEEP_DIVIDER_ID 5 #define MAX_REGULAR_DPM_NUMBER 8 -#define ELLESMERE_MINIMUM_ENGINE_CLOCK 2500 +#define POLARIS10_MINIMUM_ENGINE_CLOCK 2500 -struct ellesmere_single_dpm_table { +struct polaris10_single_dpm_table { uint32_t count; - struct ellesmere_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; + struct polaris10_dpm_level dpm_levels[MAX_REGULAR_DPM_NUMBER]; }; -struct ellesmere_dpm_table { - struct ellesmere_single_dpm_table sclk_table; - struct ellesmere_single_dpm_table mclk_table; - struct ellesmere_single_dpm_table pcie_speed_table; - struct ellesmere_single_dpm_table vddc_table; - struct ellesmere_single_dpm_table vddci_table; - struct ellesmere_single_dpm_table mvdd_table; +struct polaris10_dpm_table { + struct polaris10_single_dpm_table sclk_table; + struct polaris10_single_dpm_table mclk_table; + struct polaris10_single_dpm_table pcie_speed_table; + struct polaris10_single_dpm_table vddc_table; + struct polaris10_single_dpm_table vddci_table; + struct polaris10_single_dpm_table mvdd_table; }; -struct ellesmere_clock_registers { +struct polaris10_clock_registers { uint32_t vCG_SPLL_FUNC_CNTL; uint32_t vCG_SPLL_FUNC_CNTL_2; uint32_t vCG_SPLL_FUNC_CNTL_3; @@ -116,19 +116,19 @@ struct ellesmere_clock_registers { #define DISABLE_MC_LOADMICROCODE 1 #define DISABLE_MC_CFGPROGRAMMING 2 -struct ellesmere_voltage_smio_registers { +struct polaris10_voltage_smio_registers { uint32_t vS0_VID_LOWER_SMIO_CNTL; }; -#define ELLESMERE_MAX_LEAKAGE_COUNT 8 +#define POLARIS10_MAX_LEAKAGE_COUNT 8 -struct ellesmere_leakage_voltage { +struct polaris10_leakage_voltage { uint16_t count; - uint16_t leakage_id[ELLESMERE_MAX_LEAKAGE_COUNT]; - uint16_t actual_voltage[ELLESMERE_MAX_LEAKAGE_COUNT]; + uint16_t leakage_id[POLARIS10_MAX_LEAKAGE_COUNT]; + uint16_t actual_voltage[POLARIS10_MAX_LEAKAGE_COUNT]; }; -struct ellesmere_vbios_boot_state { +struct polaris10_vbios_boot_state { uint16_t mvdd_bootup_value; uint16_t vddc_bootup_value; uint16_t vddci_bootup_value; @@ -139,19 +139,19 @@ struct ellesmere_vbios_boot_state { }; /* Ultra Low Voltage parameter structure */ -struct ellesmere_ulv_parm { +struct polaris10_ulv_parm { bool ulv_supported; uint32_t cg_ulv_parameter; uint32_t ulv_volt_change_delay; - struct ellesmere_performance_level ulv_power_level; + struct polaris10_performance_level ulv_power_level; }; -struct ellesmere_display_timing { +struct polaris10_display_timing { uint32_t min_clock_in_sr; uint32_t num_existing_displays; }; -struct ellesmere_dpmlevel_enable_mask { +struct polaris10_dpmlevel_enable_mask { uint32_t uvd_dpm_enable_mask; uint32_t vce_dpm_enable_mask; uint32_t acp_dpm_enable_mask; @@ -161,22 +161,22 @@ struct ellesmere_dpmlevel_enable_mask { uint32_t pcie_dpm_enable_mask; }; -struct ellesmere_pcie_perf_range { +struct polaris10_pcie_perf_range { uint16_t max; uint16_t min; }; -struct ellesmere_range_table { +struct polaris10_range_table { uint32_t trans_lower_frequency; /* in 10khz */ uint32_t trans_upper_frequency; }; -struct ellesmere_hwmgr { - struct ellesmere_dpm_table dpm_table; - struct ellesmere_dpm_table golden_dpm_table; +struct polaris10_hwmgr { + struct polaris10_dpm_table dpm_table; + struct polaris10_dpm_table golden_dpm_table; SMU74_Discrete_DpmTable smc_state_table; struct SMU74_Discrete_Ulv ulv_setting; - struct ellesmere_range_table range_table[NUM_SCLK_RANGE]; + struct polaris10_range_table range_table[NUM_SCLK_RANGE]; uint32_t voting_rights_clients0; uint32_t voting_rights_clients1; uint32_t voting_rights_clients2; @@ -192,8 +192,8 @@ struct ellesmere_hwmgr { uint32_t active_auto_throttle_sources; - struct ellesmere_clock_registers clock_registers; - struct ellesmere_voltage_smio_registers voltage_smio_registers; + struct polaris10_clock_registers clock_registers; + struct polaris10_voltage_smio_registers voltage_smio_registers; bool is_memory_gddr5; uint16_t acpi_vddc; @@ -203,8 +203,8 @@ struct ellesmere_hwmgr { uint32_t pcie_gen_cap; uint32_t pcie_lane_cap; uint32_t pcie_spc_cap; - struct ellesmere_leakage_voltage vddc_leakage; - struct ellesmere_leakage_voltage Vddci_leakage; + struct polaris10_leakage_voltage vddc_leakage; + struct polaris10_leakage_voltage Vddci_leakage; uint32_t mvdd_control; uint32_t vddc_mask_low; @@ -218,7 +218,7 @@ struct ellesmere_hwmgr { uint32_t mclk_edc_enable_threshold; uint32_t mclk_edcwr_enable_threshold; bool is_uvd_enabled; - struct ellesmere_vbios_boot_state vbios_boot_state; + struct polaris10_vbios_boot_state vbios_boot_state; bool pcie_performance_request; bool battery_state; @@ -250,7 +250,7 @@ struct ellesmere_hwmgr { bool performance_request_registered; /* ---- Low Power Features ---- */ - struct ellesmere_ulv_parm ulv; + struct polaris10_ulv_parm ulv; /* ---- CAC Stuff ---- */ uint32_t cac_table_start; @@ -264,7 +264,7 @@ struct ellesmere_hwmgr { bool enable_tdc_limit_feature; bool enable_pkg_pwr_tracking_feature; bool disable_uvd_power_tune_feature; - struct ellesmere_pt_defaults *power_tune_defaults; + struct polaris10_pt_defaults *power_tune_defaults; struct SMU74_Discrete_PmFuses power_tune_table; uint32_t dte_tj_offset; uint32_t fast_watermark_threshold; @@ -273,20 +273,20 @@ struct ellesmere_hwmgr { bool vddc_phase_shed_control; /* ---- DI/DT ---- */ - struct ellesmere_display_timing display_timing; + struct polaris10_display_timing display_timing; uint32_t bif_sclk_table[SMU74_MAX_LEVELS_LINK]; /* ---- Thermal Temperature Setting ---- */ - struct ellesmere_dpmlevel_enable_mask dpm_level_enable_mask; + struct polaris10_dpmlevel_enable_mask dpm_level_enable_mask; uint32_t need_update_smu7_dpm_table; uint32_t sclk_dpm_key_disabled; uint32_t mclk_dpm_key_disabled; uint32_t pcie_dpm_key_disabled; uint32_t min_engine_clocks; - struct ellesmere_pcie_perf_range pcie_gen_performance; - struct ellesmere_pcie_perf_range pcie_lane_performance; - struct ellesmere_pcie_perf_range pcie_gen_power_saving; - struct ellesmere_pcie_perf_range pcie_lane_power_saving; + struct polaris10_pcie_perf_range pcie_gen_performance; + struct polaris10_pcie_perf_range pcie_lane_performance; + struct polaris10_pcie_perf_range pcie_gen_power_saving; + struct polaris10_pcie_perf_range pcie_lane_power_saving; bool use_pcie_performance_levels; bool use_pcie_power_saving_levels; uint32_t activity_target[SMU74_MAX_LEVELS_GRAPHICS]; @@ -312,43 +312,43 @@ struct ellesmere_hwmgr { }; /* To convert to Q8.8 format for firmware */ -#define ELLESMERE_Q88_FORMAT_CONVERSION_UNIT 256 - -enum Ellesmere_I2CLineID { - Ellesmere_I2CLineID_DDC1 = 0x90, - Ellesmere_I2CLineID_DDC2 = 0x91, - Ellesmere_I2CLineID_DDC3 = 0x92, - Ellesmere_I2CLineID_DDC4 = 0x93, - Ellesmere_I2CLineID_DDC5 = 0x94, - Ellesmere_I2CLineID_DDC6 = 0x95, - Ellesmere_I2CLineID_SCLSDA = 0x96, - Ellesmere_I2CLineID_DDCVGA = 0x97 +#define POLARIS10_Q88_FORMAT_CONVERSION_UNIT 256 + +enum Polaris10_I2CLineID { + Polaris10_I2CLineID_DDC1 = 0x90, + Polaris10_I2CLineID_DDC2 = 0x91, + Polaris10_I2CLineID_DDC3 = 0x92, + Polaris10_I2CLineID_DDC4 = 0x93, + Polaris10_I2CLineID_DDC5 = 0x94, + Polaris10_I2CLineID_DDC6 = 0x95, + Polaris10_I2CLineID_SCLSDA = 0x96, + Polaris10_I2CLineID_DDCVGA = 0x97 }; -#define ELLESMERE_I2C_DDC1DATA 0 -#define ELLESMERE_I2C_DDC1CLK 1 -#define ELLESMERE_I2C_DDC2DATA 2 -#define ELLESMERE_I2C_DDC2CLK 3 -#define ELLESMERE_I2C_DDC3DATA 4 -#define ELLESMERE_I2C_DDC3CLK 5 -#define ELLESMERE_I2C_SDA 40 -#define ELLESMERE_I2C_SCL 41 -#define ELLESMERE_I2C_DDC4DATA 65 -#define ELLESMERE_I2C_DDC4CLK 66 -#define ELLESMERE_I2C_DDC5DATA 0x48 -#define ELLESMERE_I2C_DDC5CLK 0x49 -#define ELLESMERE_I2C_DDC6DATA 0x4a -#define ELLESMERE_I2C_DDC6CLK 0x4b -#define ELLESMERE_I2C_DDCVGADATA 0x4c -#define ELLESMERE_I2C_DDCVGACLK 0x4d - -#define ELLESMERE_UNUSED_GPIO_PIN 0x7F - -int ellesemere_hwmgr_init(struct pp_hwmgr *hwmgr); - -int ellesmere_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate); -int ellesmere_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate); -int ellesmere_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); +#define POLARIS10_I2C_DDC1DATA 0 +#define POLARIS10_I2C_DDC1CLK 1 +#define POLARIS10_I2C_DDC2DATA 2 +#define POLARIS10_I2C_DDC2CLK 3 +#define POLARIS10_I2C_DDC3DATA 4 +#define POLARIS10_I2C_DDC3CLK 5 +#define POLARIS10_I2C_SDA 40 +#define POLARIS10_I2C_SCL 41 +#define POLARIS10_I2C_DDC4DATA 65 +#define POLARIS10_I2C_DDC4CLK 66 +#define POLARIS10_I2C_DDC5DATA 0x48 +#define POLARIS10_I2C_DDC5CLK 0x49 +#define POLARIS10_I2C_DDC6DATA 0x4a +#define POLARIS10_I2C_DDC6CLK 0x4b +#define POLARIS10_I2C_DDCVGADATA 0x4c +#define POLARIS10_I2C_DDCVGACLK 0x4d + +#define POLARIS10_UNUSED_GPIO_PIN 0x7F + +int polaris10_hwmgr_init(struct pp_hwmgr *hwmgr); + +int polaris10_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_update_samu_dpm(struct pp_hwmgr *hwmgr, bool bgate); +int polaris10_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable); #endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c index ff41c41b0b0f..4d97326517e5 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.c @@ -23,16 +23,16 @@ #include "hwmgr.h" #include "smumgr.h" -#include "ellesmere_hwmgr.h" -#include "ellesmere_powertune.h" -#include "ellesmere_smumgr.h" +#include "polaris10_hwmgr.h" +#include "polaris10_powertune.h" +#include "polaris10_smumgr.h" #include "smu74_discrete.h" #include "pp_debug.h" #define VOLTAGE_SCALE 4 #define POWERTUNE_DEFAULT_SET_MAX 1 -struct ellesmere_pt_defaults ellesmere_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { +struct polaris10_pt_defaults polaris10_power_tune_data_set_array[POWERTUNE_DEFAULT_SET_MAX] = { /* sviLoadLIneEn, SviLoadLineVddC, TDC_VDDC_ThrottleReleaseLimitPerc, TDC_MAWt, * TdcWaterfallCtl, DTEAmbientTempBase, DisplayCac, BAPM_TEMP_GRADIENT */ { 1, 0xF, 0xFD, 0x19, 5, 45, 0, 0xB0000, @@ -40,27 +40,27 @@ struct ellesmere_pt_defaults ellesmere_power_tune_data_set_array[POWERTUNE_DEFAU { 0x17C, 0x172, 0x180, 0x1BC, 0x1B3, 0x1BD, 0x206, 0x200, 0x203, 0x25D, 0x25A, 0x255, 0x2C3, 0x2C5, 0x2B4 } }, }; -void ellesmere_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) +void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *ellesmere_hwmgr = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *polaris10_hwmgr = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); if (table_info && table_info->cac_dtp_table->usPowerTuneDataSetID <= POWERTUNE_DEFAULT_SET_MAX && table_info->cac_dtp_table->usPowerTuneDataSetID) - ellesmere_hwmgr->power_tune_defaults = - &ellesmere_power_tune_data_set_array + polaris10_hwmgr->power_tune_defaults = + &polaris10_power_tune_data_set_array [table_info->cac_dtp_table->usPowerTuneDataSetID - 1]; else - ellesmere_hwmgr->power_tune_defaults = &ellesmere_power_tune_data_set_array[0]; + polaris10_hwmgr->power_tune_defaults = &polaris10_power_tune_data_set_array[0]; } -int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) +int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_pt_defaults *defaults = data->power_tune_defaults; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_pt_defaults *defaults = data->power_tune_defaults; SMU74_Discrete_DpmTable *dpm_table = &(data->smc_state_table); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -101,10 +101,10 @@ int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_populate_svi_load_line(struct pp_hwmgr *hwmgr) +static int polaris10_populate_svi_load_line(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_pt_defaults *defaults = data->power_tune_defaults; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_pt_defaults *defaults = data->power_tune_defaults; data->power_tune_table.SviLoadLineEn = defaults->SviLoadLineEn; data->power_tune_table.SviLoadLineVddC = defaults->SviLoadLineVddC; @@ -114,13 +114,13 @@ static int ellesmere_populate_svi_load_line(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_populate_tdc_limit(struct pp_hwmgr *hwmgr) +static int polaris10_populate_tdc_limit(struct pp_hwmgr *hwmgr) { uint16_t tdc_limit; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); - struct ellesmere_pt_defaults *defaults = data->power_tune_defaults; + struct polaris10_pt_defaults *defaults = data->power_tune_defaults; tdc_limit = (uint16_t)(table_info->cac_dtp_table->usTDC * 128); data->power_tune_table.TDC_VDDC_PkgLimit = @@ -132,13 +132,13 @@ static int ellesmere_populate_tdc_limit(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) +static int polaris10_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_offset) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); - struct ellesmere_pt_defaults *defaults = data->power_tune_defaults; + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); + struct polaris10_pt_defaults *defaults = data->power_tune_defaults; uint32_t temp; - if (ellesmere_read_smc_sram_dword(hwmgr->smumgr, + if (polaris10_read_smc_sram_dword(hwmgr->smumgr, fuse_table_offset + offsetof(SMU74_Discrete_PmFuses, TdcWaterfallCtl), (uint32_t *)&temp, data->sram_end)) @@ -156,10 +156,10 @@ static int ellesmere_populate_dw8(struct pp_hwmgr *hwmgr, uint32_t fuse_table_of return 0; } -static int ellesmere_populate_temperature_scaler(struct pp_hwmgr *hwmgr) +static int polaris10_populate_temperature_scaler(struct pp_hwmgr *hwmgr) { int i; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); /* Currently not used. Set all to zero. */ for (i = 0; i < 16; i++) @@ -168,9 +168,9 @@ static int ellesmere_populate_temperature_scaler(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) +static int polaris10_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); if ((hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity & (1 << 15)) || 0 == hwmgr->thermal_controller.advanceFanControlParameters.usFanOutputSensitivity) @@ -182,10 +182,10 @@ static int ellesmere_populate_fuzzy_fan(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_populate_gnb_lpml(struct pp_hwmgr *hwmgr) +static int polaris10_populate_gnb_lpml(struct pp_hwmgr *hwmgr) { int i; - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); /* Currently not used. Set all to zero. */ for (i = 0; i < 16; i++) @@ -194,14 +194,14 @@ static int ellesmere_populate_gnb_lpml(struct pp_hwmgr *hwmgr) return 0; } -static int ellesmere_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr) +static int polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(struct pp_hwmgr *hwmgr) { return 0; } -static int ellesmere_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) +static int polaris10_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); uint16_t hi_sidd = data->power_tune_table.BapmVddCBaseLeakageHiSidd; @@ -219,14 +219,14 @@ static int ellesmere_populate_bapm_vddc_base_leakage_sidd(struct pp_hwmgr *hwmgr return 0; } -int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr) +int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); uint32_t pm_fuse_table_offset; if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) { - if (ellesmere_read_smc_sram_dword(hwmgr->smumgr, + if (polaris10_read_smc_sram_dword(hwmgr->smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, PmFuseTable), &pm_fuse_table_offset, data->sram_end)) @@ -234,47 +234,47 @@ int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr) "Attempt to get pm_fuse_table_offset Failed!", return -EINVAL); - if (ellesmere_populate_svi_load_line(hwmgr)) + if (polaris10_populate_svi_load_line(hwmgr)) PP_ASSERT_WITH_CODE(false, "Attempt to populate SviLoadLine Failed!", return -EINVAL); - if (ellesmere_populate_tdc_limit(hwmgr)) + if (polaris10_populate_tdc_limit(hwmgr)) PP_ASSERT_WITH_CODE(false, "Attempt to populate TDCLimit Failed!", return -EINVAL); - if (ellesmere_populate_dw8(hwmgr, pm_fuse_table_offset)) + if (polaris10_populate_dw8(hwmgr, pm_fuse_table_offset)) PP_ASSERT_WITH_CODE(false, "Attempt to populate TdcWaterfallCtl, " "LPMLTemperature Min and Max Failed!", return -EINVAL); - if (0 != ellesmere_populate_temperature_scaler(hwmgr)) + if (0 != polaris10_populate_temperature_scaler(hwmgr)) PP_ASSERT_WITH_CODE(false, "Attempt to populate LPMLTemperatureScaler Failed!", return -EINVAL); - if (ellesmere_populate_fuzzy_fan(hwmgr)) + if (polaris10_populate_fuzzy_fan(hwmgr)) PP_ASSERT_WITH_CODE(false, "Attempt to populate Fuzzy Fan Control parameters Failed!", return -EINVAL); - if (ellesmere_populate_gnb_lpml(hwmgr)) + if (polaris10_populate_gnb_lpml(hwmgr)) PP_ASSERT_WITH_CODE(false, "Attempt to populate GnbLPML Failed!", return -EINVAL); - if (ellesmere_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr)) + if (polaris10_min_max_vgnb_lpml_id_from_bapm_vddc(hwmgr)) PP_ASSERT_WITH_CODE(false, "Attempt to populate GnbLPML Min and Max Vid Failed!", return -EINVAL); - if (ellesmere_populate_bapm_vddc_base_leakage_sidd(hwmgr)) + if (polaris10_populate_bapm_vddc_base_leakage_sidd(hwmgr)) PP_ASSERT_WITH_CODE(false, "Attempt to populate BapmVddCBaseLeakage Hi and Lo " "Sidd Failed!", return -EINVAL); - if (ellesmere_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, + if (polaris10_copy_bytes_to_smc(hwmgr->smumgr, pm_fuse_table_offset, (uint8_t *)&data->power_tune_table, sizeof(struct SMU74_Discrete_PmFuses), data->sram_end)) PP_ASSERT_WITH_CODE(false, @@ -284,9 +284,9 @@ int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr) return 0; } -int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr) +int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); int result = 0; if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, @@ -302,9 +302,9 @@ int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr) return result; } -int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) +int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); if (data->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) @@ -313,15 +313,15 @@ int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n) return 0; } -static int ellesmere_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp) +static int polaris10_set_overdriver_target_tdp(struct pp_hwmgr *pHwMgr, uint32_t target_tdp) { return smum_send_msg_to_smc_with_parameter(pHwMgr->smumgr, PPSMC_MSG_OverDriveSetTargetTdp, target_tdp); } -int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr) +int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); int smc_result; @@ -363,7 +363,7 @@ int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr) data->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; - if (ellesmere_set_power_limit(hwmgr, default_limit)) + if (polaris10_set_power_limit(hwmgr, default_limit)) printk(KERN_ERR "Failed to set Default Power Limit in SMC!"); } } @@ -371,7 +371,7 @@ int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr) return result; } -int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr) +int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr) { struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); @@ -389,7 +389,7 @@ int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr) * but message to be 8 bit fraction for messages */ target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100; - result = ellesmere_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp); + result = polaris10_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp); } return result; diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h index 5772bf929eaf..68bc1cb6d40c 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_powertune.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_powertune.h @@ -20,15 +20,15 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#ifndef ELLESMERE_POWERTUNE_H -#define ELLESMERE_POWERTUNE_H +#ifndef POLARIS10_POWERTUNE_H +#define POLARIS10_POWERTUNE_H -enum ellesmere_pt_config_reg_type { - ELLESMERE_CONFIGREG_MMR = 0, - ELLESMERE_CONFIGREG_SMC_IND, - ELLESMERE_CONFIGREG_DIDT_IND, - ELLESMERE_CONFIGREG_CACHE, - ELLESMERE_CONFIGREG_MAX +enum polaris10_pt_config_reg_type { + POLARIS10_CONFIGREG_MMR = 0, + POLARIS10_CONFIGREG_SMC_IND, + POLARIS10_CONFIGREG_DIDT_IND, + POLARIS10_CONFIGREG_CACHE, + POLARIS10_CONFIGREG_MAX }; /* PowerContainment Features */ @@ -36,15 +36,15 @@ enum ellesmere_pt_config_reg_type { #define POWERCONTAINMENT_FEATURE_TDCLimit 0x00000002 #define POWERCONTAINMENT_FEATURE_PkgPwrLimit 0x00000004 -struct ellesmere_pt_config_reg { +struct polaris10_pt_config_reg { uint32_t offset; uint32_t mask; uint32_t shift; uint32_t value; - enum ellesmere_pt_config_reg_type type; + enum polaris10_pt_config_reg_type type; }; -struct ellesmere_pt_defaults { +struct polaris10_pt_defaults { uint8_t SviLoadLineEn; uint8_t SviLoadLineVddC; uint8_t TDC_VDDC_ThrottleReleaseLimitPerc; @@ -58,13 +58,13 @@ struct ellesmere_pt_defaults { uint16_t BAPMTI_RC[SMU74_DTE_ITERATIONS * SMU74_DTE_SOURCES * SMU74_DTE_SINKS]; }; -void ellesmere_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr); -int ellesmere_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr); -int ellesmere_populate_pm_fuses(struct pp_hwmgr *hwmgr); -int ellesmere_enable_smc_cac(struct pp_hwmgr *hwmgr); -int ellesmere_enable_power_containment(struct pp_hwmgr *hwmgr); -int ellesmere_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); -int ellesmere_power_control_set_level(struct pp_hwmgr *hwmgr); +void polaris10_initialize_power_tune_defaults(struct pp_hwmgr *hwmgr); +int polaris10_populate_bapm_parameters_in_dpm_table(struct pp_hwmgr *hwmgr); +int polaris10_populate_pm_fuses(struct pp_hwmgr *hwmgr); +int polaris10_enable_smc_cac(struct pp_hwmgr *hwmgr); +int polaris10_enable_power_containment(struct pp_hwmgr *hwmgr); +int polaris10_set_power_limit(struct pp_hwmgr *hwmgr, uint32_t n); +int polaris10_power_control_set_level(struct pp_hwmgr *hwmgr); -#endif /* ELLESMERE_POWERTUNE_H */ +#endif /* POLARIS10_POWERTUNE_H */ diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c index 08be40069ad9..d2f553d61c3d 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.c @@ -21,14 +21,14 @@ * */ -#include "ellesmere_thermal.h" -#include "ellesmere_hwmgr.h" -#include "ellesmere_smumgr.h" -#include "ellesmere_ppsmc.h" +#include "polaris10_thermal.h" +#include "polaris10_hwmgr.h" +#include "polaris10_smumgr.h" +#include "polaris10_ppsmc.h" #include "smu/smu_7_1_3_d.h" #include "smu/smu_7_1_3_sh_mask.h" -int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, +int polaris10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info) { if (hwmgr->thermal_controller.fanInfo.bNoFan) @@ -54,7 +54,7 @@ int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, return 0; } -int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, +int polaris10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed) { uint32_t duty100; @@ -83,7 +83,7 @@ int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, return 0; } -int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) +int polaris10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed) { uint32_t tach_period; uint32_t crystal_clock_freq; @@ -112,7 +112,7 @@ int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed * mode the fan control mode, 0 default, 1 by percent, 5, by RPM * @exception Should always succeed. */ -int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) +int polaris10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) { if (hwmgr->fan_ctrl_is_in_default_mode) { @@ -138,7 +138,7 @@ int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode) * @param hwmgr the address of the powerplay hardware manager. * @exception Should always succeed. */ -int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) +int polaris10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) { if (!hwmgr->fan_ctrl_is_in_default_mode) { PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, @@ -151,7 +151,7 @@ int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr) return 0; } -int ellesmere_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) +int polaris10_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) { int result; @@ -186,7 +186,7 @@ int ellesmere_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) } -int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) +int polaris10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) { return smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StopFanControl); } @@ -197,7 +197,7 @@ int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr) * @param speed is the percentage value (0% - 100%) to be set. * @exception Fails is the 100% setting appears to be 0. */ -int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, +int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed) { uint32_t duty100; @@ -212,7 +212,7 @@ int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) - ellesmere_fan_ctrl_stop_smc_fan_control(hwmgr); + polaris10_fan_ctrl_stop_smc_fan_control(hwmgr); duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100); @@ -227,7 +227,7 @@ int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL0, FDO_STATIC_DUTY, duty); - return ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); + return polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); } /** @@ -235,7 +235,7 @@ int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, * @param hwmgr the address of the powerplay hardware manager. * @exception Always succeeds. */ -int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) +int polaris10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) { int result; @@ -244,11 +244,11 @@ int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) { - result = ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); + result = polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); if (!result) - result = ellesmere_fan_ctrl_start_smc_fan_control(hwmgr); + result = polaris10_fan_ctrl_start_smc_fan_control(hwmgr); } else - result = ellesmere_fan_ctrl_set_default_mode(hwmgr); + result = polaris10_fan_ctrl_set_default_mode(hwmgr); return result; } @@ -259,7 +259,7 @@ int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) * @param speed is the percentage value (min - max) to be set. * @exception Fails is the speed not lie between min and max. */ -int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) +int polaris10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) { uint32_t tach_period; uint32_t crystal_clock_freq; @@ -273,7 +273,7 @@ int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) - ellesmere_fan_ctrl_stop_smc_fan_control(hwmgr); + polaris10_fan_ctrl_stop_smc_fan_control(hwmgr); crystal_clock_freq = tonga_get_xclk(hwmgr); @@ -282,7 +282,7 @@ int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_TACH_STATUS, TACH_PERIOD, tach_period); - return ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); + return polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); } /** @@ -290,7 +290,7 @@ int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) * * @param hwmgr The address of the hardware manager. */ -int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr) +int polaris10_thermal_get_temperature(struct pp_hwmgr *hwmgr) { int temp; @@ -299,7 +299,7 @@ int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr) /* Bit 9 means the reading is lower than the lowest usable value. */ if (temp & 0x200) - temp = ELLESMERE_THERMAL_MAXIMUM_TEMP_READING; + temp = POLARIS10_THERMAL_MAXIMUM_TEMP_READING; else temp = temp & 0x1ff; @@ -315,12 +315,12 @@ int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr) * @param range Temperature range to be programmed for high and low alert signals * @exception PP_Result_BadInput if the input data is not valid. */ -static int ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, +static int polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, uint32_t low_temp, uint32_t high_temp) { - uint32_t low = ELLESMERE_THERMAL_MINIMUM_ALERT_TEMP * + uint32_t low = POLARIS10_THERMAL_MINIMUM_ALERT_TEMP * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; - uint32_t high = ELLESMERE_THERMAL_MAXIMUM_ALERT_TEMP * + uint32_t high = POLARIS10_THERMAL_MAXIMUM_ALERT_TEMP * PP_TEMPERATURE_UNITS_PER_CENTIGRADES; if (low < low_temp) @@ -349,7 +349,7 @@ static int ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, * * @param hwmgr The address of the hardware manager. */ -static int ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr) +static int polaris10_thermal_initialize(struct pp_hwmgr *hwmgr) { if (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, @@ -368,13 +368,13 @@ static int ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr) * * @param hwmgr The address of the hardware manager. */ -static int ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr) +static int polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr) { uint32_t alert; alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, THERM_INT_MASK); - alert &= ~(ELLESMERE_THERMAL_HIGH_ALERT_MASK | ELLESMERE_THERMAL_LOW_ALERT_MASK); + alert &= ~(POLARIS10_THERMAL_HIGH_ALERT_MASK | POLARIS10_THERMAL_LOW_ALERT_MASK); PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, THERM_INT_MASK, alert); @@ -386,13 +386,13 @@ static int ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr) * Disable thermal alerts on the RV770 thermal controller. * @param hwmgr The address of the hardware manager. */ -static int ellesmere_thermal_disable_alert(struct pp_hwmgr *hwmgr) +static int polaris10_thermal_disable_alert(struct pp_hwmgr *hwmgr) { uint32_t alert; alert = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, THERM_INT_MASK); - alert |= (ELLESMERE_THERMAL_HIGH_ALERT_MASK | ELLESMERE_THERMAL_LOW_ALERT_MASK); + alert |= (POLARIS10_THERMAL_HIGH_ALERT_MASK | POLARIS10_THERMAL_LOW_ALERT_MASK); PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_THERMAL_INT, THERM_INT_MASK, alert); @@ -405,12 +405,12 @@ static int ellesmere_thermal_disable_alert(struct pp_hwmgr *hwmgr) * Currently just disables alerts. * @param hwmgr The address of the hardware manager. */ -int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) +int polaris10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) { - int result = ellesmere_thermal_disable_alert(hwmgr); + int result = polaris10_thermal_disable_alert(hwmgr); if (!hwmgr->thermal_controller.fanInfo.bNoFan) - ellesmere_fan_ctrl_set_default_mode(hwmgr); + polaris10_fan_ctrl_set_default_mode(hwmgr); return result; } @@ -424,10 +424,10 @@ int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr) * @param Result the last failure code * @return result from set temperature range routine */ -int tf_ellesmere_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, +int tf_polaris10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) { - struct ellesmere_hwmgr *data = (struct ellesmere_hwmgr *)(hwmgr->backend); + struct polaris10_hwmgr *data = (struct polaris10_hwmgr *)(hwmgr->backend); SMU74_Discrete_FanTable fan_table = { FDO_MODE_HARDWARE }; uint32_t duty100; uint32_t t_diff1, t_diff2, pwm_diff1, pwm_diff2; @@ -502,7 +502,7 @@ int tf_ellesmere_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, hwmgr->device, CGS_IND_REG__SMC, CG_MULT_THERMAL_CTRL, TEMP_SEL); - res = ellesmere_copy_bytes_to_smc(hwmgr->smumgr, data->fan_table_start, + res = polaris10_copy_bytes_to_smc(hwmgr->smumgr, data->fan_table_start, (uint8_t *)&fan_table, (uint32_t)sizeof(fan_table), data->sram_end); @@ -536,7 +536,7 @@ int tf_ellesmere_thermal_setup_fan_table(struct pp_hwmgr *hwmgr, * @param Result the last failure code * @return result from set temperature range routine */ -int tf_ellesmere_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, +int tf_polaris10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) { /* If the fantable setup has failed we could have disabled @@ -546,8 +546,8 @@ int tf_ellesmere_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, */ if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) { - ellesmere_fan_ctrl_start_smc_fan_control(hwmgr); - ellesmere_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); + polaris10_fan_ctrl_start_smc_fan_control(hwmgr); + polaris10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC); } return 0; @@ -562,7 +562,7 @@ int tf_ellesmere_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, * @param Result the last failure code * @return result from set temperature range routine */ -int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, +int tf_polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) { struct PP_TemperatureRange *range = (struct PP_TemperatureRange *)input; @@ -570,7 +570,7 @@ int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, if (range == NULL) return -EINVAL; - return ellesmere_thermal_set_temperature_range(hwmgr, range->min, range->max); + return polaris10_thermal_set_temperature_range(hwmgr, range->min, range->max); } /** @@ -582,10 +582,10 @@ int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, * @param Result the last failure code * @return result from initialize thermal controller routine */ -int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr, +int tf_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) { - return ellesmere_thermal_initialize(hwmgr); + return polaris10_thermal_initialize(hwmgr); } /** @@ -597,10 +597,10 @@ int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr, * @param Result the last failure code * @return result from enable alert routine */ -int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr, +int tf_polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) { - return ellesmere_thermal_enable_alert(hwmgr); + return polaris10_thermal_enable_alert(hwmgr); } /** @@ -612,18 +612,18 @@ int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr, * @param Result the last failure code * @return result from disable alert routine */ -static int tf_ellesmere_thermal_disable_alert(struct pp_hwmgr *hwmgr, +static int tf_polaris10_thermal_disable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) { - return ellesmere_thermal_disable_alert(hwmgr); + return polaris10_thermal_disable_alert(hwmgr); } -static int tf_ellesmere_thermal_avfs_enable(struct pp_hwmgr *hwmgr, +static int tf_polaris10_thermal_avfs_enable(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) { int ret; struct pp_smumgr *smumgr = (struct pp_smumgr *)(hwmgr->smumgr); - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); if (smu_data->avfs.avfs_btc_status != AVFS_BTC_ENABLEAVFS) return 0; @@ -639,47 +639,47 @@ static int tf_ellesmere_thermal_avfs_enable(struct pp_hwmgr *hwmgr, } static struct phm_master_table_item -ellesmere_thermal_start_thermal_controller_master_list[] = { - {NULL, tf_ellesmere_thermal_initialize}, - {NULL, tf_ellesmere_thermal_set_temperature_range}, - {NULL, tf_ellesmere_thermal_enable_alert}, - {NULL, tf_ellesmere_thermal_avfs_enable}, +polaris10_thermal_start_thermal_controller_master_list[] = { + {NULL, tf_polaris10_thermal_initialize}, + {NULL, tf_polaris10_thermal_set_temperature_range}, + {NULL, tf_polaris10_thermal_enable_alert}, + {NULL, tf_polaris10_thermal_avfs_enable}, /* We should restrict performance levels to low before we halt the SMC. * On the other hand we are still in boot state when we do this * so it would be pointless. * If this assumption changes we have to revisit this table. */ - {NULL, tf_ellesmere_thermal_setup_fan_table}, - {NULL, tf_ellesmere_thermal_start_smc_fan_control}, + {NULL, tf_polaris10_thermal_setup_fan_table}, + {NULL, tf_polaris10_thermal_start_smc_fan_control}, {NULL, NULL} }; static struct phm_master_table_header -ellesmere_thermal_start_thermal_controller_master = { +polaris10_thermal_start_thermal_controller_master = { 0, PHM_MasterTableFlag_None, - ellesmere_thermal_start_thermal_controller_master_list + polaris10_thermal_start_thermal_controller_master_list }; static struct phm_master_table_item -ellesmere_thermal_set_temperature_range_master_list[] = { - {NULL, tf_ellesmere_thermal_disable_alert}, - {NULL, tf_ellesmere_thermal_set_temperature_range}, - {NULL, tf_ellesmere_thermal_enable_alert}, +polaris10_thermal_set_temperature_range_master_list[] = { + {NULL, tf_polaris10_thermal_disable_alert}, + {NULL, tf_polaris10_thermal_set_temperature_range}, + {NULL, tf_polaris10_thermal_enable_alert}, {NULL, NULL} }; struct phm_master_table_header -ellesmere_thermal_set_temperature_range_master = { +polaris10_thermal_set_temperature_range_master = { 0, PHM_MasterTableFlag_None, - ellesmere_thermal_set_temperature_range_master_list + polaris10_thermal_set_temperature_range_master_list }; -int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) +int polaris10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr) { if (!hwmgr->thermal_controller.fanInfo.bNoFan) - ellesmere_fan_ctrl_set_default_mode(hwmgr); + polaris10_fan_ctrl_set_default_mode(hwmgr); return 0; } @@ -688,17 +688,17 @@ int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmg * @param hwmgr The address of the hardware manager. * @exception Any error code from the low-level communication. */ -int pp_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr) +int pp_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr) { int result; result = phm_construct_table(hwmgr, - &ellesmere_thermal_set_temperature_range_master, + &polaris10_thermal_set_temperature_range_master, &(hwmgr->set_temperature_range)); if (!result) { result = phm_construct_table(hwmgr, - &ellesmere_thermal_start_thermal_controller_master, + &polaris10_thermal_start_thermal_controller_master, &(hwmgr->start_thermal_controller)); if (result) phm_destroy_table(hwmgr, &(hwmgr->set_temperature_range)); diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h index 4263e9bdf76d..62f8cbc2d590 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/ellesmere_thermal.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/polaris10_thermal.h @@ -21,41 +21,41 @@ * */ -#ifndef _ELLESMERE_THERMAL_H_ -#define _ELLESMERE_THERMAL_H_ +#ifndef _POLARIS10_THERMAL_H_ +#define _POLARIS10_THERMAL_H_ #include "hwmgr.h" -#define ELLESMERE_THERMAL_HIGH_ALERT_MASK 0x1 -#define ELLESMERE_THERMAL_LOW_ALERT_MASK 0x2 +#define POLARIS10_THERMAL_HIGH_ALERT_MASK 0x1 +#define POLARIS10_THERMAL_LOW_ALERT_MASK 0x2 -#define ELLESMERE_THERMAL_MINIMUM_TEMP_READING -256 -#define ELLESMERE_THERMAL_MAXIMUM_TEMP_READING 255 +#define POLARIS10_THERMAL_MINIMUM_TEMP_READING -256 +#define POLARIS10_THERMAL_MAXIMUM_TEMP_READING 255 -#define ELLESMERE_THERMAL_MINIMUM_ALERT_TEMP 0 -#define ELLESMERE_THERMAL_MAXIMUM_ALERT_TEMP 255 +#define POLARIS10_THERMAL_MINIMUM_ALERT_TEMP 0 +#define POLARIS10_THERMAL_MAXIMUM_ALERT_TEMP 255 #define FDO_PWM_MODE_STATIC 1 #define FDO_PWM_MODE_STATIC_RPM 5 -extern int tf_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); -extern int tf_ellesmere_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); -extern int tf_ellesmere_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); - -extern int ellesmere_thermal_get_temperature(struct pp_hwmgr *hwmgr); -extern int ellesmere_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr); -extern int ellesmere_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); -extern int ellesmere_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed); -extern int ellesmere_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr); -extern int ellesmere_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode); -extern int ellesmere_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed); -extern int ellesmere_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr); -extern int pp_ellesmere_thermal_initialize(struct pp_hwmgr *hwmgr); -extern int ellesmere_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr); -extern int ellesmere_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed); -extern int ellesmere_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed); -extern int ellesmere_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr); +extern int tf_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); +extern int tf_polaris10_thermal_set_temperature_range(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); +extern int tf_polaris10_thermal_enable_alert(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result); + +extern int polaris10_thermal_get_temperature(struct pp_hwmgr *hwmgr); +extern int polaris10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr); +extern int polaris10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info); +extern int polaris10_fan_ctrl_get_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t *speed); +extern int polaris10_fan_ctrl_set_default_mode(struct pp_hwmgr *hwmgr); +extern int polaris10_fan_ctrl_set_static_mode(struct pp_hwmgr *hwmgr, uint32_t mode); +extern int polaris10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed); +extern int polaris10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr); +extern int pp_polaris10_thermal_initialize(struct pp_hwmgr *hwmgr); +extern int polaris10_thermal_ctrl_uninitialize_thermal_controller(struct pp_hwmgr *hwmgr); +extern int polaris10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed); +extern int polaris10_fan_ctrl_get_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t *speed); +extern int polaris10_fan_ctrl_stop_smc_fan_control(struct pp_hwmgr *hwmgr); extern uint32_t tonga_get_xclk(struct pp_hwmgr *hwmgr); #endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h index a2c87ae20fb0..1b44f4e9b8f5 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_pptable.h @@ -209,18 +209,18 @@ typedef struct _ATOM_Tonga_PCIE_Table { ATOM_Tonga_PCIE_Record entries[1]; /* Dynamically allocate entries. */ } ATOM_Tonga_PCIE_Table; -typedef struct _ATOM_Ellesmere_PCIE_Record { +typedef struct _ATOM_Polaris10_PCIE_Record { UCHAR ucPCIEGenSpeed; UCHAR usPCIELaneWidth; UCHAR ucReserved[2]; ULONG ulPCIE_Sclk; -} ATOM_Ellesmere_PCIE_Record; +} ATOM_Polaris10_PCIE_Record; -typedef struct _ATOM_Ellesmere_PCIE_Table { +typedef struct _ATOM_Polaris10_PCIE_Table { UCHAR ucRevId; UCHAR ucNumEntries; /* Number of entries. */ - ATOM_Ellesmere_PCIE_Record entries[1]; /* Dynamically allocate entries. */ -} ATOM_Ellesmere_PCIE_Table; + ATOM_Polaris10_PCIE_Record entries[1]; /* Dynamically allocate entries. */ +} ATOM_Polaris10_PCIE_Table; typedef struct _ATOM_Tonga_MM_Dependency_Record { diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c index ecbc43f170bf..96a27876a704 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/tonga_processpptables.c @@ -493,8 +493,8 @@ static int get_pcie_table( *pp_tonga_pcie_table = pcie_table; } else { - /* Ellesmere/Baffin and newer. */ - const ATOM_Ellesmere_PCIE_Table *atom_pcie_table = (ATOM_Ellesmere_PCIE_Table *)pTable; + /* Polaris10/Polaris11 and newer. */ + const ATOM_Polaris10_PCIE_Table *atom_pcie_table = (ATOM_Polaris10_PCIE_Table *)pTable; PP_ASSERT_WITH_CODE((atom_pcie_table->ucNumEntries != 0), "Invalid PowerPlay Table!", return -1); diff --git a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h index 18fe2300adb1..0c6a413eaa5b 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_ppsmc.h +++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_ppsmc.h @@ -21,8 +21,8 @@ * */ -#ifndef ELLESMERE_PP_SMC_H -#define ELLESMERE_PP_SMC_H +#ifndef POLARIS10_PP_SMC_H +#define POLARIS10_PP_SMC_H #pragma pack(push, 1) @@ -386,8 +386,16 @@ typedef uint16_t PPSMC_Result; #define PPSMC_MSG_GFX_CU_PG_ENABLE ((uint16_t) 0x280) #define PPSMC_MSG_GFX_CU_PG_DISABLE ((uint16_t) 0x281) +#define PPSMC_MSG_GetCurrPkgPwr ((uint16_t) 0x282) #define PPSMC_MSG_SetGpuPllDfsForSclk ((uint16_t) 0x300) +#define PPSMC_MSG_Didt_Block_Function ((uint16_t) 0x301) + +#define PPSMC_MSG_SecureSRBMWrite ((uint16_t) 0x600) +#define PPSMC_MSG_SecureSRBMRead ((uint16_t) 0x601) +#define PPSMC_MSG_SetAddress ((uint16_t) 0x800) +#define PPSMC_MSG_GetData ((uint16_t) 0x801) +#define PPSMC_MSG_SetData ((uint16_t) 0x802) typedef uint16_t PPSMC_Msg; diff --git a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h index 997811cde61b..933103e6ad08 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/ellesmere_pwrvirus.h +++ b/drivers/gpu/drm/amd/powerplay/inc/polaris10_pwrvirus.h @@ -20,8 +20,8 @@ * OTHER DEALINGS IN THE SOFTWARE. * */ -#ifndef _ELLESMERE_PWRVIRUS_H -#define _ELLESMERE_PWRVIRUS_H +#ifndef _POLARIS10_PWRVIRUS_H +#define _POLARIS10_PWRVIRUS_H #define mmSMC_IND_INDEX_11 0x01AC #define mmSMC_IND_DATA_11 0x01AD diff --git a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h index f81626257a37..f6a7591274ba 100644 --- a/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h +++ b/drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h @@ -705,6 +705,7 @@ struct SMU7_Discrete_Pm_Status_Table { uint16_t Sclk_dpm_residency[8]; uint16_t Uvd_dpm_residency[8]; uint16_t Vce_dpm_residency[8]; + uint16_t Mclk_dpm_residency[4]; uint32_t P_vddci_acc; uint32_t P_vddr1_acc; @@ -779,6 +780,47 @@ typedef struct SMU7_GfxCuPgScoreboard SMU7_GfxCuPgScoreboard; #define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1 #define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2 +// DIDT Defines +#define SQ_Enable_MASK 0x1 +#define SQ_IR_MASK 0x2 +#define SQ_PCC_MASK 0x4 +#define SQ_EDC_MASK 0x8 + +#define TCP_Enable_MASK 0x100 +#define TCP_IR_MASK 0x200 +#define TCP_PCC_MASK 0x400 +#define TCP_EDC_MASK 0x800 + +#define TD_Enable_MASK 0x10000 +#define TD_IR_MASK 0x20000 +#define TD_PCC_MASK 0x40000 +#define TD_EDC_MASK 0x80000 + +#define DB_Enable_MASK 0x1000000 +#define DB_IR_MASK 0x2000000 +#define DB_PCC_MASK 0x4000000 +#define DB_EDC_MASK 0x8000000 + +#define SQ_Enable_SHIFT 0 +#define SQ_IR_SHIFT 1 +#define SQ_PCC_SHIFT 2 +#define SQ_EDC_SHIFT 3 + +#define TCP_Enable_SHIFT 8 +#define TCP_IR_SHIFT 9 +#define TCP_PCC_SHIFT 10 +#define TCP_EDC_SHIFT 11 + +#define TD_Enable_SHIFT 16 +#define TD_IR_SHIFT 17 +#define TD_PCC_SHIFT 18 +#define TD_EDC_SHIFT 19 + +#define DB_Enable_SHIFT 24 +#define DB_IR_SHIFT 25 +#define DB_PCC_SHIFT 26 +#define DB_EDC_SHIFT 27 + #pragma pack(pop) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile index 4f751e5fe5ae..f10fb64ef981 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/smumgr/Makefile @@ -2,7 +2,7 @@ # Makefile for the 'smu manager' sub-component of powerplay. # It provides the smu management services for the driver. -SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o ellesmere_smumgr.o +SMU_MGR = smumgr.o cz_smumgr.o tonga_smumgr.o fiji_smumgr.o polaris10_smumgr.o AMD_PP_SMUMGR = $(addprefix $(AMD_PP_PATH)/smumgr/,$(SMU_MGR)) diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c index 6395065a6e19..667e055edd01 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c @@ -24,7 +24,7 @@ #include "smumgr.h" #include "smu74.h" #include "smu_ucode_xfer_vi.h" -#include "ellesmere_smumgr.h" +#include "polaris10_smumgr.h" #include "smu74_discrete.h" #include "smu/smu_7_1_3_d.h" #include "smu/smu_7_1_3_sh_mask.h" @@ -34,12 +34,12 @@ #include "gca/gfx_8_0_d.h" #include "bif/bif_5_0_d.h" #include "bif/bif_5_0_sh_mask.h" -#include "ellesmere_pwrvirus.h" +#include "polaris10_pwrvirus.h" #include "ppatomctrl.h" #include "pp_debug.h" #include "cgs_common.h" -#define ELLESMERE_SMC_SIZE 0x20000 +#define POLARIS10_SMC_SIZE 0x20000 #define VOLTAGE_SCALE 4 /* Microcode file is stored in this buffer */ @@ -49,7 +49,7 @@ #define SMC_RAM_END 0x40000 -SMU74_Discrete_GraphicsLevel avfs_graphics_level_ellesmere[8] = { +SMU74_Discrete_GraphicsLevel avfs_graphics_level_polaris10[8] = { /* Min pcie DeepSleep Activity CgSpll CgSpll CcPwr CcPwr Sclk Enabled Enabled Voltage Power */ /* Voltage, DpmLevel, DivId, Level, FuncCntl3, FuncCntl4, DynRm, DynRm1 Did, Padding,ForActivity, ForThrottle, UpHyst, DownHyst, DownHyst, Throttle */ { 0x3c0fd047, 0x00, 0x03, 0x1e00, 0x00200410, 0x87020000, 0, 0, 0x16, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x30750000, 0, 0, 0, 0, 0, 0, 0 } }, @@ -62,7 +62,7 @@ SMU74_Discrete_GraphicsLevel avfs_graphics_level_ellesmere[8] = { { 0xf811d047, 0x01, 0x00, 0x1e00, 0x00000610, 0x87020000, 0, 0, 0x0c, 0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, { 0x80380100, 0, 0, 0, 0, 0, 0, 0 } } }; -SMU74_Discrete_MemoryLevel avfs_memory_level_ellesmere = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00, +SMU74_Discrete_MemoryLevel avfs_memory_level_polaris10 = {0x50140000, 0x50140000, 0x00320000, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x0000, 0x00, 0x00}; /** @@ -70,7 +70,7 @@ SMU74_Discrete_MemoryLevel avfs_memory_level_ellesmere = {0x50140000, 0x50140000 * @param smumgr the address of the powerplay hardware manager. * @param smcAddress the address in the SMC RAM to access. */ -static int ellesmere_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit) +static int polaris10_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t limit) { PP_ASSERT_WITH_CODE((0 == (3 & smc_addr)), "SMC address must be 4 byte aligned.", return -EINVAL); PP_ASSERT_WITH_CODE((limit > (smc_addr + 3)), "SMC addr is beyond the SMC RAM area.", return -EINVAL); @@ -89,7 +89,7 @@ static int ellesmere_set_smc_sram_address(struct pp_smumgr *smumgr, uint32_t smc * @param src the byte array to copy the bytes to. * @param byte_count the number of bytes to copy. */ -int ellesmere_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit) +int polaris10_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, uint32_t *dest, uint32_t byte_count, uint32_t limit) { uint32_t data; uint32_t addr; @@ -103,7 +103,7 @@ int ellesmere_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_a addr = smc_start_address; while (byte_count >= 4) { - ellesmere_read_smc_sram_dword(smumgr, addr, &data, limit); + polaris10_read_smc_sram_dword(smumgr, addr, &data, limit); *dest = PP_SMC_TO_HOST_UL(data); @@ -113,7 +113,7 @@ int ellesmere_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_a } if (byte_count) { - ellesmere_read_smc_sram_dword(smumgr, addr, &data, limit); + polaris10_read_smc_sram_dword(smumgr, addr, &data, limit); *pdata = PP_SMC_TO_HOST_UL(data); /* Cast dest into byte type in dest_byte. This way, we don't overflow if the allocated memory is not 4-byte aligned. */ dest_byte = (uint8_t *)dest; @@ -132,7 +132,7 @@ int ellesmere_copy_bytes_from_smc(struct pp_smumgr *smumgr, uint32_t smc_start_a * @param src the byte array to copy the bytes from. * @param byte_count the number of bytes to copy. */ -int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, +int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, const uint8_t *src, uint32_t byte_count, uint32_t limit) { int result; @@ -150,7 +150,7 @@ int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add /* Bytes are written into the SMC addres space with the MSB first. */ data = src[0] * 0x1000000 + src[1] * 0x10000 + src[2] * 0x100 + src[3]; - result = ellesmere_set_smc_sram_address(smumgr, addr, limit); + result = polaris10_set_smc_sram_address(smumgr, addr, limit); if (0 != result) return result; @@ -166,7 +166,7 @@ int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add data = 0; - result = ellesmere_set_smc_sram_address(smumgr, addr, limit); + result = polaris10_set_smc_sram_address(smumgr, addr, limit); if (0 != result) return result; @@ -186,7 +186,7 @@ int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add data |= (original_data & ~((~0UL) << extra_shift)); - result = ellesmere_set_smc_sram_address(smumgr, addr, limit); + result = polaris10_set_smc_sram_address(smumgr, addr, limit); if (0 != result) return result; @@ -198,11 +198,11 @@ int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_add } -static int ellesmere_program_jump_on_start(struct pp_smumgr *smumgr) +static int polaris10_program_jump_on_start(struct pp_smumgr *smumgr) { static unsigned char data[4] = { 0xE0, 0x00, 0x80, 0x40 }; - ellesmere_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1); + polaris10_copy_bytes_to_smc(smumgr, 0x0, data, 4, sizeof(data)+1); return 0; } @@ -212,7 +212,7 @@ static int ellesmere_program_jump_on_start(struct pp_smumgr *smumgr) * * @param smumgr the address of the powerplay hardware manager. */ -bool ellesmere_is_smc_ram_running(struct pp_smumgr *smumgr) +bool polaris10_is_smc_ram_running(struct pp_smumgr *smumgr) { return ((0 == SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable)) && (0x20100 <= cgs_read_ind_register(smumgr->device, CGS_IND_REG__SMC, ixSMC_PC_C))); @@ -225,9 +225,9 @@ bool ellesmere_is_smc_ram_running(struct pp_smumgr *smumgr) * @param msg the message to send. * @return The response that came from the SMC. */ -int ellesmere_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) +int polaris10_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) { - if (!ellesmere_is_smc_ram_running(smumgr)) + if (!polaris10_is_smc_ram_running(smumgr)) return -1; SMUM_WAIT_FIELD_UNEQUAL(smumgr, SMC_RESP_0, SMC_RESP, 0); @@ -254,7 +254,7 @@ int ellesmere_send_msg_to_smc(struct pp_smumgr *smumgr, uint16_t msg) * @param msg the message to send. * @return Always return 0. */ -int ellesmere_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg) +int polaris10_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t msg) { cgs_write_register(smumgr->device, mmSMC_MESSAGE_0, msg); @@ -269,9 +269,9 @@ int ellesmere_send_msg_to_smc_without_waiting(struct pp_smumgr *smumgr, uint16_t * @param parameter: the parameter to send * @return The response that came from the SMC. */ -int ellesmere_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) +int polaris10_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) { - if (!ellesmere_is_smc_ram_running(smumgr)) { + if (!polaris10_is_smc_ram_running(smumgr)) { return -1; } @@ -279,7 +279,7 @@ int ellesmere_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); - return ellesmere_send_msg_to_smc(smumgr, msg); + return polaris10_send_msg_to_smc(smumgr, msg); } @@ -291,14 +291,14 @@ int ellesmere_send_msg_to_smc_with_parameter(struct pp_smumgr *smumgr, uint16_t * @param parameter: the parameter to send * @return The response that came from the SMC. */ -int ellesmere_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) +int polaris10_send_msg_to_smc_with_parameter_without_waiting(struct pp_smumgr *smumgr, uint16_t msg, uint32_t parameter) { cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, parameter); - return ellesmere_send_msg_to_smc_without_waiting(smumgr, msg); + return polaris10_send_msg_to_smc_without_waiting(smumgr, msg); } -int ellesmere_send_msg_to_smc_offset(struct pp_smumgr *smumgr) +int polaris10_send_msg_to_smc_offset(struct pp_smumgr *smumgr) { cgs_write_register(smumgr->device, mmSMC_MSG_ARG_0, 0x20000); @@ -319,10 +319,10 @@ int ellesmere_send_msg_to_smc_offset(struct pp_smumgr *smumgr) * @param msg the message to send. * @return The response that came from the SMC. */ -int ellesmere_wait_for_smc_inactive(struct pp_smumgr *smumgr) +int polaris10_wait_for_smc_inactive(struct pp_smumgr *smumgr) { /* If the SMC is not even on it qualifies as inactive. */ - if (!ellesmere_is_smc_ram_running(smumgr)) + if (!polaris10_is_smc_ram_running(smumgr)) return -1; SMUM_WAIT_VFPF_INDIRECT_FIELD(smumgr, SMC_IND, SMC_SYSCON_CLOCK_CNTL_0, cken, 0); @@ -336,7 +336,7 @@ int ellesmere_wait_for_smc_inactive(struct pp_smumgr *smumgr) * @param smumgr the address of the powerplay hardware manager. * @param pFirmware the data structure containing the various sections of the firmware. */ -static int ellesmere_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit) +static int polaris10_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t length, uint32_t *src, uint32_t limit) { uint32_t byte_count = length; @@ -355,7 +355,7 @@ static int ellesmere_upload_smc_firmware_data(struct pp_smumgr *smumgr, uint32_t return 0; } -static enum cgs_ucode_id ellesmere_convert_fw_type_to_cgs(uint32_t fw_type) +static enum cgs_ucode_id polaris10_convert_fw_type_to_cgs(uint32_t fw_type) { enum cgs_ucode_id result = CGS_UCODE_ID_MAXIMUM; @@ -400,22 +400,22 @@ static enum cgs_ucode_id ellesmere_convert_fw_type_to_cgs(uint32_t fw_type) return result; } -static int ellesmere_upload_smu_firmware_image(struct pp_smumgr *smumgr) +static int polaris10_upload_smu_firmware_image(struct pp_smumgr *smumgr) { int result = 0; - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); struct cgs_firmware_info info = {0}; if (smu_data->security_hard_key == 1) cgs_get_firmware_info(smumgr->device, - ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); + polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU), &info); else cgs_get_firmware_info(smumgr->device, - ellesmere_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info); + polaris10_convert_fw_type_to_cgs(UCODE_ID_SMU_SK), &info); /* TO DO cgs_init_samu_load_smu(smumgr->device, (uint32_t *)info.kptr, info.image_size, smu_data->post_initial_boot);*/ - result = ellesmere_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, ELLESMERE_SMC_SIZE); + result = polaris10_upload_smc_firmware_data(smumgr, info.image_size, (uint32_t *)info.kptr, POLARIS10_SMC_SIZE); return result; } @@ -427,11 +427,11 @@ static int ellesmere_upload_smu_firmware_image(struct pp_smumgr *smumgr) * @param smcAddress the address in the SMC RAM to access. * @param value and output parameter for the data read from the SMC SRAM. */ -int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit) +int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit) { int result; - result = ellesmere_set_smc_sram_address(smumgr, smc_addr, limit); + result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit); if (result) return result; @@ -447,11 +447,11 @@ int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, u * @param smc_addr the address in the SMC RAM to access. * @param value to write to the SMC SRAM. */ -int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit) +int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit) { int result; - result = ellesmere_set_smc_sram_address(smumgr, smc_addr, limit); + result = polaris10_set_smc_sram_address(smumgr, smc_addr, limit); if (result) return result; @@ -462,7 +462,7 @@ int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, } -int ellesmere_smu_fini(struct pp_smumgr *smumgr) +int polaris10_smu_fini(struct pp_smumgr *smumgr) { if (smumgr->backend) { kfree(smumgr->backend); @@ -472,7 +472,7 @@ int ellesmere_smu_fini(struct pp_smumgr *smumgr) } /* Convert the firmware type to SMU type mask. For MEC, we need to check all MEC related type */ -static uint32_t ellesmere_get_mask_for_firmware_type(uint32_t fw_type) +static uint32_t polaris10_get_mask_for_firmware_type(uint32_t fw_type) { uint32_t result = 0; @@ -509,7 +509,7 @@ static uint32_t ellesmere_get_mask_for_firmware_type(uint32_t fw_type) /* Populate one firmware image to the data structure */ -static int ellesmere_populate_single_firmware_entry(struct pp_smumgr *smumgr, +static int polaris10_populate_single_firmware_entry(struct pp_smumgr *smumgr, uint32_t fw_type, struct SMU_Entry *entry) { @@ -517,7 +517,7 @@ static int ellesmere_populate_single_firmware_entry(struct pp_smumgr *smumgr, struct cgs_firmware_info info = {0}; result = cgs_get_firmware_info(smumgr->device, - ellesmere_convert_fw_type_to_cgs(fw_type), + polaris10_convert_fw_type_to_cgs(fw_type), &info); if (!result) { @@ -539,9 +539,9 @@ static int ellesmere_populate_single_firmware_entry(struct pp_smumgr *smumgr, return 0; } -static int ellesmere_request_smu_load_fw(struct pp_smumgr *smumgr) +static int polaris10_request_smu_load_fw(struct pp_smumgr *smumgr) { - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); uint32_t fw_to_load; int result = 0; @@ -557,25 +557,25 @@ static int ellesmere_request_smu_load_fw(struct pp_smumgr *smumgr) smu_data->soft_regs_start + offsetof(SMU74_SoftRegisters, UcodeLoadStatus), 0x0); - ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high); - ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low); + polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_HI, smu_data->smu_buffer.mc_addr_high); + polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_SMU_DRAM_ADDR_LO, smu_data->smu_buffer.mc_addr_low); toc = (struct SMU_DRAMData_TOC *)smu_data->header; toc->num_entries = 0; toc->structure_version = 1; - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - PP_ASSERT_WITH_CODE(0 == ellesmere_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_RLC_G, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_CE, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_PFP, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_ME, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_CP_MEC_JT2, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA0, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); + PP_ASSERT_WITH_CODE(0 == polaris10_populate_single_firmware_entry(smumgr, UCODE_ID_SDMA1, &toc->entry[toc->num_entries++]), "Failed to Get Firmware Entry.", return -1); - ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high); - ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low); + polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_HI, smu_data->header_buffer.mc_addr_high); + polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_DRV_DRAM_ADDR_LO, smu_data->header_buffer.mc_addr_low); fw_to_load = UCODE_ID_RLC_G_MASK + UCODE_ID_SDMA0_MASK @@ -585,17 +585,17 @@ static int ellesmere_request_smu_load_fw(struct pp_smumgr *smumgr) + UCODE_ID_CP_PFP_MASK + UCODE_ID_CP_MEC_MASK; - if (ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load)) + if (polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_LoadUcodes, fw_to_load)) printk(KERN_ERR "Fail to Request SMU Load uCode"); return result; } /* Check if the FW has been loaded, SMU will not return if loading has not finished. */ -static int ellesmere_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type) +static int polaris10_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_type) { - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); - uint32_t fw_mask = ellesmere_get_mask_for_firmware_type(fw_type); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); + uint32_t fw_mask = polaris10_get_mask_for_firmware_type(fw_type); uint32_t ret; /* Check SOFT_REGISTERS_TABLE_28.UcodeLoadStatus */ ret = smum_wait_on_indirect_register(smumgr, mmSMC_IND_INDEX_11, @@ -605,19 +605,19 @@ static int ellesmere_check_fw_load_finish(struct pp_smumgr *smumgr, uint32_t fw_ return ret; } -static int ellesmere_reload_firmware(struct pp_smumgr *smumgr) +static int polaris10_reload_firmware(struct pp_smumgr *smumgr) { return smumgr->smumgr_funcs->start_smu(smumgr); } -static int ellesmere_setup_pwr_virus(struct pp_smumgr *smumgr) +static int polaris10_setup_pwr_virus(struct pp_smumgr *smumgr) { int i; int result = -1; uint32_t reg, data; PWR_Command_Table *pvirus = pwr_virus_table; - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); for (i = 0; i < PWR_VIRUS_TABLE_SIZE; i++) { @@ -644,14 +644,14 @@ static int ellesmere_setup_pwr_virus(struct pp_smumgr *smumgr) return result; } -static int ellesmere_perform_btc(struct pp_smumgr *smumgr) +static int polaris10_perform_btc(struct pp_smumgr *smumgr) { int result = 0; - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); if (0 != smu_data->avfs.avfs_btc_param) { - if (0 != ellesmere_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { - printk("[AVFS][SmuEllesmere_PerformBtc] PerformBTC SMU msg failed"); + if (0 != polaris10_send_msg_to_smc_with_parameter(smumgr, PPSMC_MSG_PerformBtc, smu_data->avfs.avfs_btc_param)) { + printk("[AVFS][SmuPolaris10_PerformBtc] PerformBTC SMU msg failed"); result = -1; } } @@ -667,7 +667,7 @@ static int ellesmere_perform_btc(struct pp_smumgr *smumgr) } -int ellesmere_setup_graphics_level_structure(struct pp_smumgr *smumgr) +int polaris10_setup_graphics_level_structure(struct pp_smumgr *smumgr) { uint32_t vr_config; uint32_t dpm_table_start; @@ -675,13 +675,13 @@ int ellesmere_setup_graphics_level_structure(struct pp_smumgr *smumgr) uint16_t u16_boot_mvdd; uint32_t graphics_level_address, vr_config_address, graphics_level_size; - graphics_level_size = sizeof(avfs_graphics_level_ellesmere); + graphics_level_size = sizeof(avfs_graphics_level_polaris10); u16_boot_mvdd = PP_HOST_TO_SMC_US(1300 * VOLTAGE_SCALE); - PP_ASSERT_WITH_CODE(0 == ellesmere_read_smc_sram_dword(smumgr, + PP_ASSERT_WITH_CODE(0 == polaris10_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, DpmTable), &dpm_table_start, 0x40000), - "[AVFS][Ellesmere_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table", + "[AVFS][Polaris10_SetupGfxLvlStruct] SMU could not communicate starting address of DPM table", return -1); /* Default value for VRConfig = VR_MERGED_WITH_VDDC + VR_STATIC_VOLTAGE(VDDCI) */ @@ -689,41 +689,41 @@ int ellesmere_setup_graphics_level_structure(struct pp_smumgr *smumgr) vr_config_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, VRConfig); - PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, vr_config_address, + PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, vr_config_address, (uint8_t *)&vr_config, sizeof(uint32_t), 0x40000), - "[AVFS][Ellesmere_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC", + "[AVFS][Polaris10_SetupGfxLvlStruct] Problems copying VRConfig value over to SMC", return -1); graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, GraphicsLevel); - PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address, - (uint8_t *)(&avfs_graphics_level_ellesmere), + PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address, + (uint8_t *)(&avfs_graphics_level_polaris10), graphics_level_size, 0x40000), - "[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of SCLK DPM table failed!", + "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of SCLK DPM table failed!", return -1); graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, MemoryLevel); - PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address, - (uint8_t *)(&avfs_memory_level_ellesmere), sizeof(avfs_memory_level_ellesmere), 0x40000), - "[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of MCLK DPM table failed!", + PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address, + (uint8_t *)(&avfs_memory_level_polaris10), sizeof(avfs_memory_level_polaris10), 0x40000), + "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of MCLK DPM table failed!", return -1); /* MVDD Boot value - neccessary for getting rid of the hang that occurs during Mclk DPM enablement */ graphics_level_address = dpm_table_start + offsetof(SMU74_Discrete_DpmTable, BootMVdd); - PP_ASSERT_WITH_CODE(0 == ellesmere_copy_bytes_to_smc(smumgr, graphics_level_address, + PP_ASSERT_WITH_CODE(0 == polaris10_copy_bytes_to_smc(smumgr, graphics_level_address, (uint8_t *)(&u16_boot_mvdd), sizeof(u16_boot_mvdd), 0x40000), - "[AVFS][Ellesmere_SetupGfxLvlStruct] Copying of DPM table failed!", + "[AVFS][Polaris10_SetupGfxLvlStruct] Copying of DPM table failed!", return -1); return 0; } -int ellesmere_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) +int polaris10_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) { - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); switch (smu_data->avfs.avfs_btc_status) { case AVFS_BTC_COMPLETED_PREVIOUSLY: @@ -732,21 +732,21 @@ int ellesmere_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) case AVFS_BTC_BOOT: /* Cold Boot State - Post SMU Start */ smu_data->avfs.avfs_btc_status = AVFS_BTC_DPMTABLESETUP_FAILED; - PP_ASSERT_WITH_CODE(0 == ellesmere_setup_graphics_level_structure(smumgr), - "[AVFS][Ellesmere_AVFSEventMgr] Could not Copy Graphics Level table over to SMU", + PP_ASSERT_WITH_CODE(0 == polaris10_setup_graphics_level_structure(smumgr), + "[AVFS][Polaris10_AVFSEventMgr] Could not Copy Graphics Level table over to SMU", return -1); if (smu_data->avfs.avfs_btc_param > 1) { - printk("[AVFS][Ellesmere_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting."); + printk("[AVFS][Polaris10_AVFSEventMgr] AC BTC has not been successfully verified on Fiji. There may be in this setting."); smu_data->avfs.avfs_btc_status = AVFS_BTC_VIRUS_FAIL; - PP_ASSERT_WITH_CODE(-1 == ellesmere_setup_pwr_virus(smumgr), - "[AVFS][Ellesmere_AVFSEventMgr] Could not setup Pwr Virus for AVFS ", + PP_ASSERT_WITH_CODE(-1 == polaris10_setup_pwr_virus(smumgr), + "[AVFS][Polaris10_AVFSEventMgr] Could not setup Pwr Virus for AVFS ", return -1); } smu_data->avfs.avfs_btc_status = AVFS_BTC_FAILED; - PP_ASSERT_WITH_CODE(0 == ellesmere_perform_btc(smumgr), - "[AVFS][Ellesmere_AVFSEventMgr] Failure at SmuEllesmere_PerformBTC. AVFS Disabled", + PP_ASSERT_WITH_CODE(0 == polaris10_perform_btc(smumgr), + "[AVFS][Polaris10_AVFSEventMgr] Failure at SmuPolaris10_PerformBTC. AVFS Disabled", return -1); break; @@ -763,7 +763,7 @@ int ellesmere_avfs_event_mgr(struct pp_smumgr *smumgr, bool SMU_VFT_INTACT) return 0; } -static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr) +static int polaris10_start_smu_in_protection_mode(struct pp_smumgr *smumgr) { int result = 0; @@ -774,7 +774,7 @@ static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr) SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_RESET_CNTL, rst_reg, 1); - result = ellesmere_upload_smu_firmware_image(smumgr); + result = polaris10_upload_smu_firmware_image(smumgr); if (result != 0) return result; @@ -793,7 +793,7 @@ static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr) /* Call Test SMU message with 0x20000 offset to trigger SMU start */ - ellesmere_send_msg_to_smc_offset(smumgr); + polaris10_send_msg_to_smc_offset(smumgr); /* Wait done bit to be set */ /* Check pass/failed indicator */ @@ -818,7 +818,7 @@ static int ellesmere_start_smu_in_protection_mode(struct pp_smumgr *smumgr) return result; } -static int ellesmere_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) +static int polaris10_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) { int result = 0; @@ -834,12 +834,12 @@ static int ellesmere_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) SMC_SYSCON_RESET_CNTL, rst_reg, 1); - result = ellesmere_upload_smu_firmware_image(smumgr); + result = polaris10_upload_smu_firmware_image(smumgr); if (result != 0) return result; /* Set smc instruct start point at 0x0 */ - ellesmere_program_jump_on_start(smumgr); + polaris10_program_jump_on_start(smumgr); SMUM_WRITE_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable, 0); @@ -855,56 +855,56 @@ static int ellesmere_start_smu_in_non_protection_mode(struct pp_smumgr *smumgr) return result; } -static int ellesmere_start_smu(struct pp_smumgr *smumgr) +static int polaris10_start_smu(struct pp_smumgr *smumgr) { int result = 0; - struct ellesmere_smumgr *smu_data = (struct ellesmere_smumgr *)(smumgr->backend); + struct polaris10_smumgr *smu_data = (struct polaris10_smumgr *)(smumgr->backend); bool SMU_VFT_INTACT; /* Only start SMC if SMC RAM is not running */ - if (!ellesmere_is_smc_ram_running(smumgr)) { + if (!polaris10_is_smc_ram_running(smumgr)) { SMU_VFT_INTACT = false; smu_data->protected_mode = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_MODE)); smu_data->security_hard_key = (uint8_t) (SMUM_READ_VFPF_INDIRECT_FIELD(smumgr->device, CGS_IND_REG__SMC, SMU_FIRMWARE, SMU_SEL)); /* Check if SMU is running in protected mode */ if (smu_data->protected_mode == 0) { - result = ellesmere_start_smu_in_non_protection_mode(smumgr); + result = polaris10_start_smu_in_non_protection_mode(smumgr); } else { - result = ellesmere_start_smu_in_protection_mode(smumgr); + result = polaris10_start_smu_in_protection_mode(smumgr); /* If failed, try with different security Key. */ if (result != 0) { smu_data->security_hard_key ^= 1; - result = ellesmere_start_smu_in_protection_mode(smumgr); + result = polaris10_start_smu_in_protection_mode(smumgr); } } if (result != 0) PP_ASSERT_WITH_CODE(0, "Failed to load SMU ucode.", return result); - ellesmere_avfs_event_mgr(smumgr, true); + polaris10_avfs_event_mgr(smumgr, true); } else SMU_VFT_INTACT = true; /*Driver went offline but SMU was still alive and contains the VFT table */ smu_data->post_initial_boot = true; - ellesmere_avfs_event_mgr(smumgr, SMU_VFT_INTACT); + polaris10_avfs_event_mgr(smumgr, SMU_VFT_INTACT); /* Setup SoftRegsStart here for register lookup in case DummyBackEnd is used and ProcessFirmwareHeader is not executed */ - ellesmere_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters), + polaris10_read_smc_sram_dword(smumgr, SMU7_FIRMWARE_HEADER_LOCATION + offsetof(SMU74_Firmware_Header, SoftRegisters), &(smu_data->soft_regs_start), 0x40000); - result = ellesmere_request_smu_load_fw(smumgr); + result = polaris10_request_smu_load_fw(smumgr); return result; } -static int ellesmere_smu_init(struct pp_smumgr *smumgr) +static int polaris10_smu_init(struct pp_smumgr *smumgr) { - struct ellesmere_smumgr *smu_data; + struct polaris10_smumgr *smu_data; uint8_t *internal_buf; uint64_t mc_addr = 0; /* Allocate memory for backend private data */ - smu_data = (struct ellesmere_smumgr *)(smumgr->backend); + smu_data = (struct polaris10_smumgr *)(smumgr->backend); smu_data->header_buffer.data_size = ((sizeof(struct SMU_DRAMData_TOC) / 4096) + 1) * 4096; smu_data->smu_buffer.data_size = 200*4096; @@ -955,28 +955,28 @@ static int ellesmere_smu_init(struct pp_smumgr *smumgr) } static const struct pp_smumgr_func ellsemere_smu_funcs = { - .smu_init = ellesmere_smu_init, - .smu_fini = ellesmere_smu_fini, - .start_smu = ellesmere_start_smu, - .check_fw_load_finish = ellesmere_check_fw_load_finish, - .request_smu_load_fw = ellesmere_reload_firmware, + .smu_init = polaris10_smu_init, + .smu_fini = polaris10_smu_fini, + .start_smu = polaris10_start_smu, + .check_fw_load_finish = polaris10_check_fw_load_finish, + .request_smu_load_fw = polaris10_reload_firmware, .request_smu_load_specific_fw = NULL, - .send_msg_to_smc = ellesmere_send_msg_to_smc, - .send_msg_to_smc_with_parameter = ellesmere_send_msg_to_smc_with_parameter, + .send_msg_to_smc = polaris10_send_msg_to_smc, + .send_msg_to_smc_with_parameter = polaris10_send_msg_to_smc_with_parameter, .download_pptable_settings = NULL, .upload_pptable_settings = NULL, }; -int ellesmere_smum_init(struct pp_smumgr *smumgr) +int polaris10_smum_init(struct pp_smumgr *smumgr) { - struct ellesmere_smumgr *ellesmere_smu = NULL; + struct polaris10_smumgr *polaris10_smu = NULL; - ellesmere_smu = kzalloc(sizeof(struct ellesmere_smumgr), GFP_KERNEL); + polaris10_smu = kzalloc(sizeof(struct polaris10_smumgr), GFP_KERNEL); - if (ellesmere_smu == NULL) + if (polaris10_smu == NULL) return -1; - smumgr->backend = ellesmere_smu; + smumgr->backend = polaris10_smu; smumgr->smumgr_funcs = &ellsemere_smu_funcs; return 0; diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h index 05d636a8e5c9..e5377aec057f 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/ellesmere_smumgr.h +++ b/drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.h @@ -21,18 +21,18 @@ * */ -#ifndef _ELLESMERE_SMUMANAGER_H -#define _ELLESMERE_SMUMANAGER_H +#ifndef _POLARIS10_SMUMANAGER_H +#define _POLARIS10_SMUMANAGER_H -#include <ellesmere_ppsmc.h> +#include <polaris10_ppsmc.h> #include <pp_endian.h> -struct ellesmere_avfs { +struct polaris10_avfs { enum AVFS_BTC_STATUS avfs_btc_status; uint32_t avfs_btc_param; }; -struct ellesmere_buffer_entry { +struct polaris10_buffer_entry { uint32_t data_size; uint32_t mc_addr_low; uint32_t mc_addr_high; @@ -40,11 +40,11 @@ struct ellesmere_buffer_entry { unsigned long handle; }; -struct ellesmere_smumgr { +struct polaris10_smumgr { uint8_t *header; uint8_t *mec_image; - struct ellesmere_buffer_entry smu_buffer; - struct ellesmere_buffer_entry header_buffer; + struct polaris10_buffer_entry smu_buffer; + struct polaris10_buffer_entry header_buffer; uint32_t soft_regs_start; uint8_t *read_rrm_straps; uint32_t read_drm_straps_mc_address_high; @@ -53,15 +53,15 @@ struct ellesmere_smumgr { bool post_initial_boot; uint8_t protected_mode; uint8_t security_hard_key; - struct ellesmere_avfs avfs; + struct polaris10_avfs avfs; }; -int ellesmere_smum_init(struct pp_smumgr *smumgr); +int polaris10_smum_init(struct pp_smumgr *smumgr); -int ellesmere_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit); -int ellesmere_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit); -int ellesmere_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, +int polaris10_read_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t *value, uint32_t limit); +int polaris10_write_smc_sram_dword(struct pp_smumgr *smumgr, uint32_t smc_addr, uint32_t value, uint32_t limit); +int polaris10_copy_bytes_to_smc(struct pp_smumgr *smumgr, uint32_t smc_start_address, const uint8_t *src, uint32_t byte_count, uint32_t limit); #endif diff --git a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c index 06bbe90e8ff6..c483baf6b4fb 100644 --- a/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c +++ b/drivers/gpu/drm/amd/powerplay/smumgr/smumgr.c @@ -30,7 +30,7 @@ #include "cz_smumgr.h" #include "tonga_smumgr.h" #include "fiji_smumgr.h" -#include "ellesmere_smumgr.h" +#include "polaris10_smumgr.h" int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle) { @@ -63,9 +63,9 @@ int smum_init(struct amd_pp_init *pp_init, struct pp_instance *handle) case CHIP_FIJI: fiji_smum_init(smumgr); break; - case CHIP_BAFFIN: - case CHIP_ELLESMERE: - ellesmere_smum_init(smumgr); + case CHIP_POLARIS11: + case CHIP_POLARIS10: + polaris10_smum_init(smumgr); break; default: return -EINVAL; |
