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authorStewart Smith <stewart@linux.ibm.com>2018-08-16 19:46:03 +1000
committerStewart Smith <stewart@linux.ibm.com>2018-08-16 19:50:24 +1000
commit28b0ca5a63ca40b51ed5e61072320745600b7828 (patch)
tree13a16b2ba9e60f59272d05dff99ea17d1053f948 /doc
parentd413f4e361976d123b2cbdad816b9de49958591d (diff)
downloadtalos-op-build-28b0ca5a63ca40b51ed5e61072320745600b7828.tar.gz
talos-op-build-28b0ca5a63ca40b51ed5e61072320745600b7828.zip
op-build v2.0.9 release notes
Signed-off-by: Stewart Smith <stewart@linux.ibm.com>
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+Release Notes for OpenPower Firmware v2.0.9
+===========================================
+
+op-build v2.0.9 was released on Thursday August 16th, 2018 and replaces op-build v2.0.8 as the current stable release in
+the 2.0.x series.
+
+It is recommended that v2.0.9 be used over any previous v2.0.x version on POWER9 systems due to the bug fixes contained within.
+
+The only update in this release is to skiboot. Skiboot v6.0.8 includes the following bug fixes:
+- i2c: Ensure ordering between i2c_request_send() and completion
+
+ i2c_request_send loops waiting for a flag "uc.done" set by
+ the completion routine, and then look for a result code
+ also set by that same completion.
+
+ There is no synchronization, the completion can happen on another
+ processor, so we need to order the stores to uc and the reads
+ from uc so that uc.done is stored last and tested first using
+ memory barriers.
+- i2c: Fix multiple-enqueue of the same request on NACK
+
+ i2c_request_send() will retry the request if the error is a NAK,
+ however it forgets to clear the "ud.done" flag. It will thus
+ loop again and try to re-enqueue the same request causing internal
+ request list corruption.
+- phb4: Disable 32-bit MSI in capi mode
+
+ If a capi device does a DMA write targeting an address lower than 4GB,
+ it does so through a 32-bit operation, per the PCI spec. In capi mode,
+ the first TVE entry is configured in bypass mode, so the address is
+ valid. But with any (bad) luck, the address could be 0xFFFFxxxx, thus
+ looking like a 32-bit MSI.
+
+ We currently enable both 32-bit and 64-bit MSIs, so the PHB will
+ interpret the DMA write as a MSI, which very likely results in an EEH
+ (MSI with a bad payload size).
+
+ We can fix it by disabling 32-bit MSI when switching the PHB to capi
+ mode. Capi devices are 64-bit.
+
+- capp: Fix the capp recovery timeout comparison
+
+ The current capp recovery timeout control loop in
+ do_capp_recovery_scoms() uses a wrong comparison for return value of
+ tb_compare(). This may cause do_capp_recovery_scoms() to report an
+ timeout earlier than the 168ms stipulated time.
+
+ The patch fixes this by updating the loop timeout control branch in
+ do_capp_recovery_scoms() to use the correct enum tb_cmpval.
+- phb4/capp: Update DMA read engines set in APC_FSM_READ_MASK based on link-width
+
+ Commit 47c09cdfe7a3("phb4/capp: Calculate STQ/DMA read engines based
+ on link-width for PEC") update the CAPP init sequence by calculating
+ the needed STQ/DMA-read engines based on link width and populating it
+ in XPEC_NEST_CAPP_CNTL register. This however needs to be synchronized
+ with the value set in CAPP APC FSM Read Machine Mask Register.
+
+ Hence this patch update phb4_init_capp_regs() to calculate the link
+ width of the stack on PEC2 and populate the same values as previously
+ populated in PEC CAPP_CNTL register.
+
+- core/cpu: Call memset with proper cpu_thread offset
+
+
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