path: root/src/occ_gpe1/gpe1_dimm_control.c

/* IBM_PROLOG_BEGIN_TAG                                                   */
/* This is an automatically generated prolog.                             */
/*                                                                        */
/* $Source: src/occ_gpe1/gpe1_dimm_control.c $                            */
/*                                                                        */
/* OpenPOWER OnChipController Project                                     */
/*                                                                        */
/* Contributors Listed Below - COPYRIGHT 2015,2018                        */
/* [+] International Business Machines Corp.                              */
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/* Licensed under the Apache License, Version 2.0 (the "License");        */
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/* IBM_PROLOG_END_TAG                                                     */

#include "pk.h"
#include "ppe42_scom.h"
#include "ipc_api.h"
#include "ipc_async_cmd.h"
#include "gpe_err.h"
#include "gpe_util.h"
#include "dimm_structs.h"
#include "mca_addresses.h"
#include "gpe1.h"
#include "gpe1_dimm.h"

/*
 * Function Specifications:
 *
 * Name: gpe_scom_nvdimms_nimbus
 *
 * Description: Sends SCOMs to NVDIMMs to tell them to back up their data.
 *              Occurs when GPIO_EPOW is asserted.
 *
 * Inputs:      cmd is a pointer to IPC msg's cmd and cmd_data struct
 *
 * End Function Specification
 */
void gpe_scom_nvdimms_nimbus(ipc_msg_t* cmd, void* arg)
{
    int rc = 0;
    int mc = 0;
    int port = 0;
    uint64_t mbarpc_regValue = 0;
    uint64_t mbastr_regValue = 0;
    ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;

    epow_gpio_args_t *args = (epow_gpio_args_t*)async_cmd->cmd_data;

    // Debug trace - Can remove
    PK_TRACE("gpe_scom_nvdimms_nimbus: configured_mbas: 0x%04x",
                args->configured_mbas );

    // Iterate over each bit in configured_mbas
    // If mc is configured, send scoms
    uint16_t mask = 0x8000;
    for (mc = 0; mc < NUM_MBAS_NIMBUS; mc++)
    {
        for (port = 0; port < NUM_PORTS_PER_MBA; port++)
        {
            if (args->configured_mbas & mask)
            {
                PK_TRACE("gpe_scom_nvdimms_nimbus: scoms for mc: %d, port: %d", mc, port);

                const uint32_t reg_MBARPC0Q = POWER_CTRL_REG0(mc,port);
                // Step 1 - In MBARPC0Q, disable power domain control, set domain
                //          to MAXALL_MINALL(0b000), and enable minimum domain
                //          reduction
                //          bit  2   - power domain control,
                //          bits 3:5 - min/max domains
                //          bit  22  - domain reduction
                rc = getscom_abs(reg_MBARPC0Q, &mbarpc_regValue);
                if (rc)
                {
                    PK_TRACE("E>gpe_scom_nvdimms_nimbus: Failed to read (MBARPC0Q) Reg:0x%08X, rc:0x%08x",
                             reg_MBARPC0Q, rc);
                }
                else
                {
                    mbarpc_regValue &= 0xC3FFFFFFFFFFFFFF; // zero out bits 2-5
                    mbarpc_regValue |= 0x0000020000000000; // set bit 22
                    rc = putscom_abs(reg_MBARPC0Q, mbarpc_regValue);
                    if (rc)
                    {
                        PK_TRACE("E>gpe_scom_nvdimms_nimbus: Failed to disable power domain control (MBARPC0Q)"
                                 " Reg:0x%08X, Data:0x%08X %08X, rc:0x%08x",
                                 reg_MBARPC0Q, WORD_HIGH(mbarpc_regValue), WORD_LOW(mbarpc_regValue), rc);
                        gpe_set_ffdc(&(args->error), reg_MBARPC0Q,
                                     GPE_RC_SCOM_PUT_FAILED, rc);
                    }

                    // Step 2 - In MBASTR0Q, enable STR entry
                    //          bit  0   - STR enable
                    const uint32_t reg_MBASTR0Q = STR_REG0(mc,port);
                    rc = getscom_abs(reg_MBASTR0Q, &mbastr_regValue);
                    if (rc)
                    {
                        PK_TRACE("E>gpe_scom_nvdimms_nimbus: Failed to read (MBASTR0Q) Reg:0x%08X, rc:0x%08x",
                                 reg_MBASTR0Q, rc);
                    }
                    else
                    {
                        mbastr_regValue |= 0x8000000000000000; // set bit 0
                        rc = putscom_abs(reg_MBASTR0Q, mbastr_regValue);
                        if (rc)
                        {
                            PK_TRACE("E>gpe_scom_nvdimms_nimbus: Failed to enable STR entry (MBASTR0Q)"
                                     " Reg:0x%08X, Data:0x%08X %08X, rc:0x%08x",
                                     reg_MBASTR0Q, WORD_HIGH(mbastr_regValue), WORD_LOW(mbastr_regValue), rc);
                            gpe_set_ffdc(&(args->error), reg_MBASTR0Q,
                                         GPE_RC_SCOM_PUT_FAILED, rc);
                        }
                    }

                    // Step 3 - In MBARPC0Q, re-enable power domain control
                    //          bit  2   - power domain control
                    mbarpc_regValue |= 0x2000000000000000; // set bit 2
                    rc = putscom_abs(reg_MBARPC0Q, mbarpc_regValue);
                    if (rc)
                    {
                        PK_TRACE(">gpe_scom_nvdimms_nimbus: Failed to re-enable power domain control (MBARPC0Q)"
                                 " Reg:0x%08X, Data:0x%08X %08X, rc:0x%08x",
                                 reg_MBARPC0Q, WORD_HIGH(mbarpc_regValue), WORD_LOW(mbarpc_regValue), rc);
                        gpe_set_ffdc(&(args->error), reg_MBARPC0Q,
                                     GPE_RC_SCOM_PUT_FAILED, rc);
                    }
                }
            }
            mask = mask >> 1;
        } // for each MBA port
    } // for each MC

    PK_TRACE("gpe_scom_nvdimms_nimbus: completed (rc=%d)", rc);

    // Always send back success
    rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);
    if(rc)
    {
        PK_TRACE("E>gpe_scom_nvdimms_nimbus: Failed to send response back (rc=%d)", rc);
        gpe_set_ffdc(&(args->error), 0x00, GPE_RC_IPC_SEND_FAILED, rc);
        pk_halt();
    }

    PK_TRACE("gpe_scom_nvdimms_nimbus: exiting");

} // end gpe_scom_nvdimms_nimbus()

/*
 * Function Specifications:
 *
 * Name: gpe_dimm_control
 *
 * Description:  DIMM control code on the GPE
 *
 * Inputs:       cmd is a pointer to IPC msg's cmd and cmd_data struct
 *
 * Outputs:      error: sets rc, address, and ffdc in the cmd_data's
 *                      GpeErrorStruct
 *
 * End Function Specification
 */
void gpe_dimm_control(ipc_msg_t* cmd, void* arg)
{
    // Note: arg was set to 0 in ipc func table (ipc_func_tables.c), so don't use it.
    // the ipc arguments passed through the ipc_msg_t structure, has a pointer
    // to the dimm_control_args_t struct.

    int      rc;
    uint64_t regValue; // a pointer to hold the putscom_abs register value
    ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
    dimm_control_args_t *args = (dimm_control_args_t*)async_cmd->cmd_data;

    int mc = args->mc, port = args->port; // memory controller pair and port

    args->error.error = 0;
    args->error.ffdc = 0;

    do
    {   // read N/M DIMM Throttling Control SCOM Register for specified MC pair and port numbers
        rc = getscom_abs(N_M_DIMM_TCR(mc,port), &regValue);
        if(rc)
        {
            PK_TRACE("gpe_dimm_control: N/M DIMM Throttling Control Register read fails"
                     "MC#|Port:0x%08x, Address:0x%08x, rc:0x%08x",
                     (uint32_t)((mc << 16) | port),
                     N_M_DIMM_TCR(mc,port), rc);

            gpe_set_ffdc(&(args->error), N_M_DIMM_TCR(mc,port),
                         GPE_RC_SCOM_GET_FAILED, rc);
            break;
        }

        // Store the M values if needed
        if( args->dimmDenominatorValues.need_m )
        {
            args->dimmDenominatorValues.m_value = ((regValue & 0x1FFF80000) >> 19);
        }

        // If this isn't set, we didn't need to set the N value, just needed M
        if(!args->dimmNumeratorValues.new_n)
        {
            break;
        }

        // Clear old N values for slot and port
        regValue &= 0x1FFFFFFFF;
        // copy slot and port N values (31 bits) from passed dimmNumeratorValues
        regValue |=  ((uint64_t) (args->dimmNumeratorValues.word32 & 0xFFFFFFFE)) << 32 ;

        // Write new slot and port N Values
        rc = putscom_abs(N_M_DIMM_TCR(mc,port), regValue);
        if(rc)
        {
            PK_TRACE("gpe_dimm_control: N/M DIMM Throttling Control Register write fails"
                     "dimm#:%d, Address:0x%04x, Nvalues:0x%08x, rc:0x%08x",
                     (uint16_t)((mc << 8) | port),
                     N_M_DIMM_TCR(mc,port), regValue, rc);

            gpe_set_ffdc(&(args->error), N_M_DIMM_TCR(mc,port),
                         GPE_RC_SCOM_PUT_FAILED, rc);
            break;
        }
        else
        {
            GPE1_DIMM_DBG("gpe_dimm_control: N/M DIMM Throttling Control Register write"
                          "mc|port#:0x%04x, Address:0x%08x, Nvalues:0x%08x",
                          (uint16_t)((mc << 8) | port),
                          N_M_DIMM_TCR(mc,port), regValue);
        }
    } while(0);

    // send back a response, IPC success even if ffdc/rc are non zeros
    rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);
    if(rc)
    {
        PK_TRACE("E>gpe_dimm_control: Failed to send response back. Halting GPE1 (rc=%d)", rc);
        gpe_set_ffdc(&(args->error), 0x00, GPE_RC_IPC_SEND_FAILED, rc);
        pk_halt();
    }
}

/*
 * Function Specifications:
 *
 * Name: gpe_reset_mem_deadman
 *
 * Description:  Read memory performance counter for one MCA.
 *               This effectively resets the memory deadman timer
 *
 * Inputs:       cmd is a pointer to IPC msg's cmd and cmd_data struct
 *
 * Outputs:      error: sets rc, address, and ffdc in the cmd_data's
 *                      GpeErrorStruct
 *
 * End Function Specification
 */

void gpe_reset_mem_deadman(ipc_msg_t* cmd, void* arg)
{
    // Note: arg was set to 0 in ipc func table (ipc_func_tables.c), so don't use it.
    // the ipc arguments passed through the ipc_msg_t structure, has a pointer
    // to the reset_mem_deadman_args_t struct.

    static bool L_init_complete[NUM_NIMBUS_MCAS] = {FALSE};
    int      rc = 0;
    uint64_t regValue; // a pointer to hold get/put SCOM register value
    ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
    reset_mem_deadman_args_t *args = (reset_mem_deadman_args_t*)async_cmd->cmd_data;

    args->error.error = 0;
    args->error.ffdc = 0;

    do
    {
        int mca = args->mca; // Nimbus MCA; mc_pair = mca >>2 and port = mca & 3

        // Part of init is to enable the deadman timer for this MCA
        if(!L_init_complete[mca])
        {
            // Read STR Register 0
            rc = getscom_abs(STR_REG0_MCA(mca), &regValue);

            if(rc)
            {
                PK_TRACE("gpe_reset_mem_deadman: Failed to read STR0 to program deadman timer"
                         " MCA:0x%08x, Address:0x%08x, rc:0x%08x", mca, STR_REG0_MCA(mca), rc);

                gpe_set_ffdc(&(args->error), STR_REG0_MCA(mca),
                             GPE_RC_SCOM_GET_FAILED, rc);
                break;
            }

            // set the deadman timer to the max value: bits 57:60 = 0b1000
            regValue |= 0x0000000000000040;
            regValue &= ~(0x0000000000000038);

            // Write Modified STR Register 0
            rc = putscom_abs(STR_REG0_MCA(mca), regValue);

            if(rc)
            {
                PK_TRACE("gpe_reset_mem_deadman: Failed to program deadman timer (STR REG0)"
                         " MCA:0x%08x, Data:0x%08x, rc:0x%08x", mca, (uint32_t)regValue, rc);

                gpe_set_ffdc(&(args->error), STR_REG0_MCA(mca),
                             GPE_RC_SCOM_PUT_FAILED, rc);
                break;
            }
        }

        // The "Deadman" timer is reset by reading from this performance monitor counts register
        rc = getscom_abs(PERF_MON_COUNTS_IDLE_MCA(mca), &regValue);
        if(rc)
        {
            PK_TRACE("gpe_reset_mem_deadman: Performance Monitor Counts read failed"
                     " MCA:0x%08x, Address:0x%08x, rc:0x%08x",
                     mca, PERF_MON_COUNTS_IDLE_MCA(mca), rc);

            gpe_set_ffdc(&(args->error), PERF_MON_COUNTS_IDLE_MCA(mca),
                         GPE_RC_SCOM_GET_FAILED, rc);
            break;
        }
        else
        {
            args->idle_counts.med_idle_cnt = ((regValue & 0xFFFFFFFF00000000) >> 32);
            args->idle_counts.high_idle_cnt = (regValue & 0xFFFFFFFF);
        }

        // Now that we are poking the deadman timer as second part of init check for and clear
        // any previous emergency throttle that may have happened from the last time OCC was running
        if(!L_init_complete[mca])
        {
            L_init_complete[mca] = TRUE; // Done handling initialization

            // Read Emergency Throttle Register
            rc = getscom_abs(ER_THROTTLE_MCA(mca), &regValue);

            if(rc)
            {
                PK_TRACE("gpe_reset_mem_deadman: Failed to read emergency throttle register"
                         " MCA:0x%08x, Address:0x%08x, rc:0x%08x", mca, ER_THROTTLE_MCA(mca), rc);

                gpe_set_ffdc(&(args->error), ER_THROTTLE_MCA(mca), GPE_RC_SCOM_GET_FAILED, rc);
                break;
            }

            // clear Emergency Throttle In-Progress bit if set, this is indication that OCC has been
            // re-started from permanent safe mode without an IPL
            if(regValue & ER_THROTTLE_IN_PROGRESS_MASK)
            {
                PK_TRACE("gpe_reset_mem_deadman: Enabled timer and clearing throttle for MCA:0x%08x", mca);
                regValue &= ~(ER_THROTTLE_IN_PROGRESS_MASK);

                // Write Modified Emergency Throttle Register
                rc = putscom_abs(ER_THROTTLE_MCA(mca), regValue);

                if(rc)
                {
                    PK_TRACE("gpe_reset_mem_deadman: Failed to clear emergency throttle"
                             " MCA:0x%08x, rc:0x%08x", mca, rc);

                    gpe_set_ffdc(&(args->error), ER_THROTTLE_MCA(mca), GPE_RC_SCOM_PUT_FAILED, rc);
                    break;
                }

                // Clear the emergency throttle engaged FIR bit
                rc = getscom_abs(MCA_CAL_FIR_REG_MCA(mca), &regValue);

                if(rc)
                {
                    PK_TRACE("gpe_reset_mem_deadman: Failed to read MCA FIR register"
                             " MCA:0x%08x, Address:0x%08x, rc:0x%08x",
                             mca, MCA_CAL_FIR_REG_MCA(mca), rc);

                    gpe_set_ffdc(&(args->error), MCA_CAL_FIR_REG_MCA(mca), GPE_RC_SCOM_GET_FAILED, rc);
                    break;
                }
                regValue &= ~(MCA_FIR_THROTTLE_ENGAGED_MASK);

                // Write Modified MCA FIR Register
                rc = putscom_abs(MCA_CAL_FIR_REG_MCA(mca), regValue);

                if(rc)
                {
                    PK_TRACE("gpe_reset_mem_deadman: Failed to clear emergency throttle FIR bit"
                             " MCA:0x%08x, rc:0x%08x", mca, rc);

                    gpe_set_ffdc(&(args->error), MCA_CAL_FIR_REG_MCA(mca), GPE_RC_SCOM_PUT_FAILED, rc);
                    break;
                }
            }
            else
            {
                PK_TRACE("gpe_reset_mem_deadman: Enabled timer for MCA:0x%08x", mca);
            }
        }  // if !L_init_complete

        // In addition to resetting the "deadman" counter, get some performance information
        rc = getscom_abs(PERF_MON_COUNTS0_MCA(mca), &regValue);
        if(rc)
        {
            PK_TRACE("gpe_reset_mem_deadman: Performance Monitor Counts0 read failed"
                     " MCA:0x%08x, Address:0x%08x, rc:0x%08x",
                     mca, PERF_MON_COUNTS0_MCA(mca), rc);

            gpe_set_ffdc(&(args->error), PERF_MON_COUNTS0_MCA(mca),
                         GPE_RC_SCOM_GET_FAILED, rc);
            break;
        }
        else
        {
            args->rd_wr_counts.mba_read_cnt = ((regValue & 0xFFFFFFFF00000000) >> 32);
            args->rd_wr_counts.mba_write_cnt = (regValue & 0xFFFFFFFF);
        }

    } while(0);

    // send back a response, IPC success even if ffdc/rc are non zeros
    rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);
    if(rc)
    {
        PK_TRACE("E>gpe_reset_mem_deadman: Failed to send response back. Halting GPE1 (rc=%d)", rc);
        gpe_set_ffdc(&(args->error), 0x00, GPE_RC_IPC_SEND_FAILED, rc);
        pk_halt();
    }
}