blob: f4a298e7b1f2b4c8d964b92a42cfda0534b8a0dc (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
|
/* IBM_PROLOG_BEGIN_TAG */
/* This is an automatically generated prolog. */
/* */
/* $Source: src/include/registers/sramctl_register_addresses.h $ */
/* */
/* OpenPOWER OnChipController Project */
/* */
/* Contributors Listed Below - COPYRIGHT 2015,2016 */
/* [+] International Business Machines Corp. */
/* */
/* */
/* Licensed under the Apache License, Version 2.0 (the "License"); */
/* you may not use this file except in compliance with the License. */
/* You may obtain a copy of the License at */
/* */
/* http://www.apache.org/licenses/LICENSE-2.0 */
/* */
/* Unless required by applicable law or agreed to in writing, software */
/* distributed under the License is distributed on an "AS IS" BASIS, */
/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */
/* implied. See the License for the specific language governing */
/* permissions and limitations under the License. */
/* */
/* IBM_PROLOG_END_TAG */
#ifndef __SRAMCTL_REGISTER_ADDRESSES_H__
#define __SRAMCTL_REGISTER_ADDRESSES_H__
/// \file sramctl_register_addresses.h
/// \brief Symbolic addresses for the SRAMCTL unit
// *** WARNING *** - This file is generated automatically, do not edit.
#define SRAMCTL_OCI_BASE 0x40050000
#define SRAMCTL_SRBAR 0x40050000
#define SRAMCTL_SRMR 0x40050008
#define SRAMCTL_SRMAP 0x40050010
#define SRAMCTL_SREAR 0x40050018
#define SRAMCTL_SRBV0 0x40050020
#define SRAMCTL_SRBV1 0x40050028
#define SRAMCTL_SRBV2 0x40050030
#define SRAMCTL_SRBV3 0x40050038
#define SRAMCTL_SRCHSW 0x40050040
#endif // __SRAMCTL_REGISTER_ADDRESSES_H__
|
