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* Use HOMER Init DataWael El-Essawy2016-10-113-112/+55
| | | | | | | | | | | | | Enable reading and usage of HOMER init data. i.e. nest frequency, attention type... Change-Id: Ic9e0bc47fc110983e7e995191eda1ed6578a1ae8 RTC: 145754 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30674 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Save Core & Quad DTS AvgsWilliam Bryan2016-10-1116-210/+338
| | | | | | | | | | Change-Id: I7c57c072f4f84f02ce7bbc5f95c80a4901d6c9a2 RTC:160341 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30180 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* SSX Runtime Environment CheckWilliam Bryan2016-10-116-20/+57
| | | | | | | | | | | RTC: 139829 Change-Id: Ic43ab936fd9d9b0d41270bbea50cd3969d9f8432 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30063 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Fix Centaur Control Module IDWael El-Essawy2016-10-052-2/+3
| | | | | | | | | | | Even though the code is commented out, it has to be fixed to pass the firestation test. Change-Id: I6ed3829cb8ae0a329f9e4d78d6c7aba9cd69a71d Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30737 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Implement Current Mode and Idle State in the Poll ResponseWael El-Essawy2016-10-041-1/+6
| | | | | | | | | | Change-Id: Ib2197e2197fae41455b4a8c39861eb891e1f0838 RTC: 161994 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/30632 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Enable APSS Composite ModeWilliam Bryan2016-09-302-3/+3
| | | | | | | | | | RTC:132559 Change-Id: Id66a6ee7083031f0a6a3364f4f01bdc9886ca638 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29070 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Sync HW SSX with OCC FW SSXWilliam Bryan2016-09-293-3/+9
| | | | | | | | Change-Id: I2d416da654566747f40df3bed0e122919fc514e7 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29592 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Collect Nest DTS AverageWilliam Bryan2016-09-2917-38/+231
| | | | | | | | | | RTC:133842 Change-Id: I565a6f2e848652b7eddd3b319f9c3a411913074a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29804 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Enable power capping and oversubscription. RTC:137621 RTC:133156mbroyles2016-09-2923-403/+319
| | | | | | | | Change-Id: I98b745ccb56d89d066508d4195250b1bf446dbc6 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29898 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
* Enable FW Timing SensorsWael El-Essawy2016-09-233-64/+52
| | | | | | | | | | | Enable scheduling of the GPE NOP task to do GPE timings and verify all sensors being updated in amec_update_fw_sensors() are being populated correctly. Change-Id: I623dd7518be9a8736e601c7d2fa748097a4d773a RTC: 141299 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29849 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Update extended RC to 2 bytesWilliam Bryan2016-09-234-99/+101
| | | | | | | | | RTC: 148702 Change-Id: I4e0c7486333a17009061c52c42bb1c96367879ae Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29331 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Enable FREQ and CAPS "sensor" sections in poll responseWael El-Essawy2016-09-208-9/+30
| | | | | | | | | | | Populate the "FREQ" and "CAPS" sections with data in the poll response according to the interface spec Change-Id: I65ac8602776f12e796d3c6cae8e49215177f942c RTC: 143442 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29913 Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Tested-by: Wael El-Essawy <welessa@us.ibm.com>
* Do not overwrite DIMM gpe args prior to op completionChris Cain2016-09-201-37/+48
| | | | | | | | | Change-Id: Ia7f935441a351eb9916620cfd405293f08defd4e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29905 Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Tested-by: Christopher J. Cain <cjcain@us.ibm.com>
* Memory Temperature Control Loop (memory throttling)Wael El-Essawy2016-09-1637-727/+1518
| | | | | | | | | | | | * Memory throttling due to over temp * Throttle when reach timeout getting new temperature readings * Log error for temperature exceeding ERROR threshold Change-Id: I089c88aadba84e7296ad87b8cb87fa8c045ff912 RTC: 131188 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28933 Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Tested-by: Wael El-Essawy <welessa@us.ibm.com>
* Linker script cleanupWilliam Bryan2016-09-014-73/+68
| | | | | | | | | | RTC:134263 Change-Id: I943493f7855ae002dbba929494d8bed85bbe2596 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29046 Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
* Update build process for OpenPOWERWilliam Bryan2016-08-261-1/+1
| | | | | | | | | | Change-Id: I0852869bdc9d527c54112de7223b6e95111c750a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28741 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
* EMPATH Sensor CountersWilliam Bryan2016-08-2620-586/+460
| | | | | | | | | | | | RTC:148388 Change-Id: Iae66cd0a73032fa908eb96a149d4163397c2e275 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27781 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
* Checkpoint improvementsChris Cain2016-08-259-50/+124
| | | | | | | | | Change-Id: I08d76ac1db6e425a9690864f693f36cb848cead5 RTC: 153965 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28188 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Add DIMM temperature validation, update fru flags, and rename dimm sensorChris Cain2016-08-1111-34/+121
| | | | | | | | | Change-Id: Ie201160d92b0d00dd523c78eb1496a1b05e2647a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27836 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
* Remove IBM Confidential DisclaimersWilliam Bryan2016-08-021-6/+1
| | | | | | | | Change-Id: Ie3dcd5b6cee3e6b191cf136d30af634c9966318e Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27718 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
* Delete unused files, update PK, and use new compilersWilliam Bryan2016-07-292-5/+15
| | | | | | | | Change-Id: I9e4951a2cebd204d1ea752c63e3f2b532ad3a2db Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27465 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Command Changes for fan control and cappingChris Cain2016-07-134-76/+73
| | | | | | | | | | Change-Id: Ib8ba444674bbf5b5554f12730aaffa3ce7c087e4 RTC: 155693 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26005 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
* Fix DIMM temperature error handling for poll responseWilliam Bryan2016-06-294-43/+51
| | | | | | | | | | | RTC:155187 Change-Id: I38039dc18de9bfc5b9194f63b3b869bf7c16991f Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/26067 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Update SSX to latest in EKBWilliam Bryan2016-06-136-5/+13
| | | | | | | | RTC: 132999 Change-Id: I29478c074e3086e0bf09b402d55782e03cb1f787 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23394 Tested-by: FSP CI Jenkins Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Processor Thermal Control LoopWael El-Essawy2016-06-1312-175/+55
| | | | | | | | | | | | | | | | | | | Enable processor thermal control loop. Enable frequency votes due to thermal and error reading temperatures. Verify The following: *Error log generation when a proc reaches Error limit *Reach throttle points when: -- Processor reached over temperature limit -- Processor temperature sensors timeout enable transition to active mode Change-Id: Iae24f64a872e031e1cf93ff0d9248d3fa3847ed7 RTC: 130210 RTC: 133942 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/25458 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Add support for Clear Error Log commandsWael El-Essawy2016-06-011-2/+2
| | | | | | | | | | | | uncommented "clear error log" command, tested command in simics. Change-Id: Id9afe81a58b797713f0aced63428ddd230823935 RTC: 133943 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24983 Tested-by: FSP CI Jenkins Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Pstate Infrastructure & Support config data required for active stateWael El-Essawy2016-05-2524-1442/+435
| | | | | | | | | | | | | | | | | | | | | | | | - Support all config data required for active state. - Set 'active ready' bit in poll response when all config data has been received. - Rewrite & rename proc_gpsm_pstate_initialize() - Delete GPSM, doesn't exist. - Put in TODO call PGPE to enable pstates this will also be telling PGPE how to set PMCR mode register (OCC control pstates or OPAL). - Initialize globals for fmax, fmin, pmax and mhz_per_pstate with temporary hard codes until PGPE is available. - Call to "proc_pstate_initialize()" moved to state transition to observation - Cleanup proc_freq2pstate() - rewrite amec_slv_freq_smh() - the calls to proc_set_core_bounds() and proc_set_core_pstate() will be replaced with 1 IPC call to the PGPE to set pmin/pmax given all cores or set pstate for all given cores. - Remove all DCM related code. Change-Id: I449d188b2cffc345afca19717dcbea037f159114 RTC:130224 RTC:150935 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23977 Tested-by: FSP CI Jenkins Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Fix up SRC parsing errorsWilliam Bryan2016-05-132-4/+6
| | | | | | | | Change-Id: I4c708fbc0158577ff143462490e7abe8d3795d66 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24382 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Commit the FSP_COMM_INITIALIZED checpoint only if no errors occurWael El-Essawy2016-05-131-2/+5
| | | | | | | | | Change-Id: I4a40950cabc7712f31b776d2a1472e0b4dd7eee8 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24044 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Fix Ping Pong and HOMER addresses, usign new P9 pba_region default value.Wael El-Essawy2016-05-1315-98/+123
| | | | | | | | | | | | | | | | | | | | | | | The new P9 pba_region field in the PBA_MODE register is now 0b10 contrary to the P8 pba_region setting of 0b00. Addresses have been corrected for Ping Pong communications, HOMER Host Data, Sapphire Table, and HTMGT send and receive Buffers. Replaced Sapphire legacy term with OPAL. Defined COMMON_BASE_ADDRESS, and offset addresses relative to it. modified HOMER_HD_OFFSET, OCC_HTMGT_CMD_OFFSET_HOMER, OCC_HTMGT_RSP_OFFSET_HOMER, and OPAL_OFFSET_HOMER according to new P9 specifications. Change-Id: Ib233181c4ad1837b57c45144d1256b87799dc5bc Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/24085 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Build full OCC image and update build processWilliam Bryan2016-05-044-22/+40
| | | | | | | | Change-Id: I8e6d716a48f30021b653e850c74deb7526cfe293 RTC:133001 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22155 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Change attention type default to FSPWael El-Essawy2016-05-037-619/+13
| | | | | | | | | Change-Id: I6661e64e2bb29762ba038bddcebd9e6b4afcf85e RTC: 147814 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23618 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Create common handling path for FSP and BMC communicationChris Cain2016-04-2910-261/+144
| | | | | | | | | | Change-Id: Ie6eaa2054bb47d1b48d466409ebb44cbae2ea0ad RTC: 150749 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23616 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
* Poll with sensor support and power accumulator resizeChris Cain2016-04-1912-276/+295
| | | | | | | | | | Change-Id: I64eb18a567e8d899de085903412a9b4fd13e4be7 RTC: 148327 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22365 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
* Fix occ/ssx_checkpoint_panic_and_save_ffdc bugs and create two deathbedsWael El-Essawy2016-04-121-12/+64
| | | | | | | | | | | | | | | | | | | | | | 1. use r3 to index the lmw instruction. r0 is not a valid index register for this command ((RA|0) in the 405 user's manual). This maintains the integrity of the r1 register, and hence the correct restoration of all registers. 2. store the LR to the stack at the entrance of called functions, and restoring fron the stack before calling the blr return instruction. 3. to avoid infinite loop through the occ/ssx_checkpoint_panic_and_save_ffdc routines, two branch to self (deathbed) locations were created. In multichip systems, this will avoid competing for the FFDC scom registers, which may be causing an FFDC SCOM access timeout due to SCOM_PROTOCOL_ERROR_GETSCOM_BUSY error (0x00726615). Change-Id: Ifc1616212b4abdbce83008c4ba1ea16289ddaab2 CQ: SW324506 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21101 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Enable Master-slave OCC communicationWael El-Essawy2016-04-0525-464/+303
| | | | | | | | | | Change-Id: I445072e20d599e30f80cc8059b3f3b2a956c453e RTC: 133154 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22005 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Moving OCC Common Image from BAR3 to BAR2Wael El-Essawy2016-03-291-6/+6
| | | | | | | | | | Change-Id: Ied1545784fd0f4aa2e0fca0dcc04231795b8a8f2 RTC: 131182 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22481 Tested-by: FSP CI Jenkins Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Write error logs to SRAM for TMGT to collectWael El-Essawy2016-03-011-50/+21
| | | | | | | | | Change-Id: Iafba9e2b35c5ab9044cbea3ee2cf7fdc9c2834b9 RTC: 133943 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/21100 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Implement I2C locking with hostChris Cain2016-03-0116-528/+1039
| | | | | | | | | | Change-Id: I9e99e799e0df442bebef473360ca87d564f5ddaf RTC: 140545 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/12898 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
* Fix Bug: FFDC_BUFFER_ADDR not matching _LINEAR_RD_WINDOW_SECTION_BASEWael El-Essawy2016-02-162-3/+3
| | | | | | | | | | add comments to stress that these two variables must match Change-Id: I0e1571e1f092a16e142baf6a9d0625731ad0101a Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/24332 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Changed poll response to version 0x20William Bryan2016-01-279-238/+176
| | | | | | | | | RTC: 143441 Change-Id: Ib964b5f8d8b00029971935ffc8eb957975dc6cce Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/23406 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
* Implement code to read DIMM temperaturesChris Cain2016-01-2718-74/+960
| | | | | | | | | | Change-Id: I98fc83ab1c78bd40241fe6e47a9ddeae24f78c38 RTC: 140093 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22770 Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher Cain <cjcain@us.ibm.com>
* OCC GPE0: HWP to read Core/Quad DTSWael El-Essawy2016-01-191-3/+9
| | | | | | | | | | | | Updating the code with HWP, simulated under simics with core and quad DTSs, and verified trace results. Change-Id: I914d65687f7c26d7073edae846de6a2c6f84cc02 RTC: 140095 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22929 Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: Wael Elessawy <welessa@us.ibm.com>
* Enabled reading CCSR via OCIWilliam Bryan2016-01-153-41/+16
| | | | | | | | | RTC: 140187 Change-Id: I3ad92658c18e76f58b3e7c9733e97cff437c7cdc Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22581 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
* Enable state transition to observationWilliam Bryan2015-12-1512-40/+62
| | | | | | | | | | | Enabled DCOM thread RTC:140900 Change-Id: I857e2c4b2a15903ccddc2df5db910dddf155a8e5 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22658 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
* CC: Support Thermal Control Threshold Config Data format 0x13Wael El-Essawy2015-12-1117-909/+164
| | | | | | | | | | | | | | | | | | | | | Support thermal control thresholds format 0x13 config data command with new version 0x20 defined in P9 interface spec. All older P8 versions of format 0x13 deleted. Tested in simics. remove thermal thread. fix a dts calculation bug. add a firmware failure error log. Change-Id: I4a9979929292833a5e6f4f7f4e162ea20983b96a RTC: 141647 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22516 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
* Enable system config command and sensor listWilliam Bryan2015-12-109-152/+328
| | | | | | | | | | | Added configuration data debug command RTC: 141643 Change-Id: I3d98321508780c25795d66a8d353c36593448a6e Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22549 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
* Fix Timing Discrepancy between OCC and PPEsWael El-Essawy2015-12-092-5/+8
| | | | | | | | | | | | | | Fix the code so that The whole OCC complex runs at the same (nest) frequency. This is the POR, which also solves the timing bug. Change-Id: Ib33c1951384b552fc4a44e07be09e9261a4b133d RTC: 139478 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22554 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
* P9 change set APSS commandSheldon Bailey2015-12-083-119/+19
| | | | | | | | | RTC: 142759 Change-Id: Ia9032569afa954e58a1989d97de1a4dad4f221e4 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22512 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Change temperature sensor ID to uint32mbroyles2015-12-071-4/+4
| | | | | | | | Change-Id: Ic8e1ae62f203b3e9889ab0c4cd6dcb56226ea6cb Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22515 Reviewed-by: Christopher Cain <cjcain@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
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