summaryrefslogtreecommitdiffstats
path: root/src/occ_405/incl
Commit message (Collapse)AuthorAgeFilesLines
* OCC: Call Home Data LogAndres Lugo-Reyes2017-12-181-0/+7
| | | | | | | | | | | | | | | | | | -CPU temp PER proc -DIMM Temp changes -Memory Bandwidth changes -VRM VDD -Error History counts Change-Id: Ie30f373982a5f3327975d433d508ad2fb27f4fc3 RTC:133944 CMVC-Prereq: 1040415 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49395 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
* Remove interrupt handlers for hardware errorsChris Cain2017-11-081-2/+0
| | | | | | | | | | | | Errors will be detected by the PGPE beacon. Change-Id: I2d24ec9becc319a1cf1fce6b06714ac638faade1 RTC: 134619 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/49421 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
* IPL Time Checkstop Analysis Part 3: OCC bootloader and mainIlya Smirnov2017-08-211-1/+17
| | | | | | | | | | Change-Id: Id4d050f1d78a1921afc839c8b2b382961def64f0 RTC:155065 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/43938 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William G. Hoffa <wghoffa@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Initial 405 GPU supportmbroyles2017-08-142-1/+9
| | | | | | | Change-Id: I6e957ca1aa643d257274e99957df5b15ac8c889b Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44254 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* PGPE init updatesChris Cain2017-04-131-2/+5
| | | | | | | | | | Change-Id: I0140184371619983fb38b27199f241efe7f30f16 RTC: 169886 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/37770 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
* Pstates Support in OCCWael El-Essawy2017-01-272-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Initialize Pstates global parameters (G_proc_fmax, G_proc_fmin, G_khz_per_pstate and G_proc_pmin from the OCC Pstate Parameter Block) 2. When frequency config data packet is received and OCC is NOT already in Active state: Send IPC command to PGPE to set pState clips to be wide open from min frequency to turbo First verify min/max frequency from TMGT is within what PGPE allows saved in G_proc_fmax and G_proc_fmin if not within bounds trace and clip to G_proc_fmax/fmin) 3. Transition to active state: Send IPC command to PGPE to start pState protocol (give correct data for OCC vs OPAL in control of Pstates) and if OPAL system update OPAL shared memory with Pstate information. 4. amec_slv_freq_smh(): Send IPC command to PGPE to set requested pState (PowerVM) or set clips (OPAL). 5. Address all the TODO/TEMP/#if 0 in amec_freq.c either remove or add RTC# for when it will be addressed Change-Id: Ic323321b8c66945732a6b7345ad85d6f41a62edd RTC: 130201 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33704 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Initial Wof commitAndres Lugo-Reyes2017-01-061-1/+5
| | | | | | | | | | | Contains initial WOF directory structure Change-Id: I24ec77ca11dc711ff44c0b378f64d96696838ee1 RTC:130216 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34298 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Open linear window for SRAM access on OCB channel 2 for secure modeChris Cain2016-11-161-0/+1
| | | | | | | | | | | | Also enabled call home logs and some debug commands Change-Id: Ieac936fd1b259b0165e54ab98e05899e0d2b6912 CQ: SW371042 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/32602 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
* Implement task_poke_watchdogsWael El-Essawy2016-11-031-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | task_poke_watchdogs() should be called every 2ms (ticks 1 and 9) on both master and slaves while in observation and active state and do the following: 1. Every time called: Enable/Reset the OCC heartbeat: done by a write to OCB OCC Heartbeat Register (set count to 8ms) 2. Every time called: Reset memory deadman timer for 1 MCA (skip if not present and just wait until next call to check next MCA to keep same timing of reset per MCA regardless of # present) Resetting the deadman is done by reading one of the memory performance counters, use one at SCOM offset 0x13C. NOTE: Will take 16ms (8 MCAs x 2ms) to reset all memory timers, this is fine since the shortest time the deadman timeout can be configured to is 28ms 3. Every 4ms (on tick 1 only) : Verify PGPE is still functional by reading PGPE Beacon from SRAM if after 8ms (2 consecutive checks) there is no change to the PGPE Beacon count then log an error and request reset. In addition, this commit adds entries for the PGPE image header and shared SRAM in the TLB, and partially reads PGPE image header parameters. Change-Id: I9906102b3349506612d55c57e9f5c28441eaeb39 RTC: 154960 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/31916 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Collect Nest DTS AverageWilliam Bryan2016-09-291-0/+1
| | | | | | | | | | RTC:133842 Change-Id: I565a6f2e848652b7eddd3b319f9c3a411913074a Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29804 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Memory Temperature Control Loop (memory throttling)Wael El-Essawy2016-09-161-0/+3
| | | | | | | | | | | | * Memory throttling due to over temp * Throttle when reach timeout getting new temperature readings * Log error for temperature exceeding ERROR threshold Change-Id: I089c88aadba84e7296ad87b8cb87fa8c045ff912 RTC: 131188 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28933 Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Tested-by: Wael El-Essawy <welessa@us.ibm.com>
* Linker script cleanupWilliam Bryan2016-09-011-2/+4
| | | | | | | | | | RTC:134263 Change-Id: I943493f7855ae002dbba929494d8bed85bbe2596 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/29046 Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
* Checkpoint improvementsChris Cain2016-08-251-1/+10
| | | | | | | | | Change-Id: I08d76ac1db6e425a9690864f693f36cb848cead5 RTC: 153965 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/28188 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Build full OCC image and update build processWilliam Bryan2016-05-041-15/+21
| | | | | | | | Change-Id: I8e6d716a48f30021b653e850c74deb7526cfe293 RTC:133001 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/22155 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Change attention type default to FSPWael El-Essawy2016-05-031-3/+0
| | | | | | | | | Change-Id: I6661e64e2bb29762ba038bddcebd9e6b4afcf85e RTC: 147814 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23618 Tested-by: FSP CI Jenkins Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
* Implement code to read DIMM temperaturesChris Cain2016-01-271-0/+4
| | | | | | | | | | Change-Id: I98fc83ab1c78bd40241fe6e47a9ddeae24f78c38 RTC: 140093 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22770 Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher Cain <cjcain@us.ibm.com>
* Enabled reading CCSR via OCIWilliam Bryan2016-01-151-5/+5
| | | | | | | | | RTC: 140187 Change-Id: I3ad92658c18e76f58b3e7c9733e97cff437c7cdc Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22581 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
* Enable system config command and sensor listWilliam Bryan2015-12-101-1/+1
| | | | | | | | | | | Added configuration data debug command RTC: 141643 Change-Id: I3d98321508780c25795d66a8d353c36593448a6e Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22549 Tested-by: FSP CI Jenkins Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
* OCC GPE0: Core Data Collection infrastructure in GPE0Wael El-Essawy2015-11-231-7/+1
| | | | | | | | | | | | Create IPC function for core data collection return dummy data at this point to allow 405 to schedule and "use" data back. Change-Id: I520e9333fa25e37127d6af693ad6f21da3431939 RTC: 131183 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22247 Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com> Tested-by: Fadi Kassem <fmkassem@us.ibm.com>
* Core data initialization and 24-core supportWilliam Bryan2015-11-201-1/+17
| | | | | | | | | | RTC: 140187 RTC: 140186 Change-Id: I574acdc3933b4bc181a584226ea432b9abe72592 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/22182 Reviewed-by: Wael Elessawy <welessa@us.ibm.com> Tested-by: Fadi Kassem <fmkassem@us.ibm.com> Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com>
* Fixed warnings and added -Werror CFLAGWilliam Bryan2015-11-021-4/+4
| | | | | | | | | | Fixed adding traces in error handling code RTC: 137993 Change-Id: Ifc48da76bf2af90435b708c3415b5f456957911b Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21097 Tested-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
* Remove applet supportWilliam Bryan2015-10-271-4/+0
| | | | | | | | | | | | | | 1. Removed most files related to applets 2. Converted sensor query list and command handler debug applets to functions. 3. Removed #includes of applet header files Change-Id: I410b3c68991e4fa6a7f542e5ee346a3d313f2a94 RTC: 137992 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/21030 Tested-by: FSP CI Jenkins Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com> Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
* Start GPE0 and schedule APSS read tasksmbroyles2015-08-101-0/+2
| | | | | | | | Change-Id: I045a6b32bbbb4944ba766cde17f0ce9645f879e6 Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19693 Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: FSP CI Jenkins
* new ssx and lib filesWilliam Bryan2015-08-033-0/+584
Change-Id: I2328b1e86d59e3788910687d762fb70ec680058f Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19503 Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
OpenPOWER on IntegriCloud