new ssx and lib files

Change-Id: I2328b1e86d59e3788910687d762fb70ec680058f
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/19503
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Tested-by: William A. Bryan <wilbryan@us.ibm.com>

3 files changed, 584 insertions, 0 deletions

diff --git a/src/occ_405/incl/common_types.h b/src/occ_405/incl/common_types.h
new file mode 100755
index 0000000..51ea3ed
--- /dev/null
+++ b/src/occ_405/incl/common_types.h
@@ -0,0 +1,184 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/occ/incl/common_types.h $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef _COMMON_TYPES_H
+#define _COMMON_TYPES_H
+
+#include <stdint.h>
+
+#ifdef USE_SSX_APP_CFG_H
+#include <ssx_app_cfg.h>
+#endif
+
+typedef uint32_t      UINT32;
+typedef int32_t       INT32;
+typedef uint8_t       UCHAR;
+typedef uint8_t       UINT8;
+typedef int8_t        INT8;
+typedef uint16_t      UINT16;
+typedef int16_t       INT16;
+typedef char          CHAR;
+typedef unsigned int  UINT;
+typedef unsigned long ULONG;
+typedef int           INT;
+typedef void          VOID;
+
+// Skip this typedef in x86 environment
+#ifndef OCC_X86_PARSER
+typedef uint8_t       bool;
+#endif
+
+// Definition of FALSE and TRUE
+#if !defined(FALSE) && !defined(TRUE)
+typedef enum
+{
+    FALSE = 0,
+    TRUE
+} BOOLEAN;
+#endif
+
+#define true 1
+#define false 0
+
+#ifndef NULL
+#define NULL                 (VOID *) 0
+#endif
+
+#define MAIN_APP_ID         "Main App Image\0"
+
+#define SRAM_REPAIR_RESERVE_SZ  64
+#define IMAGE_ID_STR_SZ         16
+#define RESERVED_SZ             14
+#define TRAP_INST               0x7FE00004
+#define ID_NUM_INVALID          0xFFFF
+
+// Magic number set for applet headers
+#define APLT_MAGIC_NUMBER {0x1A,0x2B,0x3C,0x4D, 0x5E,0x6F,0x7A,0x8B, 0x9C,0xAD,0xAE,0x9F, 0x8A,0x7B,0x6C,0x5D, 0x4E,0x3F,0x2A,0x1B,\
+                           0x1A,0x2B,0x3C,0x4D, 0x5E,0x6F,0x7A,0x8B, 0x9C,0xAD,0xAE,0x9F, 0x8A,0x7B,0x6C,0x5D, 0x4E,0x3F,0x2A,0x1B,\
+                           0x1A,0x2B,0x3C,0x4D, 0x5E,0x6F,0x7A,0x8B, 0x9C,0xAD,0xAE,0x9F, 0x8A,0x7B,0x6C,0x5D, 0x4E,0x3F,0x2A,0x1B, 0x12,0x34,0xAB,0xCD}
+#define SRAM_HEADER_HACK   0x48000042
+#ifndef __ASSEMBLER__
+
+// Structure for the common image header
+struct image_header
+{
+    // Overload sram_repair_reserved for magic applet number
+    // Note: unit64_t's don't compile when used w/IMAGE_HEADER macro.
+    union
+    {
+        struct
+        {
+            uint32_t magic_1;  // 0x1A2B3C4D
+            uint32_t magic_2;  // 0x5E6F7A8B
+            uint32_t magic_3;  // 0x9CADAE9F
+            uint32_t magic_4;  // 0x8A7B6C5D
+            uint32_t magic_5;  // 0x4E3F2A1B
+            uint32_t magic_6;  // 0x1A2B3C4D
+            uint32_t magic_7;  // 0x5E6F7A8B
+            uint32_t magic_8;  // 0x9CADAE9F
+            uint32_t magic_9;  // 0x8A7B6C5D
+            uint32_t magic_a;  // 0x4E3F2A1B
+            uint32_t magic_b;  // 0x1A2B3C4D
+            uint32_t magic_c;  // 0x5E6F7A8B
+            uint32_t magic_d;  // 0x9CADAE9F
+            uint32_t magic_e;  // 0x8A7B6C5D
+            uint32_t magic_f;  // 0x4E3F2A1B
+            uint32_t magic_10; // 0x1234ABCD
+        };
+        uint8_t sram_repair_reserved[SRAM_REPAIR_RESERVE_SZ]; //reserved for HW use
+    };
+
+    uint32_t ep_branch_inst;            // entry point branch instruction for bootloader
+    uint32_t halt_inst;                 // halt instruction
+    uint32_t image_size;                // image size including header
+    uint32_t start_addr;                // image start address including header
+    uint32_t readonly_size;             // readonly image size
+    uint32_t boot_writeable_addr;       // boot writeable address
+    uint32_t boot_writeable_size;       // boot writeable size
+    uint32_t zero_data_addr;            // zero data address
+    uint32_t zero_data_size;            // zero data size
+    uint32_t ep_addr;                   // entry point to the image
+    uint32_t checksum;                  // checksum of the image including header
+    uint32_t version;                   // image version
+    char image_id_str[IMAGE_ID_STR_SZ]; // image id string
+    uint16_t aplt_id;                   // type: enum OCC_APLT
+    uint8_t reserved[RESERVED_SZ];      // reserved for future use
+} __attribute__ ((__packed__));
+
+typedef struct image_header imageHdr_t;
+
+extern uint32_t __READ_ONLY_DATA_LEN__;
+extern uint32_t __WRITEABLE_DATA_ADDR__;
+extern uint32_t __WRITEABLE_DATA_LEN__;
+extern uint32_t __START_ADDR__;
+
+
+// Macro for creating common image header
+// NOTE: ep_branch_inst is defaulted to trap instruction. Script to fix
+// header will change it to branch to address in ep_addr field.
+#define IMAGE_HEADER(nameStr, epAddr, IdStr, IdNum) \
+const volatile imageHdr_t nameStr  __attribute__((section("imageHeader")))= \
+{ \
+    /* sram_repair_reserved values should match APLT_MAGIC_NUMBER for an applet; 0 otherwise */ \
+    { \
+        { \
+            .magic_1 = (IdNum == ID_NUM_INVALID)?0:0x1A2B3C4D, \
+            .magic_2 = (IdNum == ID_NUM_INVALID)?0:0x5E6F7A8B, \
+            .magic_3 = (IdNum == ID_NUM_INVALID)?0:0x9CADAE9F, \
+            .magic_4 = (IdNum == ID_NUM_INVALID)?0:0x8A7B6C5D, \
+            .magic_5 = (IdNum == ID_NUM_INVALID)? SRAM_HEADER_HACK:0x4E3F2A1B, \
+            .magic_6 = (IdNum == ID_NUM_INVALID)?0:0x1A2B3C4D, \
+            .magic_7 = (IdNum == ID_NUM_INVALID)?0:0x5E6F7A8B, \
+            .magic_8 = (IdNum == ID_NUM_INVALID)?0:0x9CADAE9F, \
+            .magic_9 = (IdNum == ID_NUM_INVALID)?0:0x8A7B6C5D, \
+            .magic_a = (IdNum == ID_NUM_INVALID)?0:0x4E3F2A1B, \
+            .magic_b = (IdNum == ID_NUM_INVALID)?0:0x1A2B3C4D, \
+            .magic_c = (IdNum == ID_NUM_INVALID)?0:0x5E6F7A8B, \
+            .magic_d = (IdNum == ID_NUM_INVALID)?0:0x9CADAE9F, \
+            .magic_e = (IdNum == ID_NUM_INVALID)?0:0x8A7B6C5D, \
+            .magic_f = (IdNum == ID_NUM_INVALID)?0:0x4E3F2A1B, \
+            .magic_10 = (IdNum == ID_NUM_INVALID)?0:0x1234ABCD, \
+        } \
+    }, \
+    TRAP_INST,                          /* ep_branch_Inst */ \
+    TRAP_INST,                          /* halt_inst */ \
+    0,                                  /* image_size (filled in later by imageHdrScript) */ \
+    (uint32_t)&__START_ADDR__,          /* start_addr */ \
+    (uint32_t)&__READ_ONLY_DATA_LEN__,  /* readonly_size */ \
+    (uint32_t)&__WRITEABLE_DATA_ADDR__, /* boot_writeable_addr */ \
+    (uint32_t)&__WRITEABLE_DATA_LEN__,  /* boot_writeable_size */ \
+    0,                                  /* zero_data_addr (currently unused) */ \
+    0,                                  /* zero data_size (currently unused) */ \
+    (uint32_t)&epAddr,                  /* ep_addr */ \
+    0,                                  /* checksum (calculated later by imsageHdrScript) */ \
+    0,                                  /* version (filled in later by imageHdrScript) */ \
+    IdStr,                              /* image_id_str */ \
+    (uint16_t)IdNum,                    /* aplt_id */ \
+    {0}                                 /* reserved */ \
+};
+
+#endif  /* __ASSEMBLER__ */
+
+#endif //_COMMON_TYPES_H
diff --git a/src/occ_405/incl/comp_ids.h b/src/occ_405/incl/comp_ids.h
new file mode 100755
index 0000000..fb6f5d5
--- /dev/null
+++ b/src/occ_405/incl/comp_ids.h
@@ -0,0 +1,84 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/occ_405/incl/comp_ids.h $                                 */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+//Note: Be sure to mirror changes in this file to occ/plugins/tmgtTpmdCompIds.H!!!
+// If you don't, the ERRL plugin will eventually break, and you might break the
+// fips build for TMGT.
+
+#ifndef _COMP_IDS_H
+#define _COMP_IDS_H
+
+#define COMP_NAME_SIZE       4
+
+#define MAIN_COMP_ID         0x0100
+#define MAIN_COMP_NAME       "MAIN"
+
+
+#define ERRL_COMP_ID         0x0200
+#define ERRL_COMP_NAME       "ERRL"
+
+#define TRAC_COMP_ID         0x0300
+#define TRAC_COMP_NAME       "TRAC"
+
+#define RTLS_COMP_ID         0x0400
+#define RTLS_COMP_NAME       "RTLS"
+
+#define THRD_COMP_ID         0x0500
+#define THRD_COMP_NAME       "THRD"
+
+#define SNSR_COMP_ID         0x0600
+#define SNSR_COMP_NAME       "SNSR"
+
+// Applet Manager
+#define APLT_COMP_ID         0x0700
+#define APLT_COMP_NAME       "APLT"
+
+#define PSS_COMP_ID          0x0800
+#define PSS_COMP_NAME        "PSS"
+
+#define TMER_COMP_ID         0x0900
+#define TMER_COMP_NAME       "TMER"
+
+#define DCOM_COMP_ID         0x0A00
+#define DCOM_COMP_NAME       "DCOM"
+
+// Proc data
+#define PROC_COMP_ID         0x0B00
+#define PROC_COMP_NAME       "PROC"
+
+// Amec data
+#define AMEC_COMP_ID         0x0C00
+#define AMEC_COMP_NAME       "AMEC"
+
+// Centaur data
+#define CENT_COMP_ID         0x0D00
+#define CENT_COMP_NAME       "CENT"
+
+// Command Handler
+#define CMDH_COMP_ID         0x0E00
+#define CMDH_COMP_NAME       "CMDH"
+
+#endif
+
diff --git a/src/occ_405/incl/occ_common.h b/src/occ_405/incl/occ_common.h
new file mode 100755
index 0000000..032683f
--- /dev/null
+++ b/src/occ_405/incl/occ_common.h
@@ -0,0 +1,316 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/occ/incl/occ_common.h $                                   */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef _OCC_COMMON_H
+#define _OCC_COMMON_H
+
+#include <common_types.h>
+#include <comp_ids.h>
+
+// From Linker Script
+extern void _LINEAR_WR_WINDOW_SECTION_BASE;
+extern void _LINEAR_WR_WINDOW_SECTION_SIZE;
+extern void _LINEAR_RD_WINDOW_SECTION_BASE;
+extern void _LINEAR_RD_WINDOW_SECTION_SIZE;
+extern void _FIR_PARMS_SECTION_BASE;
+extern void _FIR_HEAP_SECTION_BASE;
+
+// Declare aligned data structures for Async access in a noncacheable section
+//
+// These macros declare aligned data structures in a noncacheable section, with
+// the alignment that is needed by the specified device driver (or more
+// accurately, as specified by the hardware device itself.)
+//
+// All buffers should be initialized - an initialization declaration using
+// these macros would look as follows:
+//    Example:  DMA_BUFFER(uint8_t g_bcue_test[1024]) = {0};
+//
+#define PBAX_BUFFER(declaration) \
+        declaration __attribute__ ((__aligned__ (8))) __attribute__ ((section (".noncacheable")))
+
+#define OCB_BUFFER(declaration) \
+        declaration __attribute__ ((__aligned__ (8))) __attribute__ ((section (".noncacheable")))
+
+#define DMA_BUFFER(declaration) \
+        declaration __attribute__ ((__aligned__ (128))) __attribute__ ((section (".noncacheable")))
+
+#define GPE_BUFFER(declaration) \
+        declaration __attribute__ ((__aligned__ (8))) __attribute__ ((section (".noncacheable")))
+
+#define FIR_HEAP_BUFFER(declaration) \
+        declaration __attribute__ ((section (".firHeap")))
+
+#define FIR_PARMS_BUFFER(declaration) \
+        declaration __attribute__ ((section (".firParms")))
+
+#define LINEAR_WINDOW_WR_BUFFER(declaration) \
+        declaration __attribute__ ((section (".linear_wr")))
+
+#define LINEAR_WINDOW_RD_BUFFER(declaration) \
+        declaration __attribute__ ((section (".linear_rd")))
+
+#define PSTATE_TABLE(declaration) \
+        declaration __attribute__ ((__aligned__ (1024)))
+
+// Pinned in linker file as address for TMGT cmds to be sent/received
+#define CMDH_LINEAR_WINDOW_BASE_ADDRESS ((uint32_t) &_LINEAR_WR_WINDOW_SECTION_BASE)
+#define LINEAR_WR_WINDOW_SECTION_SIZE   ((uint32_t) &_LINEAR_WR_WINDOW_SECTION_SIZE)
+#define CMDH_OCC_RESPONSE_BASE_ADDRESS  ((uint32_t) &_LINEAR_RD_WINDOW_SECTION_BASE)
+#define LINEAR_RD_WINDOW_SECTION_SIZE   ((uint32_t) &_LINEAR_RD_WINDOW_SECTION_SIZE)
+#define FIR_PARMS_SECTION_BASE_ADDRESS  ((uint32_t) &_FIR_PARMS_SECTION_BASE)
+#define FIR_HEAP_SECTION_BASE_ADDRESS   ((uint32_t) &_FIR_HEAP_SECTION_BASE)
+
+
+// Conversion Macro's
+
+// Get byte 0-1 of uint64
+#define     CONVERT_UINT64_UINT16_UPPER(a) \
+            ((UINT16)((a>>48) & 0xFFFF))
+// Get byte 2-3 of uint64
+#define     CONVERT_UINT64_UINT16_MIDUPPER(a) \
+            ((UINT16)((a>>32) & 0xFFFF))
+// Get byte 4-5 of uint64
+#define     CONVERT_UINT64_UINT16_MIDLOWER(a) \
+            ((UINT16)((a>>16) & 0xFFFF))
+// Get byte 6-7 of uint64
+#define     CONVERT_UINT64_UINT16_LOWER(a) \
+            ((UINT16)((a>>0) & 0xFFFF))
+
+
+// Get byte 0 of uint32
+#define     CONVERT_UINT32_UINT8_UPPER_HIGH(a) \
+            ((UINT8)((a>>24) & 0xFF))
+// Get byte 1 of uint32
+#define     CONVERT_UINT32_UINT8_UPPER_LOW(a) \
+            ((UINT8)((a>>16) & 0xFF))
+// Get byte 2 of uint32
+#define     CONVERT_UINT32_UINT8_LOWER_HIGH(a) \
+            ((UINT8)((a>>8) & 0xFF))
+// Get byte 3 of uint32
+#define     CONVERT_UINT32_UINT8_LOWER_LOW(a) \
+            ((UINT8)((a>>0) & 0xFF))
+
+
+// Get byte 0-1 of uint32
+#define     CONVERT_UINT32_UINT16_UPPER(a) \
+            ((UINT16)((a>>16) & 0xFFFF))
+// Get byte 1-2 of uint32
+#define     CONVERT_UINT32_UINT16_MIDDLE(a) \
+            ((UINT16)((a>>8) & 0xFFFF))
+// Get byte 2-3 of uint32
+#define     CONVERT_UINT32_UINT16_LOWER(a) \
+            ((UINT16)((a>>0) & 0xFFFF))
+
+// Get high byte of uint16
+#define     CONVERT_UINT16_UINT8_HIGH(a) \
+            ((UINT8)((a>>8) & 0xFF))
+// Get low byte of uint16
+#define     CONVERT_UINT16_UINT8_LOW(a) \
+            ((UINT8)(a & 0x00FF))
+
+
+// Get high nybble of uint8
+#define     CONVERT_UINT8_UINT4_HIGH(a) \
+            ((UINT8)((a>>4) & 0x0F))
+// Get low nybble of uint8
+#define     CONVERT_UINT8_UINT4_LOW(a) \
+            ((UINT8)(a & 0x0F))
+
+// Convert a two byte uint8 to a uint16
+// Always cast LSB to UINT8 to assure this also works with INT's
+#define     CONVERT_UINT8_ARRAY_UINT16(a,b) \
+            ((a<<8) | ((UINT8)b))
+
+// Convert a 4 byte uint8 to a uint32
+#define     CONVERT_UINT8_ARRAY_UINT32(a,b,c,d) \
+            ((((UINT32)a)<<24) | (((UINT32)b)<<16) | (((UINT32)c)<<8) | (((UINT32)d)))
+
+
+// Bit Operation Macros
+#define SETBIT(var,bit)   ((var) |= (1<<(bit)))
+#define CLEARBIT(var,bit) ((var) &= ~(1<<(bit)))
+
+#define WORDALIGN(n) \
+        ((n + 3) & ~3)
+
+// CHECKPOINT macros revamped a little to allow a little more reuse with
+// new return codes ('Ex'h).  Note that there is a special case version of this
+// code in ll_ffdc.S designed solely for writing an FFDC header in the SSX_PANIC
+// path.
+#define __CHECKPOINT(_flg, _ckp, _rc)                                          \
+{                                                                              \
+    G_fsp_msg.rsp->fields.seq = 0;                                             \
+    G_fsp_msg.rsp->fields.cmd_type = 0;                                        \
+    G_fsp_msg.rsp->fields.rc = _rc;                                            \
+    G_fsp_msg.rsp->fields.data_length[0] = 0;                                  \
+    G_fsp_msg.rsp->fields.data_length[1] = 3;                                  \
+    G_fsp_msg.rsp->fields.data[0] = _flg;                                      \
+    G_fsp_msg.rsp->fields.data[1] = (uint8_t)(_ckp >> 8);                      \
+    G_fsp_msg.rsp->fields.data[2] = (uint8_t)_ckp;                             \
+    dcache_flush_line((void *)CMDH_OCC_RESPONSE_BASE_ADDRESS);                 \
+}
+
+// This macro should only be used in the initialization path leading
+// up to being able to communicate with the FSP.  After that, the
+// response buffer is used for responses and must not be used for
+// checkpointing unless the OCC is about to halt.
+#define CHECKPOINT_INIT()                                                      \
+{                                                                              \
+    __CHECKPOINT(0x00, 0x0000, ERRL_RC_INIT_CHCKPNT);                          \
+}
+
+// In case we are not able to reach a state where OCC can receive
+// commands from the FSP.  Place a checkpoint value in the response
+// buffer with the return code of the response set to ERRL_RC_INIT_CHCKPNT.
+// Then, if OCC doesn't respond to an FSP command, the FSP will see
+// ERRL_RC_INIT_CHCKPNT and log the checkpoint in a special error log.
+#define CHECKPOINT(_ckp)                                                       \
+{                                                                              \
+    __CHECKPOINT(G_fsp_msg.rsp->fields.data[0], _ckp, ERRL_RC_INIT_CHCKPNT);   \
+}
+
+// Special purpose flags to be used at programmer's discretion
+#define CHECKPOINT_FLAG(_flg)  \
+{                                                                              \
+    G_fsp_msg.rsp->fields.data[0] |= _flg;                                     \
+    __CHECKPOINT(_flg, (G_fsp_msg.rsp->fields.data[1] << 8 | G_fsp_msg.rsp->fields.data[2]), G_fsp_msg.rsp->fields.rc);\
+}
+
+// A new OCC_HALT macro much like SSX_PANIC but for OCC code use.  The
+// ex_code parm is placed in the exception code of the FFDC header as opposed to
+// SSX_PANIC which sets the panic code.  OCC_HALT sets the panic code to 0 to
+// differentiate this halt from SSX initiated halts.  This macro mirrors what
+// SSX_PANIC does except it calls a different function for saving the FFDC.
+// This macro will not return to the caller.  There is also an assembly version
+// if needed.
+#ifndef __ASSEMBLER__
+#define OCC_HALT(ex_code)                                                      \
+do {                                                                           \
+    barrier();                                                                 \
+    asm volatile ("stw  %r3, __occ_panic_save_r3@sda21(0)");                   \
+    asm volatile ("mflr %r3");                                                 \
+    asm volatile ("stw  %r4, __occ_panic_save_r4@sda21(0)");                   \
+    asm volatile ("lis  %%r4, %0"::"i" (ex_code >> 16));                       \
+    asm volatile ("ori  %%r4, %%r4, %0"::"i" (ex_code & 0xffff));              \
+    asm volatile ("bl   __occ_checkpoint_panic_and_save_ffdc");                \
+    asm volatile ("trap");                                                     \
+    asm volatile (".long %0" : : "i" (ex_code));                               \
+} while (0)
+#else  /* __ASSEMBLER__ */
+#define OCC_HALT(ex_code) _occ_halt ex_code
+    .macro  _occ_halt, ex_code
+    stw     %r3, __occ_panic_save_r3@sda21(0)
+    mflr    %r3
+    stw     %r4, __occ_panic_save_r4@sda21(0)
+    lis     %r4, \ex_code@h
+    ori     %r4, %r4, \ex_code@l
+    bl      __occ_checkpoint_panic_and_save_ffdc
+    trap
+    .long   \ex_code
+    .endm
+#endif /* __ASSEMBLER__ */
+
+// Unique checkpoints
+enum
+{
+    MAIN_STARTED                = 0x01ff,
+    SSX_STARTING                = 0x0210,
+    SSX_INITIALIZED             = 0x02ff,
+    TRACE_INITIALIZED           = 0x0310,
+    HOMER_ACCESS_INITS          = 0x0318,
+    INITIALIZING_IRQS           = 0x0320,
+    IRQS_INITIALIZED            = 0x032f,
+    MAIN_THREAD_STARTED         = 0x03ff,
+    ROLES_INITIALIZED           = 0x04ff,
+    SENSORS_INITIALIZED         = 0x05ff,
+    PROC_CORE_INITIALIZED       = 0x06ff,
+    CENTAUR_INITIALIZED         = 0x07ff,
+    SLAVE_OCC_INITIALIZED       = 0x08ff,
+    WATCHDOG_INITIALIZED        = 0x09ff,
+    RTL_TIMER_INITIALIZED       = 0x0aff,
+    SEMS_AND_TIMERS_INITIALIZED = 0x0bff,
+    APP_SEMS_CREATED            = 0x0c10,
+    APP_MEM_MAPPED              = 0x0c20,
+    APP_ADDR_INITIALIZED        = 0x0c30,
+    APP_MEM_UNMAP               = 0x0c40,
+    APPLETS_INITIALIZED         = 0x0cff,
+    CMDH_THREAD_STARTED         = 0x0dff,
+    INIT_OCB                    = 0x0e05,
+    OCB_INITIALIZED             = 0x0e07,
+    INIT_FSI_HOST_MBOX          = 0x0e10,
+    FSI_HOST_MBOX_INITIALIZED   = 0x0e20,
+    FSP_COMM_INITIALIZED        = 0x0eff,
+    ABOUT_TO_HALT               = 0x0f00,
+    FIRST_FSP_ATTN_SENT         = 0xffff,
+};
+
+// Checkpoint flags (one byte bitmap)
+enum
+{
+    CF_FSI_MB_TIMEOUT           = 0x01,
+};
+
+#define DEFAULT_TRACE_SIZE 1536
+#define MAX_OCCS       8
+#define MAX_CORES      12
+
+//Used by G_occ_interrupt_type to distinguish between FSP supported OCCs and other servers.
+#define FSP_SUPPORTED_OCC 0x00
+#define PSIHB_INTERRUPT   0x01
+
+// TRAP instruction should also set FIR bits along with halting PPC405
+// Set DBCR0 to initial value (setting external debug event) so that
+// trap call also sets FIR bits and also does not invoke program interrupt.
+#define HALT_WITH_FIR_SET  mtspr(SPRN_DBCR0,PPC405_DBCR0_INITIAL);       \
+                           asm volatile("trap")
+
+// Static Assert Macro for Compile time assertions.
+//   - This macro can be used both inside and outside of a function.
+//   - A value of true will cause the ASSERT to produce this error
+//   - This will show up on a compile fail as:
+//      <file>:<line> error: size of array '_static_assert' is negative
+//   - It would be trivial to use the macro to paste a more descriptive
+//     array name for each assert, but we will leave it like this for now.
+#define STATIC_ASSERT(cond) extern uint8_t _static_assert[cond ? -1 : 1]  __attribute__ ((unused));
+
+// Convert duration based in SsxTimestamps to microseconds.
+#define DURATION_IN_US_UNTIL_NOW_FROM(start_time) \
+  (uint32_t) ((ssx_timebase_get() - (SsxTimebase) start_time) / ( SSX_TIMEBASE_FREQUENCY_HZ / 1000000 ))
+
+// Convert duration based in SsxTimestamps to milliseconds.
+#define DURATION_IN_MS_UNTIL_NOW_FROM(start_time) \
+  (uint32_t) ((ssx_timebase_get() - (SsxTimebase) start_time) / ( SSX_TIMEBASE_FREQUENCY_HZ / 1000 ))
+
+// Skip this typedef in x86 environment
+#ifndef OCC_X86_PARSER
+typedef uint32_t      size_t ;
+#endif
+
+extern const char G_occ_buildname[16];
+
+int memcmp ( const void * ptr1, const void * ptr2, size_t num );
+
+#endif //_OCC_COMMON_H
+