diff options
Diffstat (limited to 'src/ssx/pgp/registers')
38 files changed, 19481 insertions, 0 deletions
diff --git a/src/ssx/pgp/registers/centaur_firmware_registers.h b/src/ssx/pgp/registers/centaur_firmware_registers.h new file mode 100755 index 0000000..39f168f --- /dev/null +++ b/src/ssx/pgp/registers/centaur_firmware_registers.h @@ -0,0 +1,1496 @@ +#ifndef __CENTAUR_FIRMWARE_REGISTERS_H__ +#define __CENTAUR_FIRMWARE_REGISTERS_H__ + +// $Id: centaur_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/centaur_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file centaur_firmware_registers.h +/// \brief C register structs for the CENTAUR unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union centaur_device_id { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t cfam_id : 32; + uint64_t module_id : 2; + uint64_t _reserved0 : 30; +#else + uint64_t _reserved0 : 30; + uint64_t module_id : 2; + uint64_t cfam_id : 32; +#endif // _BIG_ENDIAN + } fields; +} centaur_device_id_t; + + + +typedef union centaur_mbs_fir_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t host_protocol_error : 1; + uint64_t int_protocol_error : 1; + uint64_t invalid_address_error : 1; + uint64_t external_timeout : 1; + uint64_t internal_timeout : 1; + uint64_t int_buffer_ce : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_parity_error : 1; + uint64_t cache_srw_ce : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_sue : 1; + uint64_t dir_ce : 1; + uint64_t dir_ue : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t lru_error : 1; + uint64_t edram_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t host_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t occ_inband_write_error : 1; + uint64_t srb_buffer_ce : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_sue : 1; + uint64_t dir_purge_ce : 1; + uint64_t spare_fir30 : 1; + uint64_t spare_fir31 : 1; + uint64_t internal_scom_error : 1; + uint64_t internal_scom_error_copy : 1; + uint64_t _reserved0 : 30; +#else + uint64_t _reserved0 : 30; + uint64_t internal_scom_error_copy : 1; + uint64_t internal_scom_error : 1; + uint64_t spare_fir31 : 1; + uint64_t spare_fir30 : 1; + uint64_t dir_purge_ce : 1; + uint64_t srb_buffer_sue : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_ce : 1; + uint64_t occ_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t host_inband_read_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t edram_error : 1; + uint64_t lru_error : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_ue : 1; + uint64_t dir_ce : 1; + uint64_t cache_co_sue : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_ce : 1; + uint64_t int_parity_error : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_ce : 1; + uint64_t internal_timeout : 1; + uint64_t external_timeout : 1; + uint64_t invalid_address_error : 1; + uint64_t int_protocol_error : 1; + uint64_t host_protocol_error : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbs_fir_reg_t; + + + +typedef union centaur_mbs_fir_reg_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t host_protocol_error : 1; + uint64_t int_protocol_error : 1; + uint64_t invalid_address_error : 1; + uint64_t external_timeout : 1; + uint64_t internal_timeout : 1; + uint64_t int_buffer_ce : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_parity_error : 1; + uint64_t cache_srw_ce : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_sue : 1; + uint64_t dir_ce : 1; + uint64_t dir_ue : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t lru_error : 1; + uint64_t edram_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t host_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t occ_inband_write_error : 1; + uint64_t srb_buffer_ce : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_sue : 1; + uint64_t dir_purge_ce : 1; + uint64_t spare_fir30 : 1; + uint64_t spare_fir31 : 1; + uint64_t internal_scom_error : 1; + uint64_t internal_scom_error_copy : 1; + uint64_t _reserved0 : 30; +#else + uint64_t _reserved0 : 30; + uint64_t internal_scom_error_copy : 1; + uint64_t internal_scom_error : 1; + uint64_t spare_fir31 : 1; + uint64_t spare_fir30 : 1; + uint64_t dir_purge_ce : 1; + uint64_t srb_buffer_sue : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_ce : 1; + uint64_t occ_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t host_inband_read_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t edram_error : 1; + uint64_t lru_error : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_ue : 1; + uint64_t dir_ce : 1; + uint64_t cache_co_sue : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_ce : 1; + uint64_t int_parity_error : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_ce : 1; + uint64_t internal_timeout : 1; + uint64_t external_timeout : 1; + uint64_t invalid_address_error : 1; + uint64_t int_protocol_error : 1; + uint64_t host_protocol_error : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbs_fir_reg_and_t; + + + +typedef union centaur_mbs_fir_reg_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t host_protocol_error : 1; + uint64_t int_protocol_error : 1; + uint64_t invalid_address_error : 1; + uint64_t external_timeout : 1; + uint64_t internal_timeout : 1; + uint64_t int_buffer_ce : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_parity_error : 1; + uint64_t cache_srw_ce : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_sue : 1; + uint64_t dir_ce : 1; + uint64_t dir_ue : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t lru_error : 1; + uint64_t edram_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t host_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t occ_inband_write_error : 1; + uint64_t srb_buffer_ce : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_sue : 1; + uint64_t dir_purge_ce : 1; + uint64_t spare_fir30 : 1; + uint64_t spare_fir31 : 1; + uint64_t internal_scom_error : 1; + uint64_t internal_scom_error_copy : 1; + uint64_t _reserved0 : 30; +#else + uint64_t _reserved0 : 30; + uint64_t internal_scom_error_copy : 1; + uint64_t internal_scom_error : 1; + uint64_t spare_fir31 : 1; + uint64_t spare_fir30 : 1; + uint64_t dir_purge_ce : 1; + uint64_t srb_buffer_sue : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_ce : 1; + uint64_t occ_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t host_inband_read_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t edram_error : 1; + uint64_t lru_error : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_ue : 1; + uint64_t dir_ce : 1; + uint64_t cache_co_sue : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_ce : 1; + uint64_t int_parity_error : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_ce : 1; + uint64_t internal_timeout : 1; + uint64_t external_timeout : 1; + uint64_t invalid_address_error : 1; + uint64_t int_protocol_error : 1; + uint64_t host_protocol_error : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbs_fir_reg_or_t; + + + +typedef union centaur_mbs_fir_mask_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t host_protocol_error : 1; + uint64_t int_protocol_error : 1; + uint64_t invalid_address_error : 1; + uint64_t external_timeout : 1; + uint64_t internal_timeout : 1; + uint64_t int_buffer_ce : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_parity_error : 1; + uint64_t cache_srw_ce : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_sue : 1; + uint64_t dir_ce : 1; + uint64_t dir_ue : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t lru_error : 1; + uint64_t edram_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t host_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t occ_inband_write_error : 1; + uint64_t srb_buffer_ce : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_sue : 1; + uint64_t dir_purge_ce : 1; + uint64_t spare_fir30 : 1; + uint64_t spare_fir31 : 1; + uint64_t internal_scom_error : 1; + uint64_t internal_scom_error_copy : 1; + uint64_t _reserved0 : 30; +#else + uint64_t _reserved0 : 30; + uint64_t internal_scom_error_copy : 1; + uint64_t internal_scom_error : 1; + uint64_t spare_fir31 : 1; + uint64_t spare_fir30 : 1; + uint64_t dir_purge_ce : 1; + uint64_t srb_buffer_sue : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_ce : 1; + uint64_t occ_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t host_inband_read_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t edram_error : 1; + uint64_t lru_error : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_ue : 1; + uint64_t dir_ce : 1; + uint64_t cache_co_sue : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_ce : 1; + uint64_t int_parity_error : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_ce : 1; + uint64_t internal_timeout : 1; + uint64_t external_timeout : 1; + uint64_t invalid_address_error : 1; + uint64_t int_protocol_error : 1; + uint64_t host_protocol_error : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbs_fir_mask_reg_t; + + + +typedef union centaur_mbs_fir_mask_reg_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t host_protocol_error : 1; + uint64_t int_protocol_error : 1; + uint64_t invalid_address_error : 1; + uint64_t external_timeout : 1; + uint64_t internal_timeout : 1; + uint64_t int_buffer_ce : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_parity_error : 1; + uint64_t cache_srw_ce : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_sue : 1; + uint64_t dir_ce : 1; + uint64_t dir_ue : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t lru_error : 1; + uint64_t edram_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t host_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t occ_inband_write_error : 1; + uint64_t srb_buffer_ce : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_sue : 1; + uint64_t dir_purge_ce : 1; + uint64_t spare_fir30 : 1; + uint64_t spare_fir31 : 1; + uint64_t internal_scom_error : 1; + uint64_t internal_scom_error_copy : 1; + uint64_t _reserved0 : 30; +#else + uint64_t _reserved0 : 30; + uint64_t internal_scom_error_copy : 1; + uint64_t internal_scom_error : 1; + uint64_t spare_fir31 : 1; + uint64_t spare_fir30 : 1; + uint64_t dir_purge_ce : 1; + uint64_t srb_buffer_sue : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_ce : 1; + uint64_t occ_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t host_inband_read_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t edram_error : 1; + uint64_t lru_error : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_ue : 1; + uint64_t dir_ce : 1; + uint64_t cache_co_sue : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_ce : 1; + uint64_t int_parity_error : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_ce : 1; + uint64_t internal_timeout : 1; + uint64_t external_timeout : 1; + uint64_t invalid_address_error : 1; + uint64_t int_protocol_error : 1; + uint64_t host_protocol_error : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbs_fir_mask_reg_and_t; + + + +typedef union centaur_mbs_fir_mask_reg_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t host_protocol_error : 1; + uint64_t int_protocol_error : 1; + uint64_t invalid_address_error : 1; + uint64_t external_timeout : 1; + uint64_t internal_timeout : 1; + uint64_t int_buffer_ce : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_parity_error : 1; + uint64_t cache_srw_ce : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_sue : 1; + uint64_t dir_ce : 1; + uint64_t dir_ue : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t lru_error : 1; + uint64_t edram_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t host_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t occ_inband_write_error : 1; + uint64_t srb_buffer_ce : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_sue : 1; + uint64_t dir_purge_ce : 1; + uint64_t spare_fir30 : 1; + uint64_t spare_fir31 : 1; + uint64_t internal_scom_error : 1; + uint64_t internal_scom_error_copy : 1; + uint64_t _reserved0 : 30; +#else + uint64_t _reserved0 : 30; + uint64_t internal_scom_error_copy : 1; + uint64_t internal_scom_error : 1; + uint64_t spare_fir31 : 1; + uint64_t spare_fir30 : 1; + uint64_t dir_purge_ce : 1; + uint64_t srb_buffer_sue : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_ce : 1; + uint64_t occ_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t host_inband_read_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t edram_error : 1; + uint64_t lru_error : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_ue : 1; + uint64_t dir_ce : 1; + uint64_t cache_co_sue : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_ce : 1; + uint64_t int_parity_error : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_ce : 1; + uint64_t internal_timeout : 1; + uint64_t external_timeout : 1; + uint64_t invalid_address_error : 1; + uint64_t int_protocol_error : 1; + uint64_t host_protocol_error : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbs_fir_mask_reg_or_t; + + + +typedef union centaur_mbs_fir_action0_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t host_protocol_error : 1; + uint64_t int_protocol_error : 1; + uint64_t invalid_address_error : 1; + uint64_t external_timeout : 1; + uint64_t internal_timeout : 1; + uint64_t int_buffer_ce : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_parity_error : 1; + uint64_t cache_srw_ce : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_sue : 1; + uint64_t dir_ce : 1; + uint64_t dir_ue : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t lru_error : 1; + uint64_t edram_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t host_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t occ_inband_write_error : 1; + uint64_t srb_buffer_ce : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_sue : 1; + uint64_t dir_purge_ce : 1; + uint64_t spare_fir30 : 1; + uint64_t spare_fir31 : 1; + uint64_t internal_scom_error : 1; + uint64_t internal_scom_error_copy : 1; + uint64_t _reserved0 : 30; +#else + uint64_t _reserved0 : 30; + uint64_t internal_scom_error_copy : 1; + uint64_t internal_scom_error : 1; + uint64_t spare_fir31 : 1; + uint64_t spare_fir30 : 1; + uint64_t dir_purge_ce : 1; + uint64_t srb_buffer_sue : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_ce : 1; + uint64_t occ_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t host_inband_read_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t edram_error : 1; + uint64_t lru_error : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_ue : 1; + uint64_t dir_ce : 1; + uint64_t cache_co_sue : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_ce : 1; + uint64_t int_parity_error : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_ce : 1; + uint64_t internal_timeout : 1; + uint64_t external_timeout : 1; + uint64_t invalid_address_error : 1; + uint64_t int_protocol_error : 1; + uint64_t host_protocol_error : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbs_fir_action0_reg_t; + + + +typedef union centaur_mbs_firact1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t host_protocol_error : 1; + uint64_t int_protocol_error : 1; + uint64_t invalid_address_error : 1; + uint64_t external_timeout : 1; + uint64_t internal_timeout : 1; + uint64_t int_buffer_ce : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_parity_error : 1; + uint64_t cache_srw_ce : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_sue : 1; + uint64_t dir_ce : 1; + uint64_t dir_ue : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t lru_error : 1; + uint64_t edram_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t host_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t occ_inband_write_error : 1; + uint64_t srb_buffer_ce : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_sue : 1; + uint64_t dir_purge_ce : 1; + uint64_t spare_fir30 : 1; + uint64_t spare_fir31 : 1; + uint64_t internal_scom_error : 1; + uint64_t internal_scom_error_copy : 1; + uint64_t _reserved0 : 30; +#else + uint64_t _reserved0 : 30; + uint64_t internal_scom_error_copy : 1; + uint64_t internal_scom_error : 1; + uint64_t spare_fir31 : 1; + uint64_t spare_fir30 : 1; + uint64_t dir_purge_ce : 1; + uint64_t srb_buffer_sue : 1; + uint64_t srb_buffer_ue : 1; + uint64_t srb_buffer_ce : 1; + uint64_t occ_inband_write_error : 1; + uint64_t occ_inband_read_error : 1; + uint64_t host_inband_write_error : 1; + uint64_t host_inband_read_error : 1; + uint64_t emergency_throttle_set : 1; + uint64_t edram_error : 1; + uint64_t lru_error : 1; + uint64_t dir_all_members_deleted : 1; + uint64_t dir_member_deleted : 1; + uint64_t dir_ue : 1; + uint64_t dir_ce : 1; + uint64_t cache_co_sue : 1; + uint64_t cache_co_ue : 1; + uint64_t cache_co_ce : 1; + uint64_t cache_srw_sue : 1; + uint64_t cache_srw_ue : 1; + uint64_t cache_srw_ce : 1; + uint64_t int_parity_error : 1; + uint64_t int_buffer_sue : 1; + uint64_t int_buffer_ue : 1; + uint64_t int_buffer_ce : 1; + uint64_t internal_timeout : 1; + uint64_t external_timeout : 1; + uint64_t invalid_address_error : 1; + uint64_t int_protocol_error : 1; + uint64_t host_protocol_error : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbs_firact1_t; + + + +typedef union centaur_mbscfgq { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t eccbp_exit_sel : 1; + uint64_t dram_ecc_bypass_dis : 1; + uint64_t mbs_scom_wat_trigger : 1; + uint64_t mbs_prq_ref_avoidance_en : 1; + uint64_t reserved4_6 : 3; + uint64_t occ_deadman_timer_sel : 4; + uint64_t sync_fsync_mba_strobe_en : 1; + uint64_t hca_timebase_op_mode : 1; + uint64_t hca_local_timer_inc_select : 3; + uint64_t mbs_01_rdtag_delay : 4; + uint64_t mbs_01_rdtag_force_dead_cycle : 1; + uint64_t sync_lat_pol_01 : 1; + uint64_t sync_lat_adj_01 : 2; + uint64_t mbs_23_rdtag_delay : 4; + uint64_t mbs_23_rdtag_force_dead_cycle : 1; + uint64_t sync_lat_pol_23 : 1; + uint64_t sync_lat_adj_23 : 2; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t sync_lat_adj_23 : 2; + uint64_t sync_lat_pol_23 : 1; + uint64_t mbs_23_rdtag_force_dead_cycle : 1; + uint64_t mbs_23_rdtag_delay : 4; + uint64_t sync_lat_adj_01 : 2; + uint64_t sync_lat_pol_01 : 1; + uint64_t mbs_01_rdtag_force_dead_cycle : 1; + uint64_t mbs_01_rdtag_delay : 4; + uint64_t hca_local_timer_inc_select : 3; + uint64_t hca_timebase_op_mode : 1; + uint64_t sync_fsync_mba_strobe_en : 1; + uint64_t occ_deadman_timer_sel : 4; + uint64_t reserved4_6 : 3; + uint64_t mbs_prq_ref_avoidance_en : 1; + uint64_t mbs_scom_wat_trigger : 1; + uint64_t dram_ecc_bypass_dis : 1; + uint64_t eccbp_exit_sel : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbscfgq_t; + + + +typedef union centaur_mbsemerthroq { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t emergency_throttle_ip : 1; + uint64_t _reserved0 : 63; +#else + uint64_t _reserved0 : 63; + uint64_t emergency_throttle_ip : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbsemerthroq_t; + + + +typedef union centaur_mbsocc01hq { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t occ_01_rd_hit : 32; + uint64_t occ_01_wr_hit : 32; +#else + uint64_t occ_01_wr_hit : 32; + uint64_t occ_01_rd_hit : 32; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbsocc01hq_t; + + + +typedef union centaur_mbsocc23hq { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t occ_23_rd_hit : 32; + uint64_t occ_23_wr_hit : 32; +#else + uint64_t occ_23_wr_hit : 32; + uint64_t occ_23_rd_hit : 32; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbsocc23hq_t; + + + +typedef union centaur_mbsoccitcq { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t occ_cent_idle_th_cnt : 32; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t occ_cent_idle_th_cnt : 32; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbsoccitcq_t; + + + +typedef union centaur_mbsoccscanq { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t occ_01_spec_can : 32; + uint64_t occ_23_spec_can : 32; +#else + uint64_t occ_23_spec_can : 32; + uint64_t occ_01_spec_can : 32; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbsoccscanq_t; + + + +typedef union centaur_mbarpc0qn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t cfg_lp2_entry_req : 1; + uint64_t cfg_lp2_state : 1; + uint64_t cfg_min_max_domains_enable : 1; + uint64_t cfg_min_max_domains : 3; + uint64_t cfg_pup_avail : 5; + uint64_t cfg_pdn_pup : 5; + uint64_t cfg_pup_pdn : 5; + uint64_t reserved0 : 1; + uint64_t cfg_min_domain_reduction_enable : 1; + uint64_t cfg_min_domain_reduction_on_time : 10; + uint64_t cfg_pup_after_activate_wait_enable : 1; + uint64_t cfg_pup_after_activate_wait_time : 8; + uint64_t cfg_force_spare_pup : 1; + uint64_t _reserved0 : 21; +#else + uint64_t _reserved0 : 21; + uint64_t cfg_force_spare_pup : 1; + uint64_t cfg_pup_after_activate_wait_time : 8; + uint64_t cfg_pup_after_activate_wait_enable : 1; + uint64_t cfg_min_domain_reduction_on_time : 10; + uint64_t cfg_min_domain_reduction_enable : 1; + uint64_t reserved0 : 1; + uint64_t cfg_pup_pdn : 5; + uint64_t cfg_pdn_pup : 5; + uint64_t cfg_pup_avail : 5; + uint64_t cfg_min_max_domains : 3; + uint64_t cfg_min_max_domains_enable : 1; + uint64_t cfg_lp2_state : 1; + uint64_t cfg_lp2_entry_req : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbarpc0qn_t; + + + +typedef union centaur_mba_farb3qn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t cfg_nm_n_per_mba : 15; + uint64_t cfg_nm_n_per_chip : 16; + uint64_t cfg_nm_m : 14; + uint64_t cfg_nm_ras_weight : 3; + uint64_t cfg_nm_cas_weight : 3; + uint64_t cfg_nm_per_slot_enabled : 1; + uint64_t cfg_nm_count_other_mba_dis : 1; + uint64_t _reserved0 : 11; +#else + uint64_t _reserved0 : 11; + uint64_t cfg_nm_count_other_mba_dis : 1; + uint64_t cfg_nm_per_slot_enabled : 1; + uint64_t cfg_nm_cas_weight : 3; + uint64_t cfg_nm_ras_weight : 3; + uint64_t cfg_nm_m : 14; + uint64_t cfg_nm_n_per_chip : 16; + uint64_t cfg_nm_n_per_mba : 15; +#endif // _BIG_ENDIAN + } fields; +} centaur_mba_farb3qn_t; + + + +typedef union centaur_mbapcn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t mode_hp_sub_cnt : 1; + uint64_t mode_lp_sub_cnt : 1; + uint64_t mode_static_idle_dly : 5; + uint64_t mode_emer_min_max_domain : 3; + uint64_t mode_pup_all_wr_pending : 2; + uint64_t mode_lp_ref_sim_enq : 1; + uint64_t _reserved0 : 51; +#else + uint64_t _reserved0 : 51; + uint64_t mode_lp_ref_sim_enq : 1; + uint64_t mode_pup_all_wr_pending : 2; + uint64_t mode_emer_min_max_domain : 3; + uint64_t mode_static_idle_dly : 5; + uint64_t mode_lp_sub_cnt : 1; + uint64_t mode_hp_sub_cnt : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbapcn_t; + + + +typedef union centaur_mbasrqn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t emergency_m : 14; + uint64_t emergency_n : 15; + uint64_t _reserved0 : 35; +#else + uint64_t _reserved0 : 35; + uint64_t emergency_n : 15; + uint64_t emergency_m : 14; +#endif // _BIG_ENDIAN + } fields; +} centaur_mbasrqn_t; + + + +typedef union centaur_pmu0qn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t read_count : 32; + uint64_t write_count : 32; +#else + uint64_t write_count : 32; + uint64_t read_count : 32; +#endif // _BIG_ENDIAN + } fields; +} centaur_pmu0qn_t; + + + +typedef union centaur_pmu1qn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t activate_count : 32; + uint64_t pu_counts : 32; +#else + uint64_t pu_counts : 32; + uint64_t activate_count : 32; +#endif // _BIG_ENDIAN + } fields; +} centaur_pmu1qn_t; + + + +typedef union centaur_pmu2qn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t frame_count : 32; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t frame_count : 32; +#endif // _BIG_ENDIAN + } fields; +} centaur_pmu2qn_t; + + + +typedef union centaur_pmu3qn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t low_idle_threshold : 16; + uint64_t med_idle_threshold : 16; + uint64_t high_idle_threshold : 32; +#else + uint64_t high_idle_threshold : 32; + uint64_t med_idle_threshold : 16; + uint64_t low_idle_threshold : 16; +#endif // _BIG_ENDIAN + } fields; +} centaur_pmu3qn_t; + + + +typedef union centaur_pmu4qn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t base_idle_count : 32; + uint64_t low_idle_count : 32; +#else + uint64_t low_idle_count : 32; + uint64_t base_idle_count : 32; +#endif // _BIG_ENDIAN + } fields; +} centaur_pmu4qn_t; + + + +typedef union centaur_pmu5qn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t med_idle_count : 32; + uint64_t high_idle_count : 32; +#else + uint64_t high_idle_count : 32; + uint64_t med_idle_count : 32; +#endif // _BIG_ENDIAN + } fields; +} centaur_pmu5qn_t; + + + +typedef union centaur_pmu6qn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t total_gap_counts : 18; + uint64_t specific_gap_counts : 18; + uint64_t gap_length_adder : 3; + uint64_t specific_gap_condition : 4; + uint64_t cmd_to_cmd_count : 18; + uint64_t command_pattern_to_count : 3; +#else + uint64_t command_pattern_to_count : 3; + uint64_t cmd_to_cmd_count : 18; + uint64_t specific_gap_condition : 4; + uint64_t gap_length_adder : 3; + uint64_t specific_gap_counts : 18; + uint64_t total_gap_counts : 18; +#endif // _BIG_ENDIAN + } fields; +} centaur_pmu6qn_t; + + + +typedef union centaur_sensor_cache_data0_3 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t crittrip0 : 1; + uint64_t abovetrip0 : 1; + uint64_t belowtrip0 : 1; + uint64_t signbit0 : 1; + uint64_t temperature0 : 8; + uint64_t temp_frac0 : 2; + uint64_t status0 : 2; + uint64_t crittrip1 : 1; + uint64_t abovetrip1 : 1; + uint64_t belowtrip1 : 1; + uint64_t signbit1 : 1; + uint64_t temperature1 : 8; + uint64_t temp_frac1 : 2; + uint64_t status1 : 2; + uint64_t crittrip2 : 1; + uint64_t abovetrip2 : 1; + uint64_t belowtrip2 : 1; + uint64_t signbit2 : 1; + uint64_t temperature2 : 8; + uint64_t temp_frac2 : 2; + uint64_t status2 : 2; + uint64_t crittrip3 : 1; + uint64_t abovetrip3 : 1; + uint64_t belowtrip3 : 1; + uint64_t signbit3 : 1; + uint64_t temperature3 : 8; + uint64_t temp_frac3 : 2; + uint64_t status3 : 2; +#else + uint64_t status3 : 2; + uint64_t temp_frac3 : 2; + uint64_t temperature3 : 8; + uint64_t signbit3 : 1; + uint64_t belowtrip3 : 1; + uint64_t abovetrip3 : 1; + uint64_t crittrip3 : 1; + uint64_t status2 : 2; + uint64_t temp_frac2 : 2; + uint64_t temperature2 : 8; + uint64_t signbit2 : 1; + uint64_t belowtrip2 : 1; + uint64_t abovetrip2 : 1; + uint64_t crittrip2 : 1; + uint64_t status1 : 2; + uint64_t temp_frac1 : 2; + uint64_t temperature1 : 8; + uint64_t signbit1 : 1; + uint64_t belowtrip1 : 1; + uint64_t abovetrip1 : 1; + uint64_t crittrip1 : 1; + uint64_t status0 : 2; + uint64_t temp_frac0 : 2; + uint64_t temperature0 : 8; + uint64_t signbit0 : 1; + uint64_t belowtrip0 : 1; + uint64_t abovetrip0 : 1; + uint64_t crittrip0 : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_sensor_cache_data0_3_t; + + + +typedef union centaur_sensor_cache_data4_7 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t crittrip4 : 1; + uint64_t abovetrip4 : 1; + uint64_t belowtrip4 : 1; + uint64_t signbit4 : 1; + uint64_t temperature4 : 8; + uint64_t temp_frac4 : 2; + uint64_t status4 : 2; + uint64_t crittrip5 : 1; + uint64_t abovetrip5 : 1; + uint64_t belowtrip5 : 1; + uint64_t signbit5 : 1; + uint64_t temperature5 : 8; + uint64_t temp_frac5 : 2; + uint64_t status5 : 2; + uint64_t crittrip6 : 1; + uint64_t abovetrip6 : 1; + uint64_t belowtrip6 : 1; + uint64_t signbit6 : 1; + uint64_t temperature6 : 8; + uint64_t temp_frac6 : 2; + uint64_t status6 : 2; + uint64_t crittrip7 : 1; + uint64_t abovetrip7 : 1; + uint64_t belowtrip7 : 1; + uint64_t signbit7 : 1; + uint64_t temperature7 : 8; + uint64_t temp_frac7 : 2; + uint64_t status7 : 2; +#else + uint64_t status7 : 2; + uint64_t temp_frac7 : 2; + uint64_t temperature7 : 8; + uint64_t signbit7 : 1; + uint64_t belowtrip7 : 1; + uint64_t abovetrip7 : 1; + uint64_t crittrip7 : 1; + uint64_t status6 : 2; + uint64_t temp_frac6 : 2; + uint64_t temperature6 : 8; + uint64_t signbit6 : 1; + uint64_t belowtrip6 : 1; + uint64_t abovetrip6 : 1; + uint64_t crittrip6 : 1; + uint64_t status5 : 2; + uint64_t temp_frac5 : 2; + uint64_t temperature5 : 8; + uint64_t signbit5 : 1; + uint64_t belowtrip5 : 1; + uint64_t abovetrip5 : 1; + uint64_t crittrip5 : 1; + uint64_t status4 : 2; + uint64_t temp_frac4 : 2; + uint64_t temperature4 : 8; + uint64_t signbit4 : 1; + uint64_t belowtrip4 : 1; + uint64_t abovetrip4 : 1; + uint64_t crittrip4 : 1; +#endif // _BIG_ENDIAN + } fields; +} centaur_sensor_cache_data4_7_t; + + + +typedef union centaur_dts_thermal_sensor_results { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t dts0 : 12; + uint64_t thermal_trip0 : 2; + uint64_t spare0 : 1; + uint64_t valid0 : 1; + uint64_t dts1 : 12; + uint64_t thermal_trip1 : 2; + uint64_t spare1 : 1; + uint64_t valid1 : 1; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t valid1 : 1; + uint64_t spare1 : 1; + uint64_t thermal_trip1 : 2; + uint64_t dts1 : 12; + uint64_t valid0 : 1; + uint64_t spare0 : 1; + uint64_t thermal_trip0 : 2; + uint64_t dts0 : 12; +#endif // _BIG_ENDIAN + } fields; +} centaur_dts_thermal_sensor_results_t; + + +#endif // __ASSEMBLER__ +#endif // __CENTAUR_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/centaur_register_addresses.h b/src/ssx/pgp/registers/centaur_register_addresses.h new file mode 100755 index 0000000..7c9c095 --- /dev/null +++ b/src/ssx/pgp/registers/centaur_register_addresses.h @@ -0,0 +1,66 @@ +#ifndef __CENTAUR_REGISTER_ADDRESSES_H__ +#define __CENTAUR_REGISTER_ADDRESSES_H__ + +// $Id: centaur_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/centaur_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file centaur_register_addresses.h +/// \brief Symbolic addresses for the CENTAUR unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define CENTAUR_PIB_BASE 0 +#define CENTAUR_DEVICE_ID 0x000f000f +#define CENTAUR_MBS_FIR_REG 0x02011400 +#define CENTAUR_MBS_FIR_REG_AND 0x02011401 +#define CENTAUR_MBS_FIR_REG_OR 0x02011402 +#define CENTAUR_MBS_FIR_MASK_REG 0x02011403 +#define CENTAUR_MBS_FIR_MASK_REG_AND 0x02011404 +#define CENTAUR_MBS_FIR_MASK_REG_OR 0x02011405 +#define CENTAUR_MBS_FIR_ACTION0_REG 0x02011406 +#define CENTAUR_MBS_FIRACT1 0x02011407 +#define CENTAUR_MBSCFGQ 0x02011411 +#define CENTAUR_MBSEMERTHROQ 0x0201142d +#define CENTAUR_MBSOCC01HQ 0x02011429 +#define CENTAUR_MBSOCC23HQ 0x0201142a +#define CENTAUR_MBSOCCITCQ 0x02011428 +#define CENTAUR_MBSOCCSCANQ 0x0201142b +#define CENTAUR_MBARPC0QN(n) (CENTAUR_MBARPC0Q0 + ((CENTAUR_MBARPC0Q1 - CENTAUR_MBARPC0Q0) * (n))) +#define CENTAUR_MBARPC0Q0 0x03010434 +#define CENTAUR_MBARPC0Q1 0x03010c34 +#define CENTAUR_MBA_FARB3QN(n) (CENTAUR_MBA_FARB3Q0 + ((CENTAUR_MBA_FARB3Q1 - CENTAUR_MBA_FARB3Q0) * (n))) +#define CENTAUR_MBA_FARB3Q0 0x03010416 +#define CENTAUR_MBA_FARB3Q1 0x03010c16 +#define CENTAUR_PMU0QN(n) (CENTAUR_PMU0Q0 + ((CENTAUR_PMU0Q1 - CENTAUR_PMU0Q0) * (n))) +#define CENTAUR_PMU0Q0 0x03010437 +#define CENTAUR_PMU0Q1 0x03010c37 +#define CENTAUR_PMU1QN(n) (CENTAUR_PMU1Q0 + ((CENTAUR_PMU1Q1 - CENTAUR_PMU1Q0) * (n))) +#define CENTAUR_PMU1Q0 0x03010438 +#define CENTAUR_PMU1Q1 0x03010c38 +#define CENTAUR_PMU2QN(n) (CENTAUR_PMU2Q0 + ((CENTAUR_PMU2Q1 - CENTAUR_PMU2Q0) * (n))) +#define CENTAUR_PMU2Q0 0x03010439 +#define CENTAUR_PMU2Q1 0x03010c39 +#define CENTAUR_PMU3QN(n) (CENTAUR_PMU3Q0 + ((CENTAUR_PMU3Q1 - CENTAUR_PMU3Q0) * (n))) +#define CENTAUR_PMU3Q0 0x0301043a +#define CENTAUR_PMU3Q1 0x03010c3a +#define CENTAUR_PMU4QN(n) (CENTAUR_PMU4Q0 + ((CENTAUR_PMU4Q1 - CENTAUR_PMU4Q0) * (n))) +#define CENTAUR_PMU4Q0 0x0301043b +#define CENTAUR_PMU4Q1 0x03010c3b +#define CENTAUR_PMU5QN(n) (CENTAUR_PMU5Q0 + ((CENTAUR_PMU5Q1 - CENTAUR_PMU5Q0) * (n))) +#define CENTAUR_PMU5Q0 0x0301043c +#define CENTAUR_PMU5Q1 0x03010c3c +#define CENTAUR_PMU6QN(n) (CENTAUR_PMU6Q0 + ((CENTAUR_PMU6Q1 - CENTAUR_PMU6Q0) * (n))) +#define CENTAUR_PMU6Q0 0x0301043d +#define CENTAUR_PMU6Q1 0x03010c3d +#define CENTAUR_SENSOR_CACHE_DATA0_3 0x020115ca +#define CENTAUR_SENSOR_CACHE_DATA4_7 0x020115cb +#define CENTAUR_DTS_THERMAL_SENSOR_RESULTS 0x02050000 + +#endif // __CENTAUR_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/fasti2c_firmware_registers.h b/src/ssx/pgp/registers/fasti2c_firmware_registers.h new file mode 100644 index 0000000..4390508 --- /dev/null +++ b/src/ssx/pgp/registers/fasti2c_firmware_registers.h @@ -0,0 +1,232 @@ +#ifndef __FASTI2C_FIRMWARE_REGISTERS_H__ +#define __FASTI2C_FIRMWARE_REGISTERS_H__ + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +// $Id: fasti2c_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ + +/// \file fasti2c_firmware_registers.h +/// \brief C register structs for the FASTI2C unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#include <stdint.h> + + + +typedef union fasti2c_control { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t with_start : 1; + uint64_t with_address : 1; + uint64_t read_continue : 1; + uint64_t with_stop : 1; + uint64_t data_length : 4; + uint64_t device_address : 7; + uint64_t read_not_write : 1; + uint64_t speed : 2; + uint64_t port_number : 5; + uint64_t address_range : 3; + uint64_t _reserved0 : 6; + uint64_t data0 : 8; + uint64_t data1 : 8; + uint64_t data2 : 8; + uint64_t data3 : 8; +#else + uint64_t data3 : 8; + uint64_t data2 : 8; + uint64_t data1 : 8; + uint64_t data0 : 8; + uint64_t _reserved0 : 6; + uint64_t address_range : 3; + uint64_t port_number : 5; + uint64_t speed : 2; + uint64_t read_not_write : 1; + uint64_t device_address : 7; + uint64_t data_length : 4; + uint64_t with_stop : 1; + uint64_t read_continue : 1; + uint64_t with_address : 1; + uint64_t with_start : 1; +#endif // _BIG_ENDIAN + } fields; +} fasti2c_control_t; + + + +typedef union fasti2c_reset { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} fasti2c_reset_t; + + + +typedef union fasti2c_status { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pib_address_invalid : 1; + uint64_t pib_write_invalid : 1; + uint64_t pib_read_invalid : 1; + uint64_t pib_address_parity_error : 1; + uint64_t pib_parity_error : 1; + uint64_t lb_parity_error : 1; + uint64_t read_data : 32; + uint64_t _reserved0 : 6; + uint64_t i2c_macro_busy : 1; + uint64_t i2c_invalid_command : 1; + uint64_t i2c_parity_error : 1; + uint64_t i2c_back_end_overrun_error : 1; + uint64_t i2c_back_end_access_error : 1; + uint64_t i2c_arbitration_lost : 1; + uint64_t i2c_nack_received : 1; + uint64_t i2c_data_request : 1; + uint64_t i2c_command_complete : 1; + uint64_t i2c_stop_error : 1; + uint64_t i2c_port_busy : 1; + uint64_t i2c_interface_busy : 1; + uint64_t i2c_fifo_entry_count : 8; +#else + uint64_t i2c_fifo_entry_count : 8; + uint64_t i2c_interface_busy : 1; + uint64_t i2c_port_busy : 1; + uint64_t i2c_stop_error : 1; + uint64_t i2c_command_complete : 1; + uint64_t i2c_data_request : 1; + uint64_t i2c_nack_received : 1; + uint64_t i2c_arbitration_lost : 1; + uint64_t i2c_back_end_access_error : 1; + uint64_t i2c_back_end_overrun_error : 1; + uint64_t i2c_parity_error : 1; + uint64_t i2c_invalid_command : 1; + uint64_t i2c_macro_busy : 1; + uint64_t _reserved0 : 6; + uint64_t read_data : 32; + uint64_t lb_parity_error : 1; + uint64_t pib_parity_error : 1; + uint64_t pib_address_parity_error : 1; + uint64_t pib_read_invalid : 1; + uint64_t pib_write_invalid : 1; + uint64_t pib_address_invalid : 1; +#endif // _BIG_ENDIAN + } fields; +} fasti2c_status_t; + + + +typedef union fasti2c_data { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} fasti2c_data_t; + + + +typedef union fasti2c_ecc_start { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} fasti2c_ecc_start_t; + + + +typedef union fasti2c_ecc_stop { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} fasti2c_ecc_stop_t; + + +#endif // __ASSEMBLER__ +#endif // __FASTI2C_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/fasti2c_register_addresses.h b/src/ssx/pgp/registers/fasti2c_register_addresses.h new file mode 100644 index 0000000..b034831 --- /dev/null +++ b/src/ssx/pgp/registers/fasti2c_register_addresses.h @@ -0,0 +1,27 @@ +#ifndef __FASTI2C_REGISTER_ADDRESSES_H__ +#define __FASTI2C_REGISTER_ADDRESSES_H__ + +// $Id: fasti2c_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ + +/// \file fasti2c_register_addresses.h +/// \brief Symbolic addresses for the FASTI2C unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define FASTI2C_LPCM_PIB_BASE 0x0000000b +#define FASTI2C_CONTROL_OFFSET 0x00000000 +#define FASTI2C_LPCM_CONTROL 0x0000000b +#define FASTI2C_RESET_OFFSET 0x00000001 +#define FASTI2C_LPCM_RESET 0x0000000c +#define FASTI2C_STATUS_OFFSET 0x00000002 +#define FASTI2C_LPCM_STATUS 0x0000000d +#define FASTI2C_DATA_OFFSET 0x00000003 +#define FASTI2C_LPCM_DATA 0x0000000e +#define FASTI2C_ECC_START_OFFSET 0x00000004 +#define FASTI2C_LPCM_ECC_START 0x0000000f +#define FASTI2C_ECC_STOP_OFFSET 0x00000005 +#define FASTI2C_LPCM_ECC_STOP 0x00000010 + +#endif // __FASTI2C_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/i2cengine_firmware_registers.h b/src/ssx/pgp/registers/i2cengine_firmware_registers.h new file mode 100644 index 0000000..ed02574 --- /dev/null +++ b/src/ssx/pgp/registers/i2cengine_firmware_registers.h @@ -0,0 +1,710 @@ +#ifndef __I2CENGINE_FIRMWARE_REGISTERS_H__ +#define __I2CENGINE_FIRMWARE_REGISTERS_H__ + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +// $Id: i2cengine_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ + +/// \file i2cengine_firmware_registers.h +/// \brief C register structs for the I2CENGINE unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#include <stdint.h> + + + +typedef union i2cengine_fast_control { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t with_start : 1; + uint64_t with_address : 1; + uint64_t read_continue : 1; + uint64_t with_stop : 1; + uint64_t data_length : 4; + uint64_t device_address : 7; + uint64_t read_not_write : 1; + uint64_t speed : 2; + uint64_t port_number : 5; + uint64_t address_range : 3; + uint64_t _reserved0 : 6; + uint64_t data0 : 8; + uint64_t data1 : 8; + uint64_t data2 : 8; + uint64_t data3 : 8; +#else + uint64_t data3 : 8; + uint64_t data2 : 8; + uint64_t data1 : 8; + uint64_t data0 : 8; + uint64_t _reserved0 : 6; + uint64_t address_range : 3; + uint64_t port_number : 5; + uint64_t speed : 2; + uint64_t read_not_write : 1; + uint64_t device_address : 7; + uint64_t data_length : 4; + uint64_t with_stop : 1; + uint64_t read_continue : 1; + uint64_t with_address : 1; + uint64_t with_start : 1; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_fast_control_t; + + + +typedef union i2cengine_fast_reset { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_fast_reset_t; + + + +typedef union i2cengine_fast_status { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pib_address_invalid : 1; + uint64_t pib_write_invalid : 1; + uint64_t pib_read_invalid : 1; + uint64_t pib_address_parity_error : 1; + uint64_t pib_parity_error : 1; + uint64_t lb_parity_error : 1; + uint64_t read_data : 32; + uint64_t _reserved0 : 6; + uint64_t i2c_macro_busy : 1; + uint64_t i2c_invalid_command : 1; + uint64_t i2c_parity_error : 1; + uint64_t i2c_back_end_overrun_error : 1; + uint64_t i2c_back_end_access_error : 1; + uint64_t i2c_arbitration_lost : 1; + uint64_t i2c_nack_received : 1; + uint64_t i2c_data_request : 1; + uint64_t i2c_command_complete : 1; + uint64_t i2c_stop_error : 1; + uint64_t i2c_port_busy : 1; + uint64_t i2c_interface_busy : 1; + uint64_t i2c_fifo_entry_count : 8; +#else + uint64_t i2c_fifo_entry_count : 8; + uint64_t i2c_interface_busy : 1; + uint64_t i2c_port_busy : 1; + uint64_t i2c_stop_error : 1; + uint64_t i2c_command_complete : 1; + uint64_t i2c_data_request : 1; + uint64_t i2c_nack_received : 1; + uint64_t i2c_arbitration_lost : 1; + uint64_t i2c_back_end_access_error : 1; + uint64_t i2c_back_end_overrun_error : 1; + uint64_t i2c_parity_error : 1; + uint64_t i2c_invalid_command : 1; + uint64_t i2c_macro_busy : 1; + uint64_t _reserved0 : 6; + uint64_t read_data : 32; + uint64_t lb_parity_error : 1; + uint64_t pib_parity_error : 1; + uint64_t pib_address_parity_error : 1; + uint64_t pib_read_invalid : 1; + uint64_t pib_write_invalid : 1; + uint64_t pib_address_invalid : 1; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_fast_status_t; + + + +typedef union i2cengine_fast_data { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_fast_data_t; + + + +typedef union i2cengine_fifo_byte { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t data : 32; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t data : 32; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_fifo_byte_t; + + + +typedef union i2cengine_command { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t with_start : 1; + uint64_t with_address : 1; + uint64_t read_continue : 1; + uint64_t not_used : 1; + uint64_t reserved : 4; + uint64_t device_address : 7; + uint64_t read_not_write : 1; + uint64_t length_bytes : 16; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t length_bytes : 16; + uint64_t read_not_write : 1; + uint64_t device_address : 7; + uint64_t reserved : 4; + uint64_t not_used : 1; + uint64_t read_continue : 1; + uint64_t with_address : 1; + uint64_t with_start : 1; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_command_t; + + + +typedef union i2cengine_mode { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t bit_rate_divisor : 15; + uint64_t _reserved0 : 1; + uint64_t port_number : 6; + uint64_t reserved : 6; + uint64_t enhanced_mode : 1; + uint64_t diagnostic_mode : 1; + uint64_t pacing_allow_mode : 1; + uint64_t wrap_mode : 1; + uint64_t _reserved1 : 32; +#else + uint64_t _reserved1 : 32; + uint64_t wrap_mode : 1; + uint64_t pacing_allow_mode : 1; + uint64_t diagnostic_mode : 1; + uint64_t enhanced_mode : 1; + uint64_t reserved : 6; + uint64_t port_number : 6; + uint64_t _reserved0 : 1; + uint64_t bit_rate_divisor : 15; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_mode_t; + + + +typedef union i2cengine_watermark { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved : 15; + uint64_t _reserved0 : 1; + uint64_t high_water_mark : 4; + uint64_t reserved1 : 4; + uint64_t low_water_mark : 4; + uint64_t reserved2 : 4; + uint64_t _reserved1 : 32; +#else + uint64_t _reserved1 : 32; + uint64_t reserved2 : 4; + uint64_t low_water_mark : 4; + uint64_t reserved1 : 4; + uint64_t high_water_mark : 4; + uint64_t _reserved0 : 1; + uint64_t reserved : 15; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_watermark_t; + + + +typedef union i2cengine_interrupt_mask { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved : 16; + uint64_t invalid_command : 1; + uint64_t lbus_parity_error : 1; + uint64_t back_end_overrun_error : 1; + uint64_t back_end_access_error : 1; + uint64_t arbitration_lost_error : 1; + uint64_t nack_received_error : 1; + uint64_t data_request : 1; + uint64_t command_complete : 1; + uint64_t stop_error : 1; + uint64_t i2c_busy : 1; + uint64_t not_i2c_busy : 1; + uint64_t reserved1 : 1; + uint64_t scl_eq_1 : 1; + uint64_t scl_eq_0 : 1; + uint64_t sda_eq_1 : 1; + uint64_t sda_eq_0 : 1; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t sda_eq_0 : 1; + uint64_t sda_eq_1 : 1; + uint64_t scl_eq_0 : 1; + uint64_t scl_eq_1 : 1; + uint64_t reserved1 : 1; + uint64_t not_i2c_busy : 1; + uint64_t i2c_busy : 1; + uint64_t stop_error : 1; + uint64_t command_complete : 1; + uint64_t data_request : 1; + uint64_t nack_received_error : 1; + uint64_t arbitration_lost_error : 1; + uint64_t back_end_access_error : 1; + uint64_t back_end_overrun_error : 1; + uint64_t lbus_parity_error : 1; + uint64_t invalid_command : 1; + uint64_t reserved : 16; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_interrupt_mask_t; + + + +typedef union i2cengine_interrupt_condition { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved : 16; + uint64_t invalid_command : 1; + uint64_t lbus_parity_error : 1; + uint64_t back_end_overrun_error : 1; + uint64_t back_end_access_error : 1; + uint64_t arbitration_lost_error : 1; + uint64_t nack_received_error : 1; + uint64_t data_request : 1; + uint64_t command_complete : 1; + uint64_t stop_error : 1; + uint64_t i2c_busy : 1; + uint64_t not_i2c_busy : 1; + uint64_t reserved1 : 1; + uint64_t scl_eq_1 : 1; + uint64_t scl_eq_0 : 1; + uint64_t sda_eq_1 : 1; + uint64_t sda_eq_0 : 1; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t sda_eq_0 : 1; + uint64_t sda_eq_1 : 1; + uint64_t scl_eq_0 : 1; + uint64_t scl_eq_1 : 1; + uint64_t reserved1 : 1; + uint64_t not_i2c_busy : 1; + uint64_t i2c_busy : 1; + uint64_t stop_error : 1; + uint64_t command_complete : 1; + uint64_t data_request : 1; + uint64_t nack_received_error : 1; + uint64_t arbitration_lost_error : 1; + uint64_t back_end_access_error : 1; + uint64_t back_end_overrun_error : 1; + uint64_t lbus_parity_error : 1; + uint64_t invalid_command : 1; + uint64_t reserved : 16; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_interrupt_condition_t; + + + +typedef union i2cengine_interrupts { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved : 16; + uint64_t invalid_command : 1; + uint64_t lbus_parity_error : 1; + uint64_t back_end_overrun_error : 1; + uint64_t back_end_access_error : 1; + uint64_t arbitration_lost_error : 1; + uint64_t nack_received_error : 1; + uint64_t data_request : 1; + uint64_t command_complete : 1; + uint64_t stop_error : 1; + uint64_t i2c_busy : 1; + uint64_t not_i2c_busy : 1; + uint64_t reserved1 : 1; + uint64_t scl_eq_1 : 1; + uint64_t scl_eq_0 : 1; + uint64_t sda_eq_1 : 1; + uint64_t sda_eq_0 : 1; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t sda_eq_0 : 1; + uint64_t sda_eq_1 : 1; + uint64_t scl_eq_0 : 1; + uint64_t scl_eq_1 : 1; + uint64_t reserved1 : 1; + uint64_t not_i2c_busy : 1; + uint64_t i2c_busy : 1; + uint64_t stop_error : 1; + uint64_t command_complete : 1; + uint64_t data_request : 1; + uint64_t nack_received_error : 1; + uint64_t arbitration_lost_error : 1; + uint64_t back_end_access_error : 1; + uint64_t back_end_overrun_error : 1; + uint64_t lbus_parity_error : 1; + uint64_t invalid_command : 1; + uint64_t reserved : 16; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_interrupts_t; + + + +typedef union i2cengine_status { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t invalid_command : 1; + uint64_t lbus_parity_error : 1; + uint64_t back_end_overrun_error : 1; + uint64_t back_end_access_error : 1; + uint64_t arbitration_lost_error : 1; + uint64_t nack_received_error : 1; + uint64_t data_request : 1; + uint64_t command_complete : 1; + uint64_t stop_error : 1; + uint64_t upper_threshold : 6; + uint64_t _reserved0 : 1; + uint64_t any_i2c_interrupt : 1; + uint64_t reserved1 : 3; + uint64_t scl_input_lvl : 1; + uint64_t sda_input_lvl : 1; + uint64_t i2c_port_busy : 1; + uint64_t i2c_interface_busy : 1; + uint64_t fifo_entry_count : 8; + uint64_t _reserved1 : 32; +#else + uint64_t _reserved1 : 32; + uint64_t fifo_entry_count : 8; + uint64_t i2c_interface_busy : 1; + uint64_t i2c_port_busy : 1; + uint64_t sda_input_lvl : 1; + uint64_t scl_input_lvl : 1; + uint64_t reserved1 : 3; + uint64_t any_i2c_interrupt : 1; + uint64_t _reserved0 : 1; + uint64_t upper_threshold : 6; + uint64_t stop_error : 1; + uint64_t command_complete : 1; + uint64_t data_request : 1; + uint64_t nack_received_error : 1; + uint64_t arbitration_lost_error : 1; + uint64_t back_end_access_error : 1; + uint64_t back_end_overrun_error : 1; + uint64_t lbus_parity_error : 1; + uint64_t invalid_command : 1; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_status_t; + + + +typedef union i2cengine_extended_status { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t table_base_addr : 32; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t table_base_addr : 32; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_extended_status_t; + + + +typedef union i2cengine_residual_front_end_back_end_length { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t residual_front_end_length : 16; + uint64_t residual_back_end_length : 16; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t residual_back_end_length : 16; + uint64_t residual_front_end_length : 16; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_residual_front_end_back_end_length_t; + + + +typedef union i2cengine_immediate_reset_s_scl { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t residual_front_end_length : 16; + uint64_t residual_back_end_length : 16; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t residual_back_end_length : 16; + uint64_t residual_front_end_length : 16; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_immediate_reset_s_scl_t; + + + +typedef union i2cengine_immediate_set_s_sda { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t residual_front_end_length : 16; + uint64_t residual_back_end_length : 16; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t residual_back_end_length : 16; + uint64_t residual_front_end_length : 16; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_immediate_set_s_sda_t; + + + +typedef union i2cengine_immediate_reset_s_sda { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t field : 1; + uint64_t _reserved0 : 63; +#else + uint64_t _reserved0 : 63; + uint64_t field : 1; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_immediate_reset_s_sda_t; + + + +typedef union i2cengine_fifo_word { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t data : 32; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t data : 32; +#endif // _BIG_ENDIAN + } fields; +} i2cengine_fifo_word_t; + + +#endif // __ASSEMBLER__ +#endif // __I2CENGINE_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/i2cengine_register_addresses.h b/src/ssx/pgp/registers/i2cengine_register_addresses.h new file mode 100644 index 0000000..bbe9104 --- /dev/null +++ b/src/ssx/pgp/registers/i2cengine_register_addresses.h @@ -0,0 +1,33 @@ +#ifndef __I2CENGINE_REGISTER_ADDRESSES_H__ +#define __I2CENGINE_REGISTER_ADDRESSES_H__ + +// $Id: i2cengine_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ + +/// \file i2cengine_register_addresses.h +/// \brief Symbolic addresses for the I2CENGINE unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define I2CENGINE_PIB_BASE 0x00000000 +#define I2CENGINE_FAST_CONTROL 0x00000000 +#define I2CENGINE_FAST_RESET 0x00000001 +#define I2CENGINE_FAST_STATUS 0x00000002 +#define I2CENGINE_FAST_DATA 0x00000003 +#define I2CENGINE_FIFO_BYTE 0x00000004 +#define I2CENGINE_COMMAND 0x00000005 +#define I2CENGINE_MODE 0x00000006 +#define I2CENGINE_WATERMARK 0x00000007 +#define I2CENGINE_INTERRUPT_MASK 0x00000008 +#define I2CENGINE_INTERRUPT_CONDITION 0x00000009 +#define I2CENGINE_INTERRUPTS 0x0000000a +#define I2CENGINE_STATUS 0x0000000b +#define I2CENGINE_EXTENDED_STATUS 0x0000000c +#define I2CENGINE_RESIDUAL_FRONT_END_BACK_END_LENGTH 0x0000000d +#define I2CENGINE_IMMEDIATE_RESET_S_SCL 0x0000000f +#define I2CENGINE_IMMEDIATE_SET_S_SDA 0x00000010 +#define I2CENGINE_IMMEDIATE_RESET_S_SDA 0x00000011 +#define I2CENGINE_FIFO_WORD 0x00000012 + +#endif // __I2CENGINE_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/icp_firmware_registers.h b/src/ssx/pgp/registers/icp_firmware_registers.h new file mode 100755 index 0000000..4e17a68 --- /dev/null +++ b/src/ssx/pgp/registers/icp_firmware_registers.h @@ -0,0 +1,189 @@ +#ifndef __ICP_FIRMWARE_REGISTERS_H__ +#define __ICP_FIRMWARE_REGISTERS_H__ + +// $Id: icp_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/icp_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file icp_firmware_registers.h +/// \brief C register structs for the ICP unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union icp_bar { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t icp_bar : 30; + uint64_t icp_bar_en : 1; + uint64_t _reserved0 : 33; +#else + uint64_t _reserved0 : 33; + uint64_t icp_bar_en : 1; + uint64_t icp_bar : 30; +#endif // _BIG_ENDIAN + } fields; +} icp_bar_t; + +#endif // __ASSEMBLER__ +#define ICP_BAR_ICP_BAR_MASK SIXTYFOUR_BIT_CONSTANT(0xfffffffc00000000) +#define ICP_BAR_ICP_BAR_EN SIXTYFOUR_BIT_CONSTANT(0x0000000200000000) +#ifndef __ASSEMBLER__ + + +typedef union icp_mode0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t priority : 8; + uint64_t reserved0 : 1; + uint64_t scope_initial : 3; + uint64_t reserved1 : 1; + uint64_t no_hang2status : 1; + uint64_t oper_disable_hang : 1; + uint64_t oper_hang_div : 5; + uint64_t reserved2 : 2; + uint64_t data_disable_hang : 1; + uint64_t data_hang_div : 5; + uint64_t backoff_disable : 1; + uint64_t fwd_que_fwd_conv_disable : 1; + uint64_t disa_wait4cresp_mode4ris : 1; + uint64_t disa_auto_no_retry4ris : 1; + uint64_t disa_retry_mode4ris : 1; + uint64_t hang_on_addr_error : 1; + uint64_t eoi_correction : 2; + uint64_t max_load_count : 4; + uint64_t max_store_count : 4; + uint64_t reserved3 : 3; + uint64_t enable_inject : 1; + uint64_t _reserved0 : 16; +#else + uint64_t _reserved0 : 16; + uint64_t enable_inject : 1; + uint64_t reserved3 : 3; + uint64_t max_store_count : 4; + uint64_t max_load_count : 4; + uint64_t eoi_correction : 2; + uint64_t hang_on_addr_error : 1; + uint64_t disa_retry_mode4ris : 1; + uint64_t disa_auto_no_retry4ris : 1; + uint64_t disa_wait4cresp_mode4ris : 1; + uint64_t fwd_que_fwd_conv_disable : 1; + uint64_t backoff_disable : 1; + uint64_t data_hang_div : 5; + uint64_t data_disable_hang : 1; + uint64_t reserved2 : 2; + uint64_t oper_hang_div : 5; + uint64_t oper_disable_hang : 1; + uint64_t no_hang2status : 1; + uint64_t reserved1 : 1; + uint64_t scope_initial : 3; + uint64_t reserved0 : 1; + uint64_t priority : 8; +#endif // _BIG_ENDIAN + } fields; +} icp_mode0_t; + +#endif // __ASSEMBLER__ +#define ICP_MODE0_PRIORITY_MASK SIXTYFOUR_BIT_CONSTANT(0xff00000000000000) +#define ICP_MODE0_SCOPE_INITIAL_MASK SIXTYFOUR_BIT_CONSTANT(0x0070000000000000) +#define ICP_MODE0_NO_HANG2STATUS SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) +#define ICP_MODE0_OPER_DISABLE_HANG SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) +#define ICP_MODE0_OPER_HANG_DIV_MASK SIXTYFOUR_BIT_CONSTANT(0x0001f00000000000) +#define ICP_MODE0_DATA_DISABLE_HANG SIXTYFOUR_BIT_CONSTANT(0x0000020000000000) +#define ICP_MODE0_DATA_HANG_DIV_MASK SIXTYFOUR_BIT_CONSTANT(0x000001f000000000) +#define ICP_MODE0_BACKOFF_DISABLE SIXTYFOUR_BIT_CONSTANT(0x0000000800000000) +#define ICP_MODE0_FWD_QUE_FWD_CONV_DISABLE SIXTYFOUR_BIT_CONSTANT(0x0000000400000000) +#define ICP_MODE0_DISA_WAIT4CRESP_MODE4RIS SIXTYFOUR_BIT_CONSTANT(0x0000000200000000) +#define ICP_MODE0_DISA_AUTO_NO_RETRY4RIS SIXTYFOUR_BIT_CONSTANT(0x0000000100000000) +#define ICP_MODE0_DISA_RETRY_MODE4RIS SIXTYFOUR_BIT_CONSTANT(0x0000000080000000) +#define ICP_MODE0_HANG_ON_ADDR_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000040000000) +#define ICP_MODE0_EOI_CORRECTION_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000030000000) +#define ICP_MODE0_MAX_LOAD_COUNT_MASK SIXTYFOUR_BIT_CONSTANT(0x000000000f000000) +#define ICP_MODE0_MAX_STORE_COUNT_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000000f00000) +#define ICP_MODE0_ENABLE_INJECT SIXTYFOUR_BIT_CONSTANT(0x0000000000010000) +#ifndef __ASSEMBLER__ + + +typedef union icp_iir { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t inject_target_core : 16; + uint64_t inject_target_thread : 8; + uint64_t reserved0 : 8; + uint64_t inject_level : 4; + uint64_t reserved1 : 4; + uint64_t inject_priority : 8; + uint64_t _reserved0 : 16; +#else + uint64_t _reserved0 : 16; + uint64_t inject_priority : 8; + uint64_t reserved1 : 4; + uint64_t inject_level : 4; + uint64_t reserved0 : 8; + uint64_t inject_target_thread : 8; + uint64_t inject_target_core : 16; +#endif // _BIG_ENDIAN + } fields; +} icp_iir_t; + +#endif // __ASSEMBLER__ +#define ICP_IIR_INJECT_TARGET_CORE_MASK SIXTYFOUR_BIT_CONSTANT(0xffff000000000000) +#define ICP_IIR_INJECT_TARGET_THREAD_MASK SIXTYFOUR_BIT_CONSTANT(0x0000ff0000000000) +#define ICP_IIR_INJECT_LEVEL_MASK SIXTYFOUR_BIT_CONSTANT(0x00000000f0000000) +#define ICP_IIR_INJECT_PRIORITY_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000000ff0000) +#ifndef __ASSEMBLER__ + +#endif // __ASSEMBLER__ +#endif // __ICP_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/icp_register_addresses.h b/src/ssx/pgp/registers/icp_register_addresses.h new file mode 100755 index 0000000..7cb8350 --- /dev/null +++ b/src/ssx/pgp/registers/icp_register_addresses.h @@ -0,0 +1,24 @@ +#ifndef __ICP_REGISTER_ADDRESSES_H__ +#define __ICP_REGISTER_ADDRESSES_H__ + +// $Id: icp_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/icp_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file icp_register_addresses.h +/// \brief Symbolic addresses for the ICP unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define ICP_PIB_BASE 0x020109c0 +#define ICP_BAR 0x020109ca +#define ICP_MODE0 0x020109cb +#define ICP_IIR 0x020109cc + +#endif // __ICP_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/mcs_firmware_registers.h b/src/ssx/pgp/registers/mcs_firmware_registers.h new file mode 100755 index 0000000..b71b888 --- /dev/null +++ b/src/ssx/pgp/registers/mcs_firmware_registers.h @@ -0,0 +1,161 @@ +#ifndef __MCS_FIRMWARE_REGISTERS_H__ +#define __MCS_FIRMWARE_REGISTERS_H__ + +// $Id: mcs_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/mcs_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file mcs_firmware_registers.h +/// \brief C register structs for the MCS unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union mcfgpr { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t mcfgprq_valid : 1; + uint64_t reserved0 : 5; + uint64_t mcfgprq_base_address : 14; + uint64_t _reserved0 : 44; +#else + uint64_t _reserved0 : 44; + uint64_t mcfgprq_base_address : 14; + uint64_t reserved0 : 5; + uint64_t mcfgprq_valid : 1; +#endif // _BIG_ENDIAN + } fields; +} mcfgpr_t; + +#endif // __ASSEMBLER__ +#define MCFGPR_MCFGPRQ_VALID SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define MCFGPR_MCFGPRQ_BASE_ADDRESS_MASK SIXTYFOUR_BIT_CONSTANT(0x03fff00000000000) +#ifndef __ASSEMBLER__ + + +typedef union mcsmode0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t enable_cmd_byp_stutter : 1; + uint64_t reserved1 : 1; + uint64_t enable_ns_rd_ao_sfu_for_dcbz : 1; + uint64_t enable_centaur_local_checkstop_command : 1; + uint64_t l3_prefetch_retry_threshold : 4; + uint64_t number_of_cl_entries_reserved_for_read : 4; + uint64_t number_of_cl_entries_reserved_for_mirrored_ops : 4; + uint64_t number_of_cl_entries_reserved_for_writes : 4; + uint64_t number_of_cl_entries_reserved_for_cp_writes : 4; + uint64_t number_of_cl_entries_reserved_for_cp_ig : 4; + uint64_t number_of_cl_entries_reserved_for_htm_ops : 4; + uint64_t number_of_cl_entries_reserved_for_ha_assist : 4; + uint64_t mcfgrp_19_is_ho_bit : 1; + uint64_t cl_channel_timeout_forces_channel_fail : 1; + uint64_t enable_fault_line_for_global_checkstop : 1; + uint64_t reserved39 : 5; + uint64_t address_collision_modes : 9; + uint64_t include_cp_ig_in_cp_write_fullness_group : 1; + uint64_t enable_dmawr_cmd_bit : 1; + uint64_t enable_read_lsfr_data : 1; + uint64_t force_channel_fail : 1; + uint64_t disable_read_crc_ecc_bypass_taken : 1; + uint64_t disable_cl_ao_queueus : 1; + uint64_t address_select_lfsr_value : 2; + uint64_t enable_centaur_sync : 1; + uint64_t write_data_buffer_ecc_check_disable : 1; + uint64_t write_data_buffer_ecc_correct_disable : 1; +#else + uint64_t write_data_buffer_ecc_correct_disable : 1; + uint64_t write_data_buffer_ecc_check_disable : 1; + uint64_t enable_centaur_sync : 1; + uint64_t address_select_lfsr_value : 2; + uint64_t disable_cl_ao_queueus : 1; + uint64_t disable_read_crc_ecc_bypass_taken : 1; + uint64_t force_channel_fail : 1; + uint64_t enable_read_lsfr_data : 1; + uint64_t enable_dmawr_cmd_bit : 1; + uint64_t include_cp_ig_in_cp_write_fullness_group : 1; + uint64_t address_collision_modes : 9; + uint64_t reserved39 : 5; + uint64_t enable_fault_line_for_global_checkstop : 1; + uint64_t cl_channel_timeout_forces_channel_fail : 1; + uint64_t mcfgrp_19_is_ho_bit : 1; + uint64_t number_of_cl_entries_reserved_for_ha_assist : 4; + uint64_t number_of_cl_entries_reserved_for_htm_ops : 4; + uint64_t number_of_cl_entries_reserved_for_cp_ig : 4; + uint64_t number_of_cl_entries_reserved_for_cp_writes : 4; + uint64_t number_of_cl_entries_reserved_for_writes : 4; + uint64_t number_of_cl_entries_reserved_for_mirrored_ops : 4; + uint64_t number_of_cl_entries_reserved_for_read : 4; + uint64_t l3_prefetch_retry_threshold : 4; + uint64_t enable_centaur_local_checkstop_command : 1; + uint64_t enable_ns_rd_ao_sfu_for_dcbz : 1; + uint64_t reserved1 : 1; + uint64_t enable_cmd_byp_stutter : 1; +#endif // _BIG_ENDIAN + } fields; +} mcsmode0_t; + +#endif // __ASSEMBLER__ +#define MCSMODE0_ENABLE_CMD_BYP_STUTTER SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define MCSMODE0_ENABLE_NS_RD_AO_SFU_FOR_DCBZ SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) +#define MCSMODE0_ENABLE_CENTAUR_LOCAL_CHECKSTOP_COMMAND SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) +#define MCSMODE0_L3_PREFETCH_RETRY_THRESHOLD_MASK SIXTYFOUR_BIT_CONSTANT(0x0f00000000000000) +#define MCSMODE0_MCFGRP_19_IS_HO_BIT SIXTYFOUR_BIT_CONSTANT(0x0000000008000000) +#define MCSMODE0_CL_CHANNEL_TIMEOUT_FORCES_CHANNEL_FAIL SIXTYFOUR_BIT_CONSTANT(0x0000000004000000) +#define MCSMODE0_ENABLE_FAULT_LINE_FOR_GLOBAL_CHECKSTOP SIXTYFOUR_BIT_CONSTANT(0x0000000002000000) +#define MCSMODE0_ADDRESS_COLLISION_MODES_MASK SIXTYFOUR_BIT_CONSTANT(0x00000000000ff800) +#define MCSMODE0_INCLUDE_CP_IG_IN_CP_WRITE_FULLNESS_GROUP SIXTYFOUR_BIT_CONSTANT(0x0000000000000400) +#define MCSMODE0_ENABLE_DMAWR_CMD_BIT SIXTYFOUR_BIT_CONSTANT(0x0000000000000200) +#define MCSMODE0_ENABLE_READ_LSFR_DATA SIXTYFOUR_BIT_CONSTANT(0x0000000000000100) +#define MCSMODE0_FORCE_CHANNEL_FAIL SIXTYFOUR_BIT_CONSTANT(0x0000000000000080) +#define MCSMODE0_DISABLE_READ_CRC_ECC_BYPASS_TAKEN SIXTYFOUR_BIT_CONSTANT(0x0000000000000040) +#define MCSMODE0_DISABLE_CL_AO_QUEUEUS SIXTYFOUR_BIT_CONSTANT(0x0000000000000020) +#define MCSMODE0_ADDRESS_SELECT_LFSR_VALUE_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000000000018) +#define MCSMODE0_ENABLE_CENTAUR_SYNC SIXTYFOUR_BIT_CONSTANT(0x0000000000000004) +#define MCSMODE0_WRITE_DATA_BUFFER_ECC_CHECK_DISABLE SIXTYFOUR_BIT_CONSTANT(0x0000000000000002) +#define MCSMODE0_WRITE_DATA_BUFFER_ECC_CORRECT_DISABLE SIXTYFOUR_BIT_CONSTANT(0x0000000000000001) +#ifndef __ASSEMBLER__ + +#endif // __ASSEMBLER__ +#endif // __MCS_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/mcs_register_addresses.h b/src/ssx/pgp/registers/mcs_register_addresses.h new file mode 100755 index 0000000..bc7f95c --- /dev/null +++ b/src/ssx/pgp/registers/mcs_register_addresses.h @@ -0,0 +1,46 @@ +#ifndef __MCS_REGISTER_ADDRESSES_H__ +#define __MCS_REGISTER_ADDRESSES_H__ + +// $Id: mcs_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/mcs_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file mcs_register_addresses.h +/// \brief Symbolic addresses for the MCS unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define MCS0_PIB_BASE 0x02011800 +#define MCS1_PIB_BASE 0x02011880 +#define MCS2_PIB_BASE 0x02011900 +#define MCS3_PIB_BASE 0x02011980 +#define MCS4_PIB_BASE 0x02011C00 +#define MCS5_PIB_BASE 0x02011C80 +#define MCS6_PIB_BASE 0x02011D00 +#define MCS7_PIB_BASE 0x02011D80 +#define MCFGPR_OFFSET 0x00000002 +#define MCS0_MCFGPR 0x02011802 +#define MCS1_MCFGPR 0x02011882 +#define MCS2_MCFGPR 0x02011902 +#define MCS3_MCFGPR 0x02011982 +#define MCS4_MCFGPR 0x02011c02 +#define MCS5_MCFGPR 0x02011c82 +#define MCS6_MCFGPR 0x02011d02 +#define MCS7_MCFGPR 0x02011d82 +#define MCSMODE0_OFFSET 0x00000007 +#define MCS0_MCSMODE0 0x02011807 +#define MCS1_MCSMODE0 0x02011887 +#define MCS2_MCSMODE0 0x02011907 +#define MCS3_MCSMODE0 0x02011987 +#define MCS4_MCSMODE0 0x02011c07 +#define MCS5_MCSMODE0 0x02011c87 +#define MCS6_MCSMODE0 0x02011d07 +#define MCS7_MCSMODE0 0x02011d87 + +#endif // __MCS_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/ocb_firmware_registers.h b/src/ssx/pgp/registers/ocb_firmware_registers.h new file mode 100755 index 0000000..4a4ddb2 --- /dev/null +++ b/src/ssx/pgp/registers/ocb_firmware_registers.h @@ -0,0 +1,2668 @@ +#ifndef __OCB_FIRMWARE_REGISTERS_H__ +#define __OCB_FIRMWARE_REGISTERS_H__ + +// $Id: ocb_firmware_registers.h,v 1.2 2014/03/14 15:33:03 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/ocb_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2014 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file ocb_firmware_registers.h +/// \brief C register structs for the OCB unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union ocb_oitr0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oitr0_t; + + + +typedef union ocb_oiepr0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oiepr0_t; + + + +typedef union ocb_ocir0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocir0_t; + + + +typedef union ocb_onisr0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_onisr0_t; + + + +typedef union ocb_ouder0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ouder0_t; + + + +typedef union ocb_ocisr0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocisr0_t; + + + +typedef union ocb_odher0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t dbg_halt_en : 32; +#else + uint32_t dbg_halt_en : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_odher0_t; + + + +typedef union ocb_oisr0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t debugger : 1; + uint32_t trace_trigger : 1; + uint32_t reserved_2 : 1; + uint32_t pba_error : 1; + uint32_t srt_error : 1; + uint32_t pore_sw_error : 1; + uint32_t pore_gpe0_fatal_error : 1; + uint32_t pore_gpe1_fatal_error : 1; + uint32_t pore_sbe_fatal_error : 1; + uint32_t pmc_error : 1; + uint32_t ocb_error : 1; + uint32_t spipss_error : 1; + uint32_t check_stop : 1; + uint32_t pmc_malf_alert : 1; + uint32_t adu_malf_alert : 1; + uint32_t external_trap : 1; + uint32_t occ_timer0 : 1; + uint32_t occ_timer1 : 1; + uint32_t pore_gpe0_error : 1; + uint32_t pore_gpe1_error : 1; + uint32_t pore_sbe_error : 1; + uint32_t pmc_interchip_msg_recv : 1; + uint32_t reserved_22 : 1; + uint32_t pore_gpe0_complete : 1; + uint32_t pore_gpe1_complete : 1; + uint32_t adcfsm_ongoing : 1; + uint32_t reserved_26 : 1; + uint32_t pba_occ_push0 : 1; + uint32_t pba_occ_push1 : 1; + uint32_t pba_bcde_attn : 1; + uint32_t pba_bcue_attn : 1; + uint32_t reserved_31 : 1; +#else + uint32_t reserved_31 : 1; + uint32_t pba_bcue_attn : 1; + uint32_t pba_bcde_attn : 1; + uint32_t pba_occ_push1 : 1; + uint32_t pba_occ_push0 : 1; + uint32_t reserved_26 : 1; + uint32_t adcfsm_ongoing : 1; + uint32_t pore_gpe1_complete : 1; + uint32_t pore_gpe0_complete : 1; + uint32_t reserved_22 : 1; + uint32_t pmc_interchip_msg_recv : 1; + uint32_t pore_sbe_error : 1; + uint32_t pore_gpe1_error : 1; + uint32_t pore_gpe0_error : 1; + uint32_t occ_timer1 : 1; + uint32_t occ_timer0 : 1; + uint32_t external_trap : 1; + uint32_t adu_malf_alert : 1; + uint32_t pmc_malf_alert : 1; + uint32_t check_stop : 1; + uint32_t spipss_error : 1; + uint32_t ocb_error : 1; + uint32_t pmc_error : 1; + uint32_t pore_sbe_fatal_error : 1; + uint32_t pore_gpe1_fatal_error : 1; + uint32_t pore_gpe0_fatal_error : 1; + uint32_t pore_sw_error : 1; + uint32_t srt_error : 1; + uint32_t pba_error : 1; + uint32_t reserved_2 : 1; + uint32_t trace_trigger : 1; + uint32_t debugger : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oisr0_t; + + + +typedef union ocb_oisr0_and { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t debugger : 1; + uint32_t trace_trigger : 1; + uint32_t reserved_2 : 1; + uint32_t pba_error : 1; + uint32_t srt_error : 1; + uint32_t pore_sw_error : 1; + uint32_t pore_gpe0_fatal_error : 1; + uint32_t pore_gpe1_fatal_error : 1; + uint32_t pore_sbe_fatal_error : 1; + uint32_t pmc_error : 1; + uint32_t ocb_error : 1; + uint32_t spipss_error : 1; + uint32_t check_stop : 1; + uint32_t pmc_malf_alert : 1; + uint32_t adu_malf_alert : 1; + uint32_t external_trap : 1; + uint32_t occ_timer0 : 1; + uint32_t occ_timer1 : 1; + uint32_t pore_gpe0_error : 1; + uint32_t pore_gpe1_error : 1; + uint32_t pore_sbe_error : 1; + uint32_t pmc_interchip_msg_recv : 1; + uint32_t reserved_22 : 1; + uint32_t pore_gpe0_complete : 1; + uint32_t pore_gpe1_complete : 1; + uint32_t adcfsm_ongoing : 1; + uint32_t reserved_26 : 1; + uint32_t pba_occ_push0 : 1; + uint32_t pba_occ_push1 : 1; + uint32_t pba_bcde_attn : 1; + uint32_t pba_bcue_attn : 1; + uint32_t reserved_31 : 1; +#else + uint32_t reserved_31 : 1; + uint32_t pba_bcue_attn : 1; + uint32_t pba_bcde_attn : 1; + uint32_t pba_occ_push1 : 1; + uint32_t pba_occ_push0 : 1; + uint32_t reserved_26 : 1; + uint32_t adcfsm_ongoing : 1; + uint32_t pore_gpe1_complete : 1; + uint32_t pore_gpe0_complete : 1; + uint32_t reserved_22 : 1; + uint32_t pmc_interchip_msg_recv : 1; + uint32_t pore_sbe_error : 1; + uint32_t pore_gpe1_error : 1; + uint32_t pore_gpe0_error : 1; + uint32_t occ_timer1 : 1; + uint32_t occ_timer0 : 1; + uint32_t external_trap : 1; + uint32_t adu_malf_alert : 1; + uint32_t pmc_malf_alert : 1; + uint32_t check_stop : 1; + uint32_t spipss_error : 1; + uint32_t ocb_error : 1; + uint32_t pmc_error : 1; + uint32_t pore_sbe_fatal_error : 1; + uint32_t pore_gpe1_fatal_error : 1; + uint32_t pore_gpe0_fatal_error : 1; + uint32_t pore_sw_error : 1; + uint32_t srt_error : 1; + uint32_t pba_error : 1; + uint32_t reserved_2 : 1; + uint32_t trace_trigger : 1; + uint32_t debugger : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oisr0_and_t; + + + +typedef union ocb_oisr0_or { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t debugger : 1; + uint32_t trace_trigger : 1; + uint32_t reserved_2 : 1; + uint32_t pba_error : 1; + uint32_t srt_error : 1; + uint32_t pore_sw_error : 1; + uint32_t pore_gpe0_fatal_error : 1; + uint32_t pore_gpe1_fatal_error : 1; + uint32_t pore_sbe_fatal_error : 1; + uint32_t pmc_error : 1; + uint32_t ocb_error : 1; + uint32_t spipss_error : 1; + uint32_t check_stop : 1; + uint32_t pmc_malf_alert : 1; + uint32_t adu_malf_alert : 1; + uint32_t external_trap : 1; + uint32_t occ_timer0 : 1; + uint32_t occ_timer1 : 1; + uint32_t pore_gpe0_error : 1; + uint32_t pore_gpe1_error : 1; + uint32_t pore_sbe_error : 1; + uint32_t pmc_interchip_msg_recv : 1; + uint32_t reserved_22 : 1; + uint32_t pore_gpe0_complete : 1; + uint32_t pore_gpe1_complete : 1; + uint32_t adcfsm_ongoing : 1; + uint32_t reserved_26 : 1; + uint32_t pba_occ_push0 : 1; + uint32_t pba_occ_push1 : 1; + uint32_t pba_bcde_attn : 1; + uint32_t pba_bcue_attn : 1; + uint32_t reserved_31 : 1; +#else + uint32_t reserved_31 : 1; + uint32_t pba_bcue_attn : 1; + uint32_t pba_bcde_attn : 1; + uint32_t pba_occ_push1 : 1; + uint32_t pba_occ_push0 : 1; + uint32_t reserved_26 : 1; + uint32_t adcfsm_ongoing : 1; + uint32_t pore_gpe1_complete : 1; + uint32_t pore_gpe0_complete : 1; + uint32_t reserved_22 : 1; + uint32_t pmc_interchip_msg_recv : 1; + uint32_t pore_sbe_error : 1; + uint32_t pore_gpe1_error : 1; + uint32_t pore_gpe0_error : 1; + uint32_t occ_timer1 : 1; + uint32_t occ_timer0 : 1; + uint32_t external_trap : 1; + uint32_t adu_malf_alert : 1; + uint32_t pmc_malf_alert : 1; + uint32_t check_stop : 1; + uint32_t spipss_error : 1; + uint32_t ocb_error : 1; + uint32_t pmc_error : 1; + uint32_t pore_sbe_fatal_error : 1; + uint32_t pore_gpe1_fatal_error : 1; + uint32_t pore_gpe0_fatal_error : 1; + uint32_t pore_sw_error : 1; + uint32_t srt_error : 1; + uint32_t pba_error : 1; + uint32_t reserved_2 : 1; + uint32_t trace_trigger : 1; + uint32_t debugger : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oisr0_or_t; + + + +typedef union ocb_oimr0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t debugger : 1; + uint32_t trace_trigger : 1; + uint32_t reserved_2 : 1; + uint32_t pba_error : 1; + uint32_t srt_error : 1; + uint32_t pore_sw_error : 1; + uint32_t pore_gpe0_fatal_error : 1; + uint32_t pore_gpe1_fatal_error : 1; + uint32_t pore_sbe_fatal_error : 1; + uint32_t pmc_error : 1; + uint32_t ocb_error : 1; + uint32_t spipss_error : 1; + uint32_t check_stop : 1; + uint32_t pmc_malf_alert : 1; + uint32_t adu_malf_alert : 1; + uint32_t external_trap : 1; + uint32_t occ_timer0 : 1; + uint32_t occ_timer1 : 1; + uint32_t pore_gpe0_error : 1; + uint32_t pore_gpe1_error : 1; + uint32_t pore_sbe_error : 1; + uint32_t pmc_interchip_msg_recv : 1; + uint32_t reserved_22 : 1; + uint32_t pore_gpe0_complete : 1; + uint32_t pore_gpe1_complete : 1; + uint32_t adcfsm_ongoing : 1; + uint32_t reserved_26 : 1; + uint32_t pba_occ_push0 : 1; + uint32_t pba_occ_push1 : 1; + uint32_t pba_bcde_attn : 1; + uint32_t pba_bcue_attn : 1; + uint32_t reserved_31 : 1; +#else + uint32_t reserved_31 : 1; + uint32_t pba_bcue_attn : 1; + uint32_t pba_bcde_attn : 1; + uint32_t pba_occ_push1 : 1; + uint32_t pba_occ_push0 : 1; + uint32_t reserved_26 : 1; + uint32_t adcfsm_ongoing : 1; + uint32_t pore_gpe1_complete : 1; + uint32_t pore_gpe0_complete : 1; + uint32_t reserved_22 : 1; + uint32_t pmc_interchip_msg_recv : 1; + uint32_t pore_sbe_error : 1; + uint32_t pore_gpe1_error : 1; + uint32_t pore_gpe0_error : 1; + uint32_t occ_timer1 : 1; + uint32_t occ_timer0 : 1; + uint32_t external_trap : 1; + uint32_t adu_malf_alert : 1; + uint32_t pmc_malf_alert : 1; + uint32_t check_stop : 1; + uint32_t spipss_error : 1; + uint32_t ocb_error : 1; + uint32_t pmc_error : 1; + uint32_t pore_sbe_fatal_error : 1; + uint32_t pore_gpe1_fatal_error : 1; + uint32_t pore_gpe0_fatal_error : 1; + uint32_t pore_sw_error : 1; + uint32_t srt_error : 1; + uint32_t pba_error : 1; + uint32_t reserved_2 : 1; + uint32_t trace_trigger : 1; + uint32_t debugger : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oimr0_t; + + + +typedef union ocb_oimr0_and { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t debugger : 1; + uint32_t trace_trigger : 1; + uint32_t reserved_2 : 1; + uint32_t pba_error : 1; + uint32_t srt_error : 1; + uint32_t pore_sw_error : 1; + uint32_t pore_gpe0_fatal_error : 1; + uint32_t pore_gpe1_fatal_error : 1; + uint32_t pore_sbe_fatal_error : 1; + uint32_t pmc_error : 1; + uint32_t ocb_error : 1; + uint32_t spipss_error : 1; + uint32_t check_stop : 1; + uint32_t pmc_malf_alert : 1; + uint32_t adu_malf_alert : 1; + uint32_t external_trap : 1; + uint32_t occ_timer0 : 1; + uint32_t occ_timer1 : 1; + uint32_t pore_gpe0_error : 1; + uint32_t pore_gpe1_error : 1; + uint32_t pore_sbe_error : 1; + uint32_t pmc_interchip_msg_recv : 1; + uint32_t reserved_22 : 1; + uint32_t pore_gpe0_complete : 1; + uint32_t pore_gpe1_complete : 1; + uint32_t adcfsm_ongoing : 1; + uint32_t reserved_26 : 1; + uint32_t pba_occ_push0 : 1; + uint32_t pba_occ_push1 : 1; + uint32_t pba_bcde_attn : 1; + uint32_t pba_bcue_attn : 1; + uint32_t reserved_31 : 1; +#else + uint32_t reserved_31 : 1; + uint32_t pba_bcue_attn : 1; + uint32_t pba_bcde_attn : 1; + uint32_t pba_occ_push1 : 1; + uint32_t pba_occ_push0 : 1; + uint32_t reserved_26 : 1; + uint32_t adcfsm_ongoing : 1; + uint32_t pore_gpe1_complete : 1; + uint32_t pore_gpe0_complete : 1; + uint32_t reserved_22 : 1; + uint32_t pmc_interchip_msg_recv : 1; + uint32_t pore_sbe_error : 1; + uint32_t pore_gpe1_error : 1; + uint32_t pore_gpe0_error : 1; + uint32_t occ_timer1 : 1; + uint32_t occ_timer0 : 1; + uint32_t external_trap : 1; + uint32_t adu_malf_alert : 1; + uint32_t pmc_malf_alert : 1; + uint32_t check_stop : 1; + uint32_t spipss_error : 1; + uint32_t ocb_error : 1; + uint32_t pmc_error : 1; + uint32_t pore_sbe_fatal_error : 1; + uint32_t pore_gpe1_fatal_error : 1; + uint32_t pore_gpe0_fatal_error : 1; + uint32_t pore_sw_error : 1; + uint32_t srt_error : 1; + uint32_t pba_error : 1; + uint32_t reserved_2 : 1; + uint32_t trace_trigger : 1; + uint32_t debugger : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oimr0_and_t; + + + +typedef union ocb_oimr0_or { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t debugger : 1; + uint32_t trace_trigger : 1; + uint32_t reserved_2 : 1; + uint32_t pba_error : 1; + uint32_t srt_error : 1; + uint32_t pore_sw_error : 1; + uint32_t pore_gpe0_fatal_error : 1; + uint32_t pore_gpe1_fatal_error : 1; + uint32_t pore_sbe_fatal_error : 1; + uint32_t pmc_error : 1; + uint32_t ocb_error : 1; + uint32_t spipss_error : 1; + uint32_t check_stop : 1; + uint32_t pmc_malf_alert : 1; + uint32_t adu_malf_alert : 1; + uint32_t external_trap : 1; + uint32_t occ_timer0 : 1; + uint32_t occ_timer1 : 1; + uint32_t pore_gpe0_error : 1; + uint32_t pore_gpe1_error : 1; + uint32_t pore_sbe_error : 1; + uint32_t pmc_interchip_msg_recv : 1; + uint32_t reserved_22 : 1; + uint32_t pore_gpe0_complete : 1; + uint32_t pore_gpe1_complete : 1; + uint32_t adcfsm_ongoing : 1; + uint32_t reserved_26 : 1; + uint32_t pba_occ_push0 : 1; + uint32_t pba_occ_push1 : 1; + uint32_t pba_bcde_attn : 1; + uint32_t pba_bcue_attn : 1; + uint32_t reserved_31 : 1; +#else + uint32_t reserved_31 : 1; + uint32_t pba_bcue_attn : 1; + uint32_t pba_bcde_attn : 1; + uint32_t pba_occ_push1 : 1; + uint32_t pba_occ_push0 : 1; + uint32_t reserved_26 : 1; + uint32_t adcfsm_ongoing : 1; + uint32_t pore_gpe1_complete : 1; + uint32_t pore_gpe0_complete : 1; + uint32_t reserved_22 : 1; + uint32_t pmc_interchip_msg_recv : 1; + uint32_t pore_sbe_error : 1; + uint32_t pore_gpe1_error : 1; + uint32_t pore_gpe0_error : 1; + uint32_t occ_timer1 : 1; + uint32_t occ_timer0 : 1; + uint32_t external_trap : 1; + uint32_t adu_malf_alert : 1; + uint32_t pmc_malf_alert : 1; + uint32_t check_stop : 1; + uint32_t spipss_error : 1; + uint32_t ocb_error : 1; + uint32_t pmc_error : 1; + uint32_t pore_sbe_fatal_error : 1; + uint32_t pore_gpe1_fatal_error : 1; + uint32_t pore_gpe0_fatal_error : 1; + uint32_t pore_sw_error : 1; + uint32_t srt_error : 1; + uint32_t pba_error : 1; + uint32_t reserved_2 : 1; + uint32_t trace_trigger : 1; + uint32_t debugger : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oimr0_or_t; + + + +typedef union ocb_oitr1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oitr1_t; + + + +typedef union ocb_oiepr1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_oiepr1_t; + + + +typedef union ocb_ocir1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocir1_t; + + + +typedef union ocb_onisr1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_onisr1_t; + + + +typedef union ocb_ouder1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ouder1_t; + + + +typedef union ocb_ocisr1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocisr1_t; + + + +typedef union ocb_odher1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t dbg_halt_en : 32; +#else + uint32_t dbg_halt_en : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_odher1_t; + + + +typedef union ocb_oisr1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t reserved_32 : 1; + uint32_t reserved_33 : 1; + uint32_t occ_strm0_pull : 1; + uint32_t occ_strm0_push : 1; + uint32_t occ_strm1_pull : 1; + uint32_t occ_strm1_push : 1; + uint32_t occ_strm2_pull : 1; + uint32_t occ_strm2_push : 1; + uint32_t occ_strm3_pull : 1; + uint32_t occ_strm3_push : 1; + uint32_t reserved_42 : 1; + uint32_t reserved_43 : 1; + uint32_t pmc_voltage_change_ongoing : 1; + uint32_t pmc_protocol_ongoing : 1; + uint32_t pmc_sync : 1; + uint32_t pmc_pstate_change : 1; + uint32_t reserved_48 : 1; + uint32_t reserved_49 : 1; + uint32_t pmc_idle_exit : 1; + uint32_t pore_sw_complete : 1; + uint32_t pmc_idle_enter : 1; + uint32_t reserved_53 : 1; + uint32_t pmc_interchip_msg_send_ongoing : 1; + uint32_t oci2spivid_ongoing : 1; + uint32_t pmc_ocb_o2p_ongoing : 1; + uint32_t pssbridge_ongoing : 1; + uint32_t pore_sbe_complete : 1; + uint32_t ipi0 : 1; + uint32_t ipi1 : 1; + uint32_t ipi2 : 1; + uint32_t ipi3 : 1; + uint32_t reserved_63 : 1; +#else + uint32_t reserved_63 : 1; + uint32_t ipi3 : 1; + uint32_t ipi2 : 1; + uint32_t ipi1 : 1; + uint32_t ipi0 : 1; + uint32_t pore_sbe_complete : 1; + uint32_t pssbridge_ongoing : 1; + uint32_t pmc_ocb_o2p_ongoing : 1; + uint32_t oci2spivid_ongoing : 1; + uint32_t pmc_interchip_msg_send_ongoing : 1; + uint32_t reserved_53 : 1; + uint32_t pmc_idle_enter : 1; + uint32_t pore_sw_complete : 1; + uint32_t pmc_idle_exit : 1; + uint32_t reserved_49 : 1; + uint32_t reserved_48 : 1; + uint32_t pmc_pstate_change : 1; + uint32_t pmc_sync : 1; + uint32_t pmc_protocol_ongoing : 1; + uint32_t pmc_voltage_change_ongoing : 1; + uint32_t reserved_43 : 1; + uint32_t reserved_42 : 1; + uint32_t occ_strm3_push : 1; + uint32_t occ_strm3_pull : 1; + uint32_t occ_strm2_push : 1; + uint32_t occ_strm2_pull : 1; + uint32_t occ_strm1_push : 1; + uint32_t occ_strm1_pull : 1; + uint32_t occ_strm0_push : 1; + uint32_t occ_strm0_pull : 1; + uint32_t reserved_33 : 1; + uint32_t reserved_32 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oisr1_t; + + + +typedef union ocb_oisr1_and { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t reserved_32 : 1; + uint32_t reserved_33 : 1; + uint32_t occ_strm0_pull : 1; + uint32_t occ_strm0_push : 1; + uint32_t occ_strm1_pull : 1; + uint32_t occ_strm1_push : 1; + uint32_t occ_strm2_pull : 1; + uint32_t occ_strm2_push : 1; + uint32_t occ_strm3_pull : 1; + uint32_t occ_strm3_push : 1; + uint32_t reserved_42 : 1; + uint32_t reserved_43 : 1; + uint32_t pmc_voltage_change_ongoing : 1; + uint32_t pmc_protocol_ongoing : 1; + uint32_t pmc_sync : 1; + uint32_t pmc_pstate_change : 1; + uint32_t reserved_48 : 1; + uint32_t reserved_49 : 1; + uint32_t pmc_idle_exit : 1; + uint32_t pore_sw_complete : 1; + uint32_t pmc_idle_enter : 1; + uint32_t reserved_53 : 1; + uint32_t pmc_interchip_msg_send_ongoing : 1; + uint32_t oci2spivid_ongoing : 1; + uint32_t pmc_ocb_o2p_ongoing : 1; + uint32_t pssbridge_ongoing : 1; + uint32_t pore_sbe_complete : 1; + uint32_t ipi0 : 1; + uint32_t ipi1 : 1; + uint32_t ipi2 : 1; + uint32_t ipi3 : 1; + uint32_t reserved_63 : 1; +#else + uint32_t reserved_63 : 1; + uint32_t ipi3 : 1; + uint32_t ipi2 : 1; + uint32_t ipi1 : 1; + uint32_t ipi0 : 1; + uint32_t pore_sbe_complete : 1; + uint32_t pssbridge_ongoing : 1; + uint32_t pmc_ocb_o2p_ongoing : 1; + uint32_t oci2spivid_ongoing : 1; + uint32_t pmc_interchip_msg_send_ongoing : 1; + uint32_t reserved_53 : 1; + uint32_t pmc_idle_enter : 1; + uint32_t pore_sw_complete : 1; + uint32_t pmc_idle_exit : 1; + uint32_t reserved_49 : 1; + uint32_t reserved_48 : 1; + uint32_t pmc_pstate_change : 1; + uint32_t pmc_sync : 1; + uint32_t pmc_protocol_ongoing : 1; + uint32_t pmc_voltage_change_ongoing : 1; + uint32_t reserved_43 : 1; + uint32_t reserved_42 : 1; + uint32_t occ_strm3_push : 1; + uint32_t occ_strm3_pull : 1; + uint32_t occ_strm2_push : 1; + uint32_t occ_strm2_pull : 1; + uint32_t occ_strm1_push : 1; + uint32_t occ_strm1_pull : 1; + uint32_t occ_strm0_push : 1; + uint32_t occ_strm0_pull : 1; + uint32_t reserved_33 : 1; + uint32_t reserved_32 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oisr1_and_t; + + + +typedef union ocb_oisr1_or { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t reserved_32 : 1; + uint32_t reserved_33 : 1; + uint32_t occ_strm0_pull : 1; + uint32_t occ_strm0_push : 1; + uint32_t occ_strm1_pull : 1; + uint32_t occ_strm1_push : 1; + uint32_t occ_strm2_pull : 1; + uint32_t occ_strm2_push : 1; + uint32_t occ_strm3_pull : 1; + uint32_t occ_strm3_push : 1; + uint32_t reserved_42 : 1; + uint32_t reserved_43 : 1; + uint32_t pmc_voltage_change_ongoing : 1; + uint32_t pmc_protocol_ongoing : 1; + uint32_t pmc_sync : 1; + uint32_t pmc_pstate_change : 1; + uint32_t reserved_48 : 1; + uint32_t reserved_49 : 1; + uint32_t pmc_idle_exit : 1; + uint32_t pore_sw_complete : 1; + uint32_t pmc_idle_enter : 1; + uint32_t reserved_53 : 1; + uint32_t pmc_interchip_msg_send_ongoing : 1; + uint32_t oci2spivid_ongoing : 1; + uint32_t pmc_ocb_o2p_ongoing : 1; + uint32_t pssbridge_ongoing : 1; + uint32_t pore_sbe_complete : 1; + uint32_t ipi0 : 1; + uint32_t ipi1 : 1; + uint32_t ipi2 : 1; + uint32_t ipi3 : 1; + uint32_t reserved_63 : 1; +#else + uint32_t reserved_63 : 1; + uint32_t ipi3 : 1; + uint32_t ipi2 : 1; + uint32_t ipi1 : 1; + uint32_t ipi0 : 1; + uint32_t pore_sbe_complete : 1; + uint32_t pssbridge_ongoing : 1; + uint32_t pmc_ocb_o2p_ongoing : 1; + uint32_t oci2spivid_ongoing : 1; + uint32_t pmc_interchip_msg_send_ongoing : 1; + uint32_t reserved_53 : 1; + uint32_t pmc_idle_enter : 1; + uint32_t pore_sw_complete : 1; + uint32_t pmc_idle_exit : 1; + uint32_t reserved_49 : 1; + uint32_t reserved_48 : 1; + uint32_t pmc_pstate_change : 1; + uint32_t pmc_sync : 1; + uint32_t pmc_protocol_ongoing : 1; + uint32_t pmc_voltage_change_ongoing : 1; + uint32_t reserved_43 : 1; + uint32_t reserved_42 : 1; + uint32_t occ_strm3_push : 1; + uint32_t occ_strm3_pull : 1; + uint32_t occ_strm2_push : 1; + uint32_t occ_strm2_pull : 1; + uint32_t occ_strm1_push : 1; + uint32_t occ_strm1_pull : 1; + uint32_t occ_strm0_push : 1; + uint32_t occ_strm0_pull : 1; + uint32_t reserved_33 : 1; + uint32_t reserved_32 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oisr1_or_t; + + + +typedef union ocb_oimr1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t reserved_32 : 1; + uint32_t reserved_33 : 1; + uint32_t occ_strm0_pull : 1; + uint32_t occ_strm0_push : 1; + uint32_t occ_strm1_pull : 1; + uint32_t occ_strm1_push : 1; + uint32_t occ_strm2_pull : 1; + uint32_t occ_strm2_push : 1; + uint32_t occ_strm3_pull : 1; + uint32_t occ_strm3_push : 1; + uint32_t reserved_42 : 1; + uint32_t reserved_43 : 1; + uint32_t pmc_voltage_change_ongoing : 1; + uint32_t pmc_protocol_ongoing : 1; + uint32_t pmc_sync : 1; + uint32_t pmc_pstate_change : 1; + uint32_t reserved_48 : 1; + uint32_t reserved_49 : 1; + uint32_t pmc_idle_exit : 1; + uint32_t pore_sw_complete : 1; + uint32_t pmc_idle_enter : 1; + uint32_t reserved_53 : 1; + uint32_t pmc_interchip_msg_send_ongoing : 1; + uint32_t oci2spivid_ongoing : 1; + uint32_t pmc_ocb_o2p_ongoing : 1; + uint32_t pssbridge_ongoing : 1; + uint32_t pore_sbe_complete : 1; + uint32_t ipi0 : 1; + uint32_t ipi1 : 1; + uint32_t ipi2 : 1; + uint32_t ipi3 : 1; + uint32_t reserved_63 : 1; +#else + uint32_t reserved_63 : 1; + uint32_t ipi3 : 1; + uint32_t ipi2 : 1; + uint32_t ipi1 : 1; + uint32_t ipi0 : 1; + uint32_t pore_sbe_complete : 1; + uint32_t pssbridge_ongoing : 1; + uint32_t pmc_ocb_o2p_ongoing : 1; + uint32_t oci2spivid_ongoing : 1; + uint32_t pmc_interchip_msg_send_ongoing : 1; + uint32_t reserved_53 : 1; + uint32_t pmc_idle_enter : 1; + uint32_t pore_sw_complete : 1; + uint32_t pmc_idle_exit : 1; + uint32_t reserved_49 : 1; + uint32_t reserved_48 : 1; + uint32_t pmc_pstate_change : 1; + uint32_t pmc_sync : 1; + uint32_t pmc_protocol_ongoing : 1; + uint32_t pmc_voltage_change_ongoing : 1; + uint32_t reserved_43 : 1; + uint32_t reserved_42 : 1; + uint32_t occ_strm3_push : 1; + uint32_t occ_strm3_pull : 1; + uint32_t occ_strm2_push : 1; + uint32_t occ_strm2_pull : 1; + uint32_t occ_strm1_push : 1; + uint32_t occ_strm1_pull : 1; + uint32_t occ_strm0_push : 1; + uint32_t occ_strm0_pull : 1; + uint32_t reserved_33 : 1; + uint32_t reserved_32 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oimr1_t; + + + +typedef union ocb_oimr1_and { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t reserved_32 : 1; + uint32_t reserved_33 : 1; + uint32_t occ_strm0_pull : 1; + uint32_t occ_strm0_push : 1; + uint32_t occ_strm1_pull : 1; + uint32_t occ_strm1_push : 1; + uint32_t occ_strm2_pull : 1; + uint32_t occ_strm2_push : 1; + uint32_t occ_strm3_pull : 1; + uint32_t occ_strm3_push : 1; + uint32_t reserved_42 : 1; + uint32_t reserved_43 : 1; + uint32_t pmc_voltage_change_ongoing : 1; + uint32_t pmc_protocol_ongoing : 1; + uint32_t pmc_sync : 1; + uint32_t pmc_pstate_change : 1; + uint32_t reserved_48 : 1; + uint32_t reserved_49 : 1; + uint32_t pmc_idle_exit : 1; + uint32_t pore_sw_complete : 1; + uint32_t pmc_idle_enter : 1; + uint32_t reserved_53 : 1; + uint32_t pmc_interchip_msg_send_ongoing : 1; + uint32_t oci2spivid_ongoing : 1; + uint32_t pmc_ocb_o2p_ongoing : 1; + uint32_t pssbridge_ongoing : 1; + uint32_t pore_sbe_complete : 1; + uint32_t ipi0 : 1; + uint32_t ipi1 : 1; + uint32_t ipi2 : 1; + uint32_t ipi3 : 1; + uint32_t reserved_63 : 1; +#else + uint32_t reserved_63 : 1; + uint32_t ipi3 : 1; + uint32_t ipi2 : 1; + uint32_t ipi1 : 1; + uint32_t ipi0 : 1; + uint32_t pore_sbe_complete : 1; + uint32_t pssbridge_ongoing : 1; + uint32_t pmc_ocb_o2p_ongoing : 1; + uint32_t oci2spivid_ongoing : 1; + uint32_t pmc_interchip_msg_send_ongoing : 1; + uint32_t reserved_53 : 1; + uint32_t pmc_idle_enter : 1; + uint32_t pore_sw_complete : 1; + uint32_t pmc_idle_exit : 1; + uint32_t reserved_49 : 1; + uint32_t reserved_48 : 1; + uint32_t pmc_pstate_change : 1; + uint32_t pmc_sync : 1; + uint32_t pmc_protocol_ongoing : 1; + uint32_t pmc_voltage_change_ongoing : 1; + uint32_t reserved_43 : 1; + uint32_t reserved_42 : 1; + uint32_t occ_strm3_push : 1; + uint32_t occ_strm3_pull : 1; + uint32_t occ_strm2_push : 1; + uint32_t occ_strm2_pull : 1; + uint32_t occ_strm1_push : 1; + uint32_t occ_strm1_pull : 1; + uint32_t occ_strm0_push : 1; + uint32_t occ_strm0_pull : 1; + uint32_t reserved_33 : 1; + uint32_t reserved_32 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oimr1_and_t; + + + +typedef union ocb_oimr1_or { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t reserved_32 : 1; + uint32_t reserved_33 : 1; + uint32_t occ_strm0_pull : 1; + uint32_t occ_strm0_push : 1; + uint32_t occ_strm1_pull : 1; + uint32_t occ_strm1_push : 1; + uint32_t occ_strm2_pull : 1; + uint32_t occ_strm2_push : 1; + uint32_t occ_strm3_pull : 1; + uint32_t occ_strm3_push : 1; + uint32_t reserved_42 : 1; + uint32_t reserved_43 : 1; + uint32_t pmc_voltage_change_ongoing : 1; + uint32_t pmc_protocol_ongoing : 1; + uint32_t pmc_sync : 1; + uint32_t pmc_pstate_change : 1; + uint32_t reserved_48 : 1; + uint32_t reserved_49 : 1; + uint32_t pmc_idle_exit : 1; + uint32_t pore_sw_complete : 1; + uint32_t pmc_idle_enter : 1; + uint32_t reserved_53 : 1; + uint32_t pmc_interchip_msg_send_ongoing : 1; + uint32_t oci2spivid_ongoing : 1; + uint32_t pmc_ocb_o2p_ongoing : 1; + uint32_t pssbridge_ongoing : 1; + uint32_t pore_sbe_complete : 1; + uint32_t ipi0 : 1; + uint32_t ipi1 : 1; + uint32_t ipi2 : 1; + uint32_t ipi3 : 1; + uint32_t reserved_63 : 1; +#else + uint32_t reserved_63 : 1; + uint32_t ipi3 : 1; + uint32_t ipi2 : 1; + uint32_t ipi1 : 1; + uint32_t ipi0 : 1; + uint32_t pore_sbe_complete : 1; + uint32_t pssbridge_ongoing : 1; + uint32_t pmc_ocb_o2p_ongoing : 1; + uint32_t oci2spivid_ongoing : 1; + uint32_t pmc_interchip_msg_send_ongoing : 1; + uint32_t reserved_53 : 1; + uint32_t pmc_idle_enter : 1; + uint32_t pore_sw_complete : 1; + uint32_t pmc_idle_exit : 1; + uint32_t reserved_49 : 1; + uint32_t reserved_48 : 1; + uint32_t pmc_pstate_change : 1; + uint32_t pmc_sync : 1; + uint32_t pmc_protocol_ongoing : 1; + uint32_t pmc_voltage_change_ongoing : 1; + uint32_t reserved_43 : 1; + uint32_t reserved_42 : 1; + uint32_t occ_strm3_push : 1; + uint32_t occ_strm3_pull : 1; + uint32_t occ_strm2_push : 1; + uint32_t occ_strm2_pull : 1; + uint32_t occ_strm1_push : 1; + uint32_t occ_strm1_pull : 1; + uint32_t occ_strm0_push : 1; + uint32_t occ_strm0_pull : 1; + uint32_t reserved_33 : 1; + uint32_t reserved_32 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oimr1_or_t; + + + +typedef union ocb_occmisc { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t core_ext_intr : 1; + uint32_t _reserved0 : 31; +#else + uint32_t _reserved0 : 31; + uint32_t core_ext_intr : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occmisc_t; + + + +typedef union ocb_occmisc_and { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t core_ext_intr : 1; + uint32_t _reserved0 : 31; +#else + uint32_t _reserved0 : 31; + uint32_t core_ext_intr : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occmisc_and_t; + + + +typedef union ocb_occmisc_or { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t core_ext_intr : 1; + uint32_t _reserved0 : 31; +#else + uint32_t _reserved0 : 31; + uint32_t core_ext_intr : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occmisc_or_t; + + + +typedef union ocb_otrn { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t timeout : 1; + uint32_t control : 1; + uint32_t auto_reload : 1; + uint32_t reserved : 13; + uint32_t timer : 16; +#else + uint32_t timer : 16; + uint32_t reserved : 13; + uint32_t auto_reload : 1; + uint32_t control : 1; + uint32_t timeout : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_otrn_t; + +#endif // __ASSEMBLER__ +#define OCB_OTRN_TIMEOUT 0x80000000 +#define OCB_OTRN_CONTROL 0x40000000 +#define OCB_OTRN_AUTO_RELOAD 0x20000000 +#define OCB_OTRN_TIMER_MASK 0x0000ffff +#ifndef __ASSEMBLER__ + + +typedef union ocb_ohtmcr { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t htm_src_sel : 2; + uint32_t htm_stop : 1; + uint32_t htm_marker_slave_adrs : 3; + uint32_t event2halt_mode : 2; + uint32_t event2halt_en : 11; + uint32_t reserved : 1; + uint32_t event2halt_halt : 1; + uint32_t _reserved0 : 11; +#else + uint32_t _reserved0 : 11; + uint32_t event2halt_halt : 1; + uint32_t reserved : 1; + uint32_t event2halt_en : 11; + uint32_t event2halt_mode : 2; + uint32_t htm_marker_slave_adrs : 3; + uint32_t htm_stop : 1; + uint32_t htm_src_sel : 2; +#endif // _BIG_ENDIAN + } fields; +} ocb_ohtmcr_t; + + + +typedef union ocb_oehdr { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t event2halt_delay : 20; + uint32_t _reserved0 : 12; +#else + uint32_t _reserved0 : 12; + uint32_t event2halt_delay : 20; +#endif // _BIG_ENDIAN + } fields; +} ocb_oehdr_t; + + + +typedef union ocb_ocbslbrn { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t pull_oci_region : 2; + uint32_t pull_start : 27; + uint32_t _reserved0 : 3; +#else + uint32_t _reserved0 : 3; + uint32_t pull_start : 27; + uint32_t pull_oci_region : 2; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbslbrn_t; + + + +typedef union ocb_ocbshbrn { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t push_oci_region : 2; + uint32_t push_start : 27; + uint32_t _reserved0 : 3; +#else + uint32_t _reserved0 : 3; + uint32_t push_start : 27; + uint32_t push_oci_region : 2; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbshbrn_t; + + + +typedef union ocb_ocbslcsn { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t pull_full : 1; + uint32_t pull_empty : 1; + uint32_t reserved0 : 2; + uint32_t pull_intr_action : 2; + uint32_t pull_length : 5; + uint32_t reserved1 : 2; + uint32_t pull_write_ptr : 5; + uint32_t reserved2 : 3; + uint32_t pull_read_ptr : 5; + uint32_t reserved3 : 5; + uint32_t pull_enable : 1; +#else + uint32_t pull_enable : 1; + uint32_t reserved3 : 5; + uint32_t pull_read_ptr : 5; + uint32_t reserved2 : 3; + uint32_t pull_write_ptr : 5; + uint32_t reserved1 : 2; + uint32_t pull_length : 5; + uint32_t pull_intr_action : 2; + uint32_t reserved0 : 2; + uint32_t pull_empty : 1; + uint32_t pull_full : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbslcsn_t; + +#endif // __ASSEMBLER__ +#define OCB_OCBSLCSN_PULL_FULL 0x80000000 +#define OCB_OCBSLCSN_PULL_EMPTY 0x40000000 +#define OCB_OCBSLCSN_PULL_INTR_ACTION_MASK 0x0c000000 +#define OCB_OCBSLCSN_PULL_LENGTH_MASK 0x03e00000 +#define OCB_OCBSLCSN_PULL_WRITE_PTR_MASK 0x0007c000 +#define OCB_OCBSLCSN_PULL_READ_PTR_MASK 0x000007c0 +#define OCB_OCBSLCSN_PULL_ENABLE 0x00000001 +#ifndef __ASSEMBLER__ + + +typedef union ocb_ocbshcsn { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t push_full : 1; + uint32_t push_empty : 1; + uint32_t reserved0 : 2; + uint32_t push_intr_action : 2; + uint32_t push_length : 5; + uint32_t reserved1 : 2; + uint32_t push_write_ptr : 5; + uint32_t reserved2 : 3; + uint32_t push_read_ptr : 5; + uint32_t reserved3 : 5; + uint32_t push_enable : 1; +#else + uint32_t push_enable : 1; + uint32_t reserved3 : 5; + uint32_t push_read_ptr : 5; + uint32_t reserved2 : 3; + uint32_t push_write_ptr : 5; + uint32_t reserved1 : 2; + uint32_t push_length : 5; + uint32_t push_intr_action : 2; + uint32_t reserved0 : 2; + uint32_t push_empty : 1; + uint32_t push_full : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbshcsn_t; + +#endif // __ASSEMBLER__ +#define OCB_OCBSHCSN_PUSH_FULL 0x80000000 +#define OCB_OCBSHCSN_PUSH_EMPTY 0x40000000 +#define OCB_OCBSHCSN_PUSH_INTR_ACTION_MASK 0x0c000000 +#define OCB_OCBSHCSN_PUSH_LENGTH_MASK 0x03e00000 +#define OCB_OCBSHCSN_PUSH_WRITE_PTR_MASK 0x0007c000 +#define OCB_OCBSHCSN_PUSH_READ_PTR_MASK 0x000007c0 +#define OCB_OCBSHCSN_PUSH_ENABLE 0x00000001 +#ifndef __ASSEMBLER__ + + +typedef union ocb_ocbslin { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t reserved : 32; +#else + uint32_t reserved : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbslin_t; + + + +typedef union ocb_ocbshin { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t reserved : 32; +#else + uint32_t reserved : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbshin_t; + + + +typedef union ocb_ocbsesn { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t push_read_underflow : 1; + uint32_t pull_write_overflow : 1; + uint32_t _reserved0 : 30; +#else + uint32_t _reserved0 : 30; + uint32_t pull_write_overflow : 1; + uint32_t push_read_underflow : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbsesn_t; + + + +typedef union ocb_ocbicrn { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t allow_unsecure_pib_masters : 1; + uint32_t _reserved0 : 31; +#else + uint32_t _reserved0 : 31; + uint32_t allow_unsecure_pib_masters : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbicrn_t; + + + +typedef union ocb_ocblwcrn { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t linear_window_enable : 1; + uint32_t spare_0 : 3; + uint32_t linear_window_bar : 16; + uint32_t linear_window_mask : 12; +#else + uint32_t linear_window_mask : 12; + uint32_t linear_window_bar : 16; + uint32_t spare_0 : 3; + uint32_t linear_window_enable : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocblwcrn_t; + + + +typedef union ocb_ocblwsrn { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t linear_window_scresp : 3; + uint32_t spare_0 : 5; + uint32_t _reserved0 : 24; +#else + uint32_t _reserved0 : 24; + uint32_t spare_0 : 5; + uint32_t linear_window_scresp : 3; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocblwsrn_t; + + + +typedef union ocb_ocblwsbrn { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t linear_window_region : 2; + uint32_t linear_window_base : 8; + uint32_t _reserved0 : 22; +#else + uint32_t _reserved0 : 22; + uint32_t linear_window_base : 8; + uint32_t linear_window_region : 2; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocblwsbrn_t; + + + +typedef union ocb_ocichsw { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t m0_priority : 2; + uint32_t m1_priority : 2; + uint32_t m2_priority : 2; + uint32_t m3_priority : 2; + uint32_t m4_priority : 2; + uint32_t m5_priority : 2; + uint32_t m6_priority : 2; + uint32_t m7_priority : 2; + uint32_t dcu_priority_sel : 1; + uint32_t icu_priority_sel : 1; + uint32_t plbarb_lockerr : 1; + uint32_t _reserved0 : 13; +#else + uint32_t _reserved0 : 13; + uint32_t plbarb_lockerr : 1; + uint32_t icu_priority_sel : 1; + uint32_t dcu_priority_sel : 1; + uint32_t m7_priority : 2; + uint32_t m6_priority : 2; + uint32_t m5_priority : 2; + uint32_t m4_priority : 2; + uint32_t m3_priority : 2; + uint32_t m2_priority : 2; + uint32_t m1_priority : 2; + uint32_t m0_priority : 2; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocichsw_t; + + + +typedef union ocb_ocr { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t core_reset : 1; + uint64_t chip_reset : 1; + uint64_t system_reset : 1; + uint64_t oci_arb_reset : 1; + uint64_t trace_disable : 1; + uint64_t trace_event : 1; + uint64_t dbg_unconditional_event : 1; + uint64_t ext_interrupt : 1; + uint64_t critical_interrupt : 1; + uint64_t spare : 7; + uint64_t _reserved0 : 48; +#else + uint64_t _reserved0 : 48; + uint64_t spare : 7; + uint64_t critical_interrupt : 1; + uint64_t ext_interrupt : 1; + uint64_t dbg_unconditional_event : 1; + uint64_t trace_event : 1; + uint64_t trace_disable : 1; + uint64_t oci_arb_reset : 1; + uint64_t system_reset : 1; + uint64_t chip_reset : 1; + uint64_t core_reset : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocr_t; + + + +typedef union ocb_ocr_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t core_reset : 1; + uint64_t chip_reset : 1; + uint64_t system_reset : 1; + uint64_t oci_arb_reset : 1; + uint64_t trace_disable : 1; + uint64_t trace_event : 1; + uint64_t dbg_unconditional_event : 1; + uint64_t ext_interrupt : 1; + uint64_t critical_interrupt : 1; + uint64_t spare : 7; + uint64_t _reserved0 : 48; +#else + uint64_t _reserved0 : 48; + uint64_t spare : 7; + uint64_t critical_interrupt : 1; + uint64_t ext_interrupt : 1; + uint64_t dbg_unconditional_event : 1; + uint64_t trace_event : 1; + uint64_t trace_disable : 1; + uint64_t oci_arb_reset : 1; + uint64_t system_reset : 1; + uint64_t chip_reset : 1; + uint64_t core_reset : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocr_and_t; + + + +typedef union ocb_ocr_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t core_reset : 1; + uint64_t chip_reset : 1; + uint64_t system_reset : 1; + uint64_t oci_arb_reset : 1; + uint64_t trace_disable : 1; + uint64_t trace_event : 1; + uint64_t dbg_unconditional_event : 1; + uint64_t ext_interrupt : 1; + uint64_t critical_interrupt : 1; + uint64_t spare : 7; + uint64_t _reserved0 : 48; +#else + uint64_t _reserved0 : 48; + uint64_t spare : 7; + uint64_t critical_interrupt : 1; + uint64_t ext_interrupt : 1; + uint64_t dbg_unconditional_event : 1; + uint64_t trace_event : 1; + uint64_t trace_disable : 1; + uint64_t oci_arb_reset : 1; + uint64_t system_reset : 1; + uint64_t chip_reset : 1; + uint64_t core_reset : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocr_or_t; + + + +typedef union ocb_ocdbg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 12; + uint64_t _reserved0 : 52; +#else + uint64_t _reserved0 : 52; + uint64_t value : 12; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocdbg_t; + + + +typedef union ocb_ocbarn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_region : 2; + uint64_t ocb_address : 27; + uint64_t reserved : 3; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t reserved : 3; + uint64_t ocb_address : 27; + uint64_t oci_region : 2; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbarn_t; + +#endif // __ASSEMBLER__ +#define OCB_OCBARN_OCI_REGION_MASK SIXTYFOUR_BIT_CONSTANT(0xc000000000000000) +#define OCB_OCBARN_OCB_ADDRESS_MASK SIXTYFOUR_BIT_CONSTANT(0x3ffffff800000000) +#ifndef __ASSEMBLER__ + + +typedef union ocb_ocbcsrn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pull_read_underflow : 1; + uint64_t push_write_overflow : 1; + uint64_t pull_read_underflow_en : 1; + uint64_t push_write_overflow_en : 1; + uint64_t ocb_stream_mode : 1; + uint64_t ocb_stream_type : 1; + uint64_t reserved1 : 2; + uint64_t ocb_oci_timeout : 1; + uint64_t ocb_oci_read_data_parity : 1; + uint64_t ocb_oci_slave_error : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_pib_data_parity_err : 1; + uint64_t reserved2 : 1; + uint64_t ocb_fsm_err : 1; + uint64_t _reserved0 : 49; +#else + uint64_t _reserved0 : 49; + uint64_t ocb_fsm_err : 1; + uint64_t reserved2 : 1; + uint64_t ocb_pib_data_parity_err : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_oci_slave_error : 1; + uint64_t ocb_oci_read_data_parity : 1; + uint64_t ocb_oci_timeout : 1; + uint64_t reserved1 : 2; + uint64_t ocb_stream_type : 1; + uint64_t ocb_stream_mode : 1; + uint64_t push_write_overflow_en : 1; + uint64_t pull_read_underflow_en : 1; + uint64_t push_write_overflow : 1; + uint64_t pull_read_underflow : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbcsrn_t; + +#endif // __ASSEMBLER__ +#define OCB_OCBCSRN_PULL_READ_UNDERFLOW SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define OCB_OCBCSRN_PUSH_WRITE_OVERFLOW SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#define OCB_OCBCSRN_PULL_READ_UNDERFLOW_EN SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) +#define OCB_OCBCSRN_PUSH_WRITE_OVERFLOW_EN SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) +#define OCB_OCBCSRN_OCB_STREAM_MODE SIXTYFOUR_BIT_CONSTANT(0x0800000000000000) +#define OCB_OCBCSRN_OCB_STREAM_TYPE SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) +#define OCB_OCBCSRN_OCB_OCI_TIMEOUT SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) +#define OCB_OCBCSRN_OCB_OCI_READ_DATA_PARITY SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) +#define OCB_OCBCSRN_OCB_OCI_SLAVE_ERROR SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) +#define OCB_OCBCSRN_OCB_PIB_ADDR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) +#define OCB_OCBCSRN_OCB_PIB_DATA_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) +#define OCB_OCBCSRN_OCB_FSM_ERR SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) +#ifndef __ASSEMBLER__ + + +typedef union ocb_ocbcsrn_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pull_read_underflow : 1; + uint64_t push_write_overflow : 1; + uint64_t pull_read_underflow_en : 1; + uint64_t push_write_overflow_en : 1; + uint64_t ocb_stream_mode : 1; + uint64_t ocb_stream_type : 1; + uint64_t reserved1 : 2; + uint64_t ocb_oci_timeout : 1; + uint64_t ocb_oci_read_data_parity : 1; + uint64_t ocb_oci_slave_error : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_pib_data_parity_err : 1; + uint64_t reserved2 : 1; + uint64_t ocb_fsm_err : 1; + uint64_t _reserved0 : 49; +#else + uint64_t _reserved0 : 49; + uint64_t ocb_fsm_err : 1; + uint64_t reserved2 : 1; + uint64_t ocb_pib_data_parity_err : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_oci_slave_error : 1; + uint64_t ocb_oci_read_data_parity : 1; + uint64_t ocb_oci_timeout : 1; + uint64_t reserved1 : 2; + uint64_t ocb_stream_type : 1; + uint64_t ocb_stream_mode : 1; + uint64_t push_write_overflow_en : 1; + uint64_t pull_read_underflow_en : 1; + uint64_t push_write_overflow : 1; + uint64_t pull_read_underflow : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbcsrn_and_t; + + + +typedef union ocb_ocbcsrn_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pull_read_underflow : 1; + uint64_t push_write_overflow : 1; + uint64_t pull_read_underflow_en : 1; + uint64_t push_write_overflow_en : 1; + uint64_t ocb_stream_mode : 1; + uint64_t ocb_stream_type : 1; + uint64_t reserved1 : 2; + uint64_t ocb_oci_timeout : 1; + uint64_t ocb_oci_read_data_parity : 1; + uint64_t ocb_oci_slave_error : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_pib_data_parity_err : 1; + uint64_t reserved2 : 1; + uint64_t ocb_fsm_err : 1; + uint64_t _reserved0 : 49; +#else + uint64_t _reserved0 : 49; + uint64_t ocb_fsm_err : 1; + uint64_t reserved2 : 1; + uint64_t ocb_pib_data_parity_err : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_oci_slave_error : 1; + uint64_t ocb_oci_read_data_parity : 1; + uint64_t ocb_oci_timeout : 1; + uint64_t reserved1 : 2; + uint64_t ocb_stream_type : 1; + uint64_t ocb_stream_mode : 1; + uint64_t push_write_overflow_en : 1; + uint64_t pull_read_underflow_en : 1; + uint64_t push_write_overflow : 1; + uint64_t pull_read_underflow : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbcsrn_or_t; + + + +typedef union ocb_ocbesrn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t ocb_error_addr : 32; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t ocb_error_addr : 32; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbesrn_t; + + + +typedef union ocb_ocbdrn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t ocb_data : 64; +#else + uint64_t ocb_data : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_ocbdrn_t; + + + +typedef union ocb_osbcr { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t occ_block_unsecure_masters : 1; + uint64_t _reserved0 : 63; +#else + uint64_t _reserved0 : 63; + uint64_t occ_block_unsecure_masters : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_osbcr_t; + + + +typedef union ocb_otdcr { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t trace_bus_en : 1; + uint64_t ocb_trace_mux_sel : 1; + uint64_t occ_trace_mux_sel : 2; + uint64_t oci_trace_mux_sel : 4; + uint64_t _reserved0 : 56; +#else + uint64_t _reserved0 : 56; + uint64_t oci_trace_mux_sel : 4; + uint64_t occ_trace_mux_sel : 2; + uint64_t ocb_trace_mux_sel : 1; + uint64_t trace_bus_en : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_otdcr_t; + + + +typedef union ocb_oppcinj { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_err_inj_dcu : 1; + uint64_t oci_err_inj_icu : 1; + uint64_t oci_err_inj_ce_ue : 1; + uint64_t oci_err_inj_singl_cont : 1; + uint64_t _reserved0 : 60; +#else + uint64_t _reserved0 : 60; + uint64_t oci_err_inj_singl_cont : 1; + uint64_t oci_err_inj_ce_ue : 1; + uint64_t oci_err_inj_icu : 1; + uint64_t oci_err_inj_dcu : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_oppcinj_t; + + + +typedef union ocb_occlfir { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t occ_fw0 : 1; + uint64_t occ_fw1 : 1; + uint64_t occ_fw2 : 1; + uint64_t occ_fw3 : 1; + uint64_t pmc_pore_sw_malf : 1; + uint64_t pmc_occ_hb_malf : 1; + uint64_t pore_gpe0_fatal_err : 1; + uint64_t pore_gpe1_fatal_err : 1; + uint64_t ocb_error : 1; + uint64_t pmc_error : 1; + uint64_t srt_ue : 1; + uint64_t srt_ce : 1; + uint64_t srt_read_error : 1; + uint64_t srt_write_error : 1; + uint64_t srt_oci_write_data_parity : 1; + uint64_t srt_oci_be_parity_err : 1; + uint64_t srt_oci_addr_parity_err : 1; + uint64_t pore_sw_error_err : 1; + uint64_t pore_gpe0_error_err : 1; + uint64_t pore_gpe1_error_err : 1; + uint64_t external_trap : 1; + uint64_t ppc405_core_reset : 1; + uint64_t ppc405_chip_reset : 1; + uint64_t ppc405_system_reset : 1; + uint64_t ppc405_dbgmsrwe : 1; + uint64_t ppc405_dbgstopack : 1; + uint64_t ocb_db_oci_timeout : 1; + uint64_t ocb_db_oci_read_data_parity : 1; + uint64_t ocb_db_oci_slave_error : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_db_pib_data_parity_err : 1; + uint64_t ocb_idc0_error : 1; + uint64_t ocb_idc1_error : 1; + uint64_t ocb_idc2_error : 1; + uint64_t ocb_idc3_error : 1; + uint64_t srt_fsm_err : 1; + uint64_t jtagacc_err : 1; + uint64_t ocb_dw_err : 1; + uint64_t c405_ecc_ue : 1; + uint64_t c405_ecc_ce : 1; + uint64_t c405_oci_machinecheck : 1; + uint64_t sram_spare_direct_error0 : 1; + uint64_t sram_spare_direct_error1 : 1; + uint64_t sram_spare_direct_error2 : 1; + uint64_t sram_spare_direct_error3 : 1; + uint64_t slw_ocislv_err : 1; + uint64_t gpe_ocislv_err : 1; + uint64_t ocb_ocislv_err : 1; + uint64_t c405icu_m_timeout : 1; + uint64_t c405dcu_m_timeout : 1; + uint64_t spare_fir : 12; + uint64_t fir_parity_err_dup : 1; + uint64_t fir_parity_err : 1; +#else + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err_dup : 1; + uint64_t spare_fir : 12; + uint64_t c405dcu_m_timeout : 1; + uint64_t c405icu_m_timeout : 1; + uint64_t ocb_ocislv_err : 1; + uint64_t gpe_ocislv_err : 1; + uint64_t slw_ocislv_err : 1; + uint64_t sram_spare_direct_error3 : 1; + uint64_t sram_spare_direct_error2 : 1; + uint64_t sram_spare_direct_error1 : 1; + uint64_t sram_spare_direct_error0 : 1; + uint64_t c405_oci_machinecheck : 1; + uint64_t c405_ecc_ce : 1; + uint64_t c405_ecc_ue : 1; + uint64_t ocb_dw_err : 1; + uint64_t jtagacc_err : 1; + uint64_t srt_fsm_err : 1; + uint64_t ocb_idc3_error : 1; + uint64_t ocb_idc2_error : 1; + uint64_t ocb_idc1_error : 1; + uint64_t ocb_idc0_error : 1; + uint64_t ocb_db_pib_data_parity_err : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_db_oci_slave_error : 1; + uint64_t ocb_db_oci_read_data_parity : 1; + uint64_t ocb_db_oci_timeout : 1; + uint64_t ppc405_dbgstopack : 1; + uint64_t ppc405_dbgmsrwe : 1; + uint64_t ppc405_system_reset : 1; + uint64_t ppc405_chip_reset : 1; + uint64_t ppc405_core_reset : 1; + uint64_t external_trap : 1; + uint64_t pore_gpe1_error_err : 1; + uint64_t pore_gpe0_error_err : 1; + uint64_t pore_sw_error_err : 1; + uint64_t srt_oci_addr_parity_err : 1; + uint64_t srt_oci_be_parity_err : 1; + uint64_t srt_oci_write_data_parity : 1; + uint64_t srt_write_error : 1; + uint64_t srt_read_error : 1; + uint64_t srt_ce : 1; + uint64_t srt_ue : 1; + uint64_t pmc_error : 1; + uint64_t ocb_error : 1; + uint64_t pore_gpe1_fatal_err : 1; + uint64_t pore_gpe0_fatal_err : 1; + uint64_t pmc_occ_hb_malf : 1; + uint64_t pmc_pore_sw_malf : 1; + uint64_t occ_fw3 : 1; + uint64_t occ_fw2 : 1; + uint64_t occ_fw1 : 1; + uint64_t occ_fw0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfir_t; + +#endif // __ASSEMBLER__ +#define OCB_OCCLFIR_OCC_FW0 SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define OCB_OCCLFIR_OCC_FW1 SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#define OCB_OCCLFIR_OCC_FW2 SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) +#define OCB_OCCLFIR_OCC_FW3 SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) +#define OCB_OCCLFIR_PMC_PORE_SW_MALF SIXTYFOUR_BIT_CONSTANT(0x0800000000000000) +#define OCB_OCCLFIR_PMC_OCC_HB_MALF SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) +#define OCB_OCCLFIR_PORE_GPE0_FATAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0200000000000000) +#define OCB_OCCLFIR_PORE_GPE1_FATAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) +#define OCB_OCCLFIR_OCB_ERROR SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) +#define OCB_OCCLFIR_PMC_ERROR SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) +#define OCB_OCCLFIR_SRT_UE SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) +#define OCB_OCCLFIR_SRT_CE SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) +#define OCB_OCCLFIR_SRT_READ_ERROR SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) +#define OCB_OCCLFIR_SRT_WRITE_ERROR SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) +#define OCB_OCCLFIR_SRT_OCI_WRITE_DATA_PARITY SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) +#define OCB_OCCLFIR_SRT_OCI_BE_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0001000000000000) +#define OCB_OCCLFIR_SRT_OCI_ADDR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000800000000000) +#define OCB_OCCLFIR_PORE_SW_ERROR_ERR SIXTYFOUR_BIT_CONSTANT(0x0000400000000000) +#define OCB_OCCLFIR_PORE_GPE0_ERROR_ERR SIXTYFOUR_BIT_CONSTANT(0x0000200000000000) +#define OCB_OCCLFIR_PORE_GPE1_ERROR_ERR SIXTYFOUR_BIT_CONSTANT(0x0000100000000000) +#define OCB_OCCLFIR_EXTERNAL_TRAP SIXTYFOUR_BIT_CONSTANT(0x0000080000000000) +#define OCB_OCCLFIR_PPC405_CORE_RESET SIXTYFOUR_BIT_CONSTANT(0x0000040000000000) +#define OCB_OCCLFIR_PPC405_CHIP_RESET SIXTYFOUR_BIT_CONSTANT(0x0000020000000000) +#define OCB_OCCLFIR_PPC405_SYSTEM_RESET SIXTYFOUR_BIT_CONSTANT(0x0000010000000000) +#define OCB_OCCLFIR_PPC405_DBGMSRWE SIXTYFOUR_BIT_CONSTANT(0x0000008000000000) +#define OCB_OCCLFIR_PPC405_DBGSTOPACK SIXTYFOUR_BIT_CONSTANT(0x0000004000000000) +#define OCB_OCCLFIR_OCB_DB_OCI_TIMEOUT SIXTYFOUR_BIT_CONSTANT(0x0000002000000000) +#define OCB_OCCLFIR_OCB_DB_OCI_READ_DATA_PARITY SIXTYFOUR_BIT_CONSTANT(0x0000001000000000) +#define OCB_OCCLFIR_OCB_DB_OCI_SLAVE_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000800000000) +#define OCB_OCCLFIR_OCB_PIB_ADDR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000400000000) +#define OCB_OCCLFIR_OCB_DB_PIB_DATA_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000200000000) +#define OCB_OCCLFIR_OCB_IDC0_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000100000000) +#define OCB_OCCLFIR_OCB_IDC1_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000080000000) +#define OCB_OCCLFIR_OCB_IDC2_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000040000000) +#define OCB_OCCLFIR_OCB_IDC3_ERROR SIXTYFOUR_BIT_CONSTANT(0x0000000020000000) +#define OCB_OCCLFIR_SRT_FSM_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000010000000) +#define OCB_OCCLFIR_JTAGACC_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000008000000) +#define OCB_OCCLFIR_OCB_DW_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000004000000) +#define OCB_OCCLFIR_C405_ECC_UE SIXTYFOUR_BIT_CONSTANT(0x0000000002000000) +#define OCB_OCCLFIR_C405_ECC_CE SIXTYFOUR_BIT_CONSTANT(0x0000000001000000) +#define OCB_OCCLFIR_C405_OCI_MACHINECHECK SIXTYFOUR_BIT_CONSTANT(0x0000000000800000) +#define OCB_OCCLFIR_SRAM_SPARE_DIRECT_ERROR0 SIXTYFOUR_BIT_CONSTANT(0x0000000000400000) +#define OCB_OCCLFIR_SRAM_SPARE_DIRECT_ERROR1 SIXTYFOUR_BIT_CONSTANT(0x0000000000200000) +#define OCB_OCCLFIR_SRAM_SPARE_DIRECT_ERROR2 SIXTYFOUR_BIT_CONSTANT(0x0000000000100000) +#define OCB_OCCLFIR_SRAM_SPARE_DIRECT_ERROR3 SIXTYFOUR_BIT_CONSTANT(0x0000000000080000) +#define OCB_OCCLFIR_SLW_OCISLV_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000040000) +#define OCB_OCCLFIR_GPE_OCISLV_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000020000) +#define OCB_OCCLFIR_OCB_OCISLV_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000010000) +#define OCB_OCCLFIR_C405ICU_M_TIMEOUT SIXTYFOUR_BIT_CONSTANT(0x0000000000008000) +#define OCB_OCCLFIR_C405DCU_M_TIMEOUT SIXTYFOUR_BIT_CONSTANT(0x0000000000004000) +#define OCB_OCCLFIR_SPARE_FIR_MASK SIXTYFOUR_BIT_CONSTANT(0x0000000000003ffc) +#define OCB_OCCLFIR_FIR_PARITY_ERR_DUP SIXTYFOUR_BIT_CONSTANT(0x0000000000000002) +#define OCB_OCCLFIR_FIR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000000001) +#ifndef __ASSEMBLER__ + + +typedef union ocb_occlfir_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t occ_fw0 : 1; + uint64_t occ_fw1 : 1; + uint64_t occ_fw2 : 1; + uint64_t occ_fw3 : 1; + uint64_t pmc_pore_sw_malf : 1; + uint64_t pmc_occ_hb_malf : 1; + uint64_t pore_gpe0_fatal_err : 1; + uint64_t pore_gpe1_fatal_err : 1; + uint64_t ocb_error : 1; + uint64_t pmc_error : 1; + uint64_t srt_ue : 1; + uint64_t srt_ce : 1; + uint64_t srt_read_error : 1; + uint64_t srt_write_error : 1; + uint64_t srt_oci_write_data_parity : 1; + uint64_t srt_oci_be_parity_err : 1; + uint64_t srt_oci_addr_parity_err : 1; + uint64_t pore_sw_error_err : 1; + uint64_t pore_gpe0_error_err : 1; + uint64_t pore_gpe1_error_err : 1; + uint64_t external_trap : 1; + uint64_t ppc405_core_reset : 1; + uint64_t ppc405_chip_reset : 1; + uint64_t ppc405_system_reset : 1; + uint64_t ppc405_dbgmsrwe : 1; + uint64_t ppc405_dbgstopack : 1; + uint64_t ocb_db_oci_timeout : 1; + uint64_t ocb_db_oci_read_data_parity : 1; + uint64_t ocb_db_oci_slave_error : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_db_pib_data_parity_err : 1; + uint64_t ocb_idc0_error : 1; + uint64_t ocb_idc1_error : 1; + uint64_t ocb_idc2_error : 1; + uint64_t ocb_idc3_error : 1; + uint64_t srt_fsm_err : 1; + uint64_t jtagacc_err : 1; + uint64_t ocb_dw_err : 1; + uint64_t c405_ecc_ue : 1; + uint64_t c405_ecc_ce : 1; + uint64_t c405_oci_machinecheck : 1; + uint64_t sram_spare_direct_error0 : 1; + uint64_t sram_spare_direct_error1 : 1; + uint64_t sram_spare_direct_error2 : 1; + uint64_t sram_spare_direct_error3 : 1; + uint64_t slw_ocislv_err : 1; + uint64_t gpe_ocislv_err : 1; + uint64_t ocb_ocislv_err : 1; + uint64_t c405icu_m_timeout : 1; + uint64_t c405dcu_m_timeout : 1; + uint64_t spare_fir : 12; + uint64_t fir_parity_err_dup : 1; + uint64_t fir_parity_err : 1; +#else + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err_dup : 1; + uint64_t spare_fir : 12; + uint64_t c405dcu_m_timeout : 1; + uint64_t c405icu_m_timeout : 1; + uint64_t ocb_ocislv_err : 1; + uint64_t gpe_ocislv_err : 1; + uint64_t slw_ocislv_err : 1; + uint64_t sram_spare_direct_error3 : 1; + uint64_t sram_spare_direct_error2 : 1; + uint64_t sram_spare_direct_error1 : 1; + uint64_t sram_spare_direct_error0 : 1; + uint64_t c405_oci_machinecheck : 1; + uint64_t c405_ecc_ce : 1; + uint64_t c405_ecc_ue : 1; + uint64_t ocb_dw_err : 1; + uint64_t jtagacc_err : 1; + uint64_t srt_fsm_err : 1; + uint64_t ocb_idc3_error : 1; + uint64_t ocb_idc2_error : 1; + uint64_t ocb_idc1_error : 1; + uint64_t ocb_idc0_error : 1; + uint64_t ocb_db_pib_data_parity_err : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_db_oci_slave_error : 1; + uint64_t ocb_db_oci_read_data_parity : 1; + uint64_t ocb_db_oci_timeout : 1; + uint64_t ppc405_dbgstopack : 1; + uint64_t ppc405_dbgmsrwe : 1; + uint64_t ppc405_system_reset : 1; + uint64_t ppc405_chip_reset : 1; + uint64_t ppc405_core_reset : 1; + uint64_t external_trap : 1; + uint64_t pore_gpe1_error_err : 1; + uint64_t pore_gpe0_error_err : 1; + uint64_t pore_sw_error_err : 1; + uint64_t srt_oci_addr_parity_err : 1; + uint64_t srt_oci_be_parity_err : 1; + uint64_t srt_oci_write_data_parity : 1; + uint64_t srt_write_error : 1; + uint64_t srt_read_error : 1; + uint64_t srt_ce : 1; + uint64_t srt_ue : 1; + uint64_t pmc_error : 1; + uint64_t ocb_error : 1; + uint64_t pore_gpe1_fatal_err : 1; + uint64_t pore_gpe0_fatal_err : 1; + uint64_t pmc_occ_hb_malf : 1; + uint64_t pmc_pore_sw_malf : 1; + uint64_t occ_fw3 : 1; + uint64_t occ_fw2 : 1; + uint64_t occ_fw1 : 1; + uint64_t occ_fw0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfir_and_t; + + + +typedef union ocb_occlfir_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t occ_fw0 : 1; + uint64_t occ_fw1 : 1; + uint64_t occ_fw2 : 1; + uint64_t occ_fw3 : 1; + uint64_t pmc_pore_sw_malf : 1; + uint64_t pmc_occ_hb_malf : 1; + uint64_t pore_gpe0_fatal_err : 1; + uint64_t pore_gpe1_fatal_err : 1; + uint64_t ocb_error : 1; + uint64_t pmc_error : 1; + uint64_t srt_ue : 1; + uint64_t srt_ce : 1; + uint64_t srt_read_error : 1; + uint64_t srt_write_error : 1; + uint64_t srt_oci_write_data_parity : 1; + uint64_t srt_oci_be_parity_err : 1; + uint64_t srt_oci_addr_parity_err : 1; + uint64_t pore_sw_error_err : 1; + uint64_t pore_gpe0_error_err : 1; + uint64_t pore_gpe1_error_err : 1; + uint64_t external_trap : 1; + uint64_t ppc405_core_reset : 1; + uint64_t ppc405_chip_reset : 1; + uint64_t ppc405_system_reset : 1; + uint64_t ppc405_dbgmsrwe : 1; + uint64_t ppc405_dbgstopack : 1; + uint64_t ocb_db_oci_timeout : 1; + uint64_t ocb_db_oci_read_data_parity : 1; + uint64_t ocb_db_oci_slave_error : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_db_pib_data_parity_err : 1; + uint64_t ocb_idc0_error : 1; + uint64_t ocb_idc1_error : 1; + uint64_t ocb_idc2_error : 1; + uint64_t ocb_idc3_error : 1; + uint64_t srt_fsm_err : 1; + uint64_t jtagacc_err : 1; + uint64_t ocb_dw_err : 1; + uint64_t c405_ecc_ue : 1; + uint64_t c405_ecc_ce : 1; + uint64_t c405_oci_machinecheck : 1; + uint64_t sram_spare_direct_error0 : 1; + uint64_t sram_spare_direct_error1 : 1; + uint64_t sram_spare_direct_error2 : 1; + uint64_t sram_spare_direct_error3 : 1; + uint64_t slw_ocislv_err : 1; + uint64_t gpe_ocislv_err : 1; + uint64_t ocb_ocislv_err : 1; + uint64_t c405icu_m_timeout : 1; + uint64_t c405dcu_m_timeout : 1; + uint64_t spare_fir : 12; + uint64_t fir_parity_err_dup : 1; + uint64_t fir_parity_err : 1; +#else + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err_dup : 1; + uint64_t spare_fir : 12; + uint64_t c405dcu_m_timeout : 1; + uint64_t c405icu_m_timeout : 1; + uint64_t ocb_ocislv_err : 1; + uint64_t gpe_ocislv_err : 1; + uint64_t slw_ocislv_err : 1; + uint64_t sram_spare_direct_error3 : 1; + uint64_t sram_spare_direct_error2 : 1; + uint64_t sram_spare_direct_error1 : 1; + uint64_t sram_spare_direct_error0 : 1; + uint64_t c405_oci_machinecheck : 1; + uint64_t c405_ecc_ce : 1; + uint64_t c405_ecc_ue : 1; + uint64_t ocb_dw_err : 1; + uint64_t jtagacc_err : 1; + uint64_t srt_fsm_err : 1; + uint64_t ocb_idc3_error : 1; + uint64_t ocb_idc2_error : 1; + uint64_t ocb_idc1_error : 1; + uint64_t ocb_idc0_error : 1; + uint64_t ocb_db_pib_data_parity_err : 1; + uint64_t ocb_pib_addr_parity_err : 1; + uint64_t ocb_db_oci_slave_error : 1; + uint64_t ocb_db_oci_read_data_parity : 1; + uint64_t ocb_db_oci_timeout : 1; + uint64_t ppc405_dbgstopack : 1; + uint64_t ppc405_dbgmsrwe : 1; + uint64_t ppc405_system_reset : 1; + uint64_t ppc405_chip_reset : 1; + uint64_t ppc405_core_reset : 1; + uint64_t external_trap : 1; + uint64_t pore_gpe1_error_err : 1; + uint64_t pore_gpe0_error_err : 1; + uint64_t pore_sw_error_err : 1; + uint64_t srt_oci_addr_parity_err : 1; + uint64_t srt_oci_be_parity_err : 1; + uint64_t srt_oci_write_data_parity : 1; + uint64_t srt_write_error : 1; + uint64_t srt_read_error : 1; + uint64_t srt_ce : 1; + uint64_t srt_ue : 1; + uint64_t pmc_error : 1; + uint64_t ocb_error : 1; + uint64_t pore_gpe1_fatal_err : 1; + uint64_t pore_gpe0_fatal_err : 1; + uint64_t pmc_occ_hb_malf : 1; + uint64_t pmc_pore_sw_malf : 1; + uint64_t occ_fw3 : 1; + uint64_t occ_fw2 : 1; + uint64_t occ_fw1 : 1; + uint64_t occ_fw0 : 1; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfir_or_t; + + + +typedef union ocb_occlfirmask { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfirmask_t; + + + +typedef union ocb_occlfirmask_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfirmask_and_t; + + + +typedef union ocb_occlfirmask_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfirmask_or_t; + + + +typedef union ocb_occlfiract0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfiract0_t; + + + +typedef union ocb_occlfiract1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} ocb_occlfiract1_t; + + + +typedef union ocb_occerrrpt { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t sram_cerrrpt : 10; + uint64_t jtagacc_cerrrpt : 6; + uint64_t c405_dcu_ecc_ue_cerrrpt : 1; + uint64_t c405_dcu_ecc_ce_cerrrpt : 1; + uint64_t c405_icu_ecc_ue_cerrrpt : 1; + uint64_t c405_icu_ecc_ce_cerrrpt : 1; + uint64_t slw_ocislv_err : 7; + uint64_t gpe_ocislv_err : 7; + uint64_t ocb_ocislv_err : 6; + uint64_t _reserved0 : 24; +#else + uint64_t _reserved0 : 24; + uint64_t ocb_ocislv_err : 6; + uint64_t gpe_ocislv_err : 7; + uint64_t slw_ocislv_err : 7; + uint64_t c405_icu_ecc_ce_cerrrpt : 1; + uint64_t c405_icu_ecc_ue_cerrrpt : 1; + uint64_t c405_dcu_ecc_ce_cerrrpt : 1; + uint64_t c405_dcu_ecc_ue_cerrrpt : 1; + uint64_t jtagacc_cerrrpt : 6; + uint64_t sram_cerrrpt : 10; +#endif // _BIG_ENDIAN + } fields; +} ocb_occerrrpt_t; + + + +typedef union ocb_scan_dummy_1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 48; + uint64_t value : 16; +#else + uint64_t value : 16; + uint64_t _reserved0 : 48; +#endif // _BIG_ENDIAN + } fields; +} ocb_scan_dummy_1_t; + + + +typedef union ocb_scan_dummy_2 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 63; + uint64_t value : 1; +#else + uint64_t value : 1; + uint64_t _reserved0 : 63; +#endif // _BIG_ENDIAN + } fields; +} ocb_scan_dummy_2_t; + + +#endif // __ASSEMBLER__ +#endif // __OCB_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/ocb_register_addresses.h b/src/ssx/pgp/registers/ocb_register_addresses.h new file mode 100755 index 0000000..3290e59 --- /dev/null +++ b/src/ssx/pgp/registers/ocb_register_addresses.h @@ -0,0 +1,148 @@ +#ifndef __OCB_REGISTER_ADDRESSES_H__ +#define __OCB_REGISTER_ADDRESSES_H__ + +// $Id: ocb_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/ocb_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file ocb_register_addresses.h +/// \brief Symbolic addresses for the OCB unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define OCB_OCI_BASE 0x40050000 +#define OCB_OITR0 0x40050040 +#define OCB_OIEPR0 0x40050048 +#define OCB_OCIR0 0x40050050 +#define OCB_ONISR0 0x40050058 +#define OCB_OUDER0 0x40050060 +#define OCB_OCISR0 0x40050068 +#define OCB_ODHER0 0x40050070 +#define OCB_OISR0 0x40050000 +#define OCB_OISR0_AND 0x40050008 +#define OCB_OISR0_OR 0x40050010 +#define OCB_OIMR0 0x40050020 +#define OCB_OIMR0_AND 0x40050028 +#define OCB_OIMR0_OR 0x40050030 +#define OCB_OITR1 0x400500c0 +#define OCB_OIEPR1 0x400500c8 +#define OCB_OCIR1 0x400500d0 +#define OCB_ONISR1 0x400500d8 +#define OCB_OUDER1 0x400500e0 +#define OCB_OCISR1 0x400500e8 +#define OCB_ODHER1 0x400500f0 +#define OCB_OISR1 0x40050080 +#define OCB_OISR1_AND 0x40050088 +#define OCB_OISR1_OR 0x40050090 +#define OCB_OIMR1 0x400500a0 +#define OCB_OIMR1_AND 0x400500a8 +#define OCB_OIMR1_OR 0x400500b0 +#define OCB_OCCMISC 0x40050100 +#define OCB_OCCMISC_AND 0x40050108 +#define OCB_OCCMISC_OR 0x40050110 +#define OCB_OTRN(n) (OCB_OTR0 + ((OCB_OTR1 - OCB_OTR0) * (n))) +#define OCB_OTR0 0x40050800 +#define OCB_OTR1 0x40050808 +#define OCB_OHTMCR 0x40050118 +#define OCB_OEHDR 0x40050120 +#define OCB_OCBSLBRN(n) (OCB_OCBSLBR0 + ((OCB_OCBSLBR1 - OCB_OCBSLBR0) * (n))) +#define OCB_OCBSLBR0 0x40051000 +#define OCB_OCBSLBR1 0x40051080 +#define OCB_OCBSLBR2 0x40051100 +#define OCB_OCBSHBRN(n) (OCB_OCBSHBR0 + ((OCB_OCBSHBR1 - OCB_OCBSHBR0) * (n))) +#define OCB_OCBSHBR0 0x40051018 +#define OCB_OCBSHBR1 0x40051098 +#define OCB_OCBSHBR2 0x40051118 +#define OCB_OCBSLCSN(n) (OCB_OCBSLCS0 + ((OCB_OCBSLCS1 - OCB_OCBSLCS0) * (n))) +#define OCB_OCBSLCS0 0x40051008 +#define OCB_OCBSLCS1 0x40051088 +#define OCB_OCBSLCS2 0x40051108 +#define OCB_OCBSHCSN(n) (OCB_OCBSHCS0 + ((OCB_OCBSHCS1 - OCB_OCBSHCS0) * (n))) +#define OCB_OCBSHCS0 0x40051020 +#define OCB_OCBSHCS1 0x400510a0 +#define OCB_OCBSHCS2 0x40051120 +#define OCB_OCBSLIN(n) (OCB_OCBSLI0 + ((OCB_OCBSLI1 - OCB_OCBSLI0) * (n))) +#define OCB_OCBSLI0 0x40051010 +#define OCB_OCBSLI1 0x40051090 +#define OCB_OCBSLI2 0x40051110 +#define OCB_OCBSHIN(n) (OCB_OCBSHI0 + ((OCB_OCBSHI1 - OCB_OCBSHI0) * (n))) +#define OCB_OCBSHI0 0x40051028 +#define OCB_OCBSHI1 0x400510a8 +#define OCB_OCBSHI2 0x40051128 +#define OCB_OCBSESN(n) (OCB_OCBSES0 + ((OCB_OCBSES1 - OCB_OCBSES0) * (n))) +#define OCB_OCBSES0 0x40051030 +#define OCB_OCBSES1 0x400510b0 +#define OCB_OCBSES2 0x40051130 +#define OCB_OCBICRN(n) (OCB_OCBICR0 + ((OCB_OCBICR1 - OCB_OCBICR0) * (n))) +#define OCB_OCBICR0 0x40051038 +#define OCB_OCBICR1 0x400510b8 +#define OCB_OCBICR2 0x40051138 +#define OCB_OCBLWCRN(n) (OCB_OCBLWCR0 + ((OCB_OCBLWCR1 - OCB_OCBLWCR0) * (n))) +#define OCB_OCBLWCR0 0x40051040 +#define OCB_OCBLWCR1 0x400510c0 +#define OCB_OCBLWCR2 0x40051140 +#define OCB_OCBLWSRN(n) (OCB_OCBLWSR0 + ((OCB_OCBLWSR1 - OCB_OCBLWSR0) * (n))) +#define OCB_OCBLWSR0 0x40051050 +#define OCB_OCBLWSR1 0x400510d0 +#define OCB_OCBLWSR2 0x40051150 +#define OCB_OCBLWSBRN(n) (OCB_OCBLWSBR0 + ((OCB_OCBLWSBR1 - OCB_OCBLWSBR0) * (n))) +#define OCB_OCBLWSBR0 0x40051060 +#define OCB_OCBLWSBR1 0x400510e0 +#define OCB_OCBLWSBR2 0x40051160 +#define OCB_OCICHSW 0x40050128 +#define OCB_PIB_BASE 0x0006a000 +#define OCB_OCR 0x0006b000 +#define OCB_OCR_AND 0x0006b001 +#define OCB_OCR_OR 0x0006b002 +#define OCB_OCDBG 0x0006b003 +#define OCB_OCBARN(n) (OCB_OCBAR0 + ((OCB_OCBAR1 - OCB_OCBAR0) * (n))) +#define OCB_OCBAR0 0x0006b010 +#define OCB_OCBAR1 0x0006b030 +#define OCB_OCBAR2 0x0006b050 +#define OCB_OCBAR3 0x0006b070 +#define OCB_OCBCSRN(n) (OCB_OCBCSR0 + ((OCB_OCBCSR1 - OCB_OCBCSR0) * (n))) +#define OCB_OCBCSR0 0x0006b011 +#define OCB_OCBCSR1 0x0006b031 +#define OCB_OCBCSR2 0x0006b051 +#define OCB_OCBCSR3 0x0006b071 +#define OCB_OCBCSRN_AND(n) (OCB_OCBCSR0_AND + ((OCB_OCBCSR1_AND - OCB_OCBCSR0_AND) * (n))) +#define OCB_OCBCSR0_AND 0x0006b012 +#define OCB_OCBCSR1_AND 0x0006b032 +#define OCB_OCBCSR2_AND 0x0006b052 +#define OCB_OCBCSR3_AND 0x0006b072 +#define OCB_OCBCSRN_OR(n) (OCB_OCBCSR0_OR + ((OCB_OCBCSR1_OR - OCB_OCBCSR0_OR) * (n))) +#define OCB_OCBCSR0_OR 0x0006b013 +#define OCB_OCBCSR1_OR 0x0006b033 +#define OCB_OCBCSR2_OR 0x0006b053 +#define OCB_OCBCSR3_OR 0x0006b073 +#define OCB_OCBESRN(n) (OCB_OCBESR0 + ((OCB_OCBESR1 - OCB_OCBESR0) * (n))) +#define OCB_OCBESR0 0x0006b014 +#define OCB_OCBESR1 0x0006b034 +#define OCB_OCBESR2 0x0006b054 +#define OCB_OCBESR3 0x0006b074 +#define OCB_OCBDRN(n) (OCB_OCBDR0 + ((OCB_OCBDR1 - OCB_OCBDR0) * (n))) +#define OCB_OCBDR0 0x0006b015 +#define OCB_OCBDR1 0x0006b035 +#define OCB_OCBDR2 0x0006b055 +#define OCB_OCBDR3 0x0006b075 +#define OCB_OSBCR 0x0006b100 +#define OCB_OTDCR 0x0006b110 +#define OCB_OPPCINJ 0x0006b111 +#define OCB_FIRPIB_BASE 0x01010800 +#define OCB_OCCLFIR 0x01010800 +#define OCB_OCCLFIR_AND 0x01010801 +#define OCB_OCCLFIR_OR 0x01010802 +#define OCB_OCCLFIRMASK 0x01010803 +#define OCB_OCCLFIRMASK_AND 0x01010804 +#define OCB_OCCLFIRMASK_OR 0x01010805 +#define OCB_OCCLFIRACT0 0x01010806 +#define OCB_OCCLFIRACT1 0x01010807 +#define OCB_OCCERRRPT 0x0101080a + +#endif // __OCB_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/oha_firmware_registers.h b/src/ssx/pgp/registers/oha_firmware_registers.h new file mode 100755 index 0000000..cba1500 --- /dev/null +++ b/src/ssx/pgp/registers/oha_firmware_registers.h @@ -0,0 +1,1248 @@ +#ifndef __OHA_FIRMWARE_REGISTERS_H__ +#define __OHA_FIRMWARE_REGISTERS_H__ + +// $Id: oha_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/oha_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file oha_firmware_registers.h +/// \brief C register structs for the OHA unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union oha_activity_sample_mode_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t enable_activity_sampling : 1; + uint64_t enable_ppt_trace : 1; + uint64_t l2_act_count_is_free_running : 1; + uint64_t l3_act_count_is_free_running : 1; + uint64_t activity_sample_l2l3_enable : 1; + uint64_t core_activity_sample_enable : 1; + uint64_t disable_activity_proxy_reset : 1; + uint64_t power_proxy_activity_range_select_vcs : 5; + uint64_t power_proxy_activity_range_select_vdd : 5; + uint64_t memory_activity_range_select : 4; + uint64_t avg_freq_counter_scaler : 3; + uint64_t ppt_trace_timer_match_val : 11; + uint64_t disable_ppt_int_timer_reset : 1; + uint64_t ppt_int_timer_select : 2; + uint64_t disable_ppt_cycle_counter_reset : 1; + uint64_t ppt_cycle_counter_scaler : 3; + uint64_t ppt_squash_timer_match_val : 6; + uint64_t ppt_timer_timeout_enable : 1; + uint64_t ppt_lpar_change_enable : 1; + uint64_t ppt_global_actual_change_enable : 1; + uint64_t ppt_local_voltage_change_enable : 1; + uint64_t ppt_ivrm_bypass_change_enable : 1; + uint64_t ppt_idle_entry_enable : 1; + uint64_t ppt_idle_exit_enable : 1; + uint64_t ppt_timer_timeout_priority : 1; + uint64_t ppt_lpar_change_priority : 1; + uint64_t ppt_global_actual_change_priority : 1; + uint64_t ppt_local_voltage_change_priority : 1; + uint64_t ppt_ivrm_bypass_change_priority : 1; + uint64_t ppt_idle_entry_priority : 1; + uint64_t ppt_idle_exit_priority : 1; + uint64_t ppt_legacy_mode : 1; + uint64_t _reserved0 : 1; +#else + uint64_t _reserved0 : 1; + uint64_t ppt_legacy_mode : 1; + uint64_t ppt_idle_exit_priority : 1; + uint64_t ppt_idle_entry_priority : 1; + uint64_t ppt_ivrm_bypass_change_priority : 1; + uint64_t ppt_local_voltage_change_priority : 1; + uint64_t ppt_global_actual_change_priority : 1; + uint64_t ppt_lpar_change_priority : 1; + uint64_t ppt_timer_timeout_priority : 1; + uint64_t ppt_idle_exit_enable : 1; + uint64_t ppt_idle_entry_enable : 1; + uint64_t ppt_ivrm_bypass_change_enable : 1; + uint64_t ppt_local_voltage_change_enable : 1; + uint64_t ppt_global_actual_change_enable : 1; + uint64_t ppt_lpar_change_enable : 1; + uint64_t ppt_timer_timeout_enable : 1; + uint64_t ppt_squash_timer_match_val : 6; + uint64_t ppt_cycle_counter_scaler : 3; + uint64_t disable_ppt_cycle_counter_reset : 1; + uint64_t ppt_int_timer_select : 2; + uint64_t disable_ppt_int_timer_reset : 1; + uint64_t ppt_trace_timer_match_val : 11; + uint64_t avg_freq_counter_scaler : 3; + uint64_t memory_activity_range_select : 4; + uint64_t power_proxy_activity_range_select_vdd : 5; + uint64_t power_proxy_activity_range_select_vcs : 5; + uint64_t disable_activity_proxy_reset : 1; + uint64_t core_activity_sample_enable : 1; + uint64_t activity_sample_l2l3_enable : 1; + uint64_t l3_act_count_is_free_running : 1; + uint64_t l2_act_count_is_free_running : 1; + uint64_t enable_ppt_trace : 1; + uint64_t enable_activity_sampling : 1; +#endif // _BIG_ENDIAN + } fields; +} oha_activity_sample_mode_reg_t; + + + +typedef union oha_vcs_activity_cnt_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t l2_activity_count_24bit_vcs : 24; + uint64_t l3_activity_count_24bit_vcs : 24; + uint64_t _reserved0 : 16; +#else + uint64_t _reserved0 : 16; + uint64_t l3_activity_count_24bit_vcs : 24; + uint64_t l2_activity_count_24bit_vcs : 24; +#endif // _BIG_ENDIAN + } fields; +} oha_vcs_activity_cnt_reg_t; + + + +typedef union oha_vdd_activity_cnt_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t l2_activity_count_24bit_vdd : 24; + uint64_t l3_activity_count_24bit_vdd : 24; + uint64_t _reserved0 : 16; +#else + uint64_t _reserved0 : 16; + uint64_t l3_activity_count_24bit_vdd : 24; + uint64_t l2_activity_count_24bit_vdd : 24; +#endif // _BIG_ENDIAN + } fields; +} oha_vdd_activity_cnt_reg_t; + + + +typedef union oha_low_activity_detect_mode_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t low_activity_detect_sample_enable : 1; + uint64_t low_activity_detect_timer_select_for_entry : 8; + uint64_t low_activity_detect_timer_select_for_exit : 8; + uint64_t low_activity_detect_threshold_range : 4; + uint64_t low_activity_detect_threshold_entry : 16; + uint64_t low_activity_detect_threshold_exit : 16; + uint64_t _reserved0 : 11; +#else + uint64_t _reserved0 : 11; + uint64_t low_activity_detect_threshold_exit : 16; + uint64_t low_activity_detect_threshold_entry : 16; + uint64_t low_activity_detect_threshold_range : 4; + uint64_t low_activity_detect_timer_select_for_exit : 8; + uint64_t low_activity_detect_timer_select_for_entry : 8; + uint64_t low_activity_detect_sample_enable : 1; +#endif // _BIG_ENDIAN + } fields; +} oha_low_activity_detect_mode_reg_t; + + + +typedef union oha_activity_and_frequ_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t low_activity_detect_engaged : 1; + uint64_t _reserved0 : 63; +#else + uint64_t _reserved0 : 63; + uint64_t low_activity_detect_engaged : 1; +#endif // _BIG_ENDIAN + } fields; +} oha_activity_and_frequ_reg_t; + + + +typedef union oha_counter_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t base_counter : 16; + uint64_t idle_detec_timer : 16; + uint64_t tod_count_msbs : 16; + uint64_t ppt_cycle_count_ovfl : 1; + uint64_t ppt_parity_error : 1; + uint64_t _reserved0 : 14; +#else + uint64_t _reserved0 : 14; + uint64_t ppt_parity_error : 1; + uint64_t ppt_cycle_count_ovfl : 1; + uint64_t tod_count_msbs : 16; + uint64_t idle_detec_timer : 16; + uint64_t base_counter : 16; +#endif // _BIG_ENDIAN + } fields; +} oha_counter_reg_t; + + + +typedef union oha_proxy_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t average_frequency : 32; + uint64_t special_memory_activity_cnt : 24; + uint64_t _reserved0 : 8; +#else + uint64_t _reserved0 : 8; + uint64_t special_memory_activity_cnt : 24; + uint64_t average_frequency : 32; +#endif // _BIG_ENDIAN + } fields; +} oha_proxy_reg_t; + + + +typedef union oha_proxy_legacy_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t aproxy_vdd : 16; + uint64_t aproxy_vcs : 16; + uint64_t memory_activity_cnt : 16; + uint64_t scaled_average_frequency : 16; +#else + uint64_t scaled_average_frequency : 16; + uint64_t memory_activity_cnt : 16; + uint64_t aproxy_vcs : 16; + uint64_t aproxy_vdd : 16; +#endif // _BIG_ENDIAN + } fields; +} oha_proxy_legacy_reg_t; + + + +typedef union oha_skitter_ctrl_mode_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t start_skitter_mux_sel : 3; + uint64_t stop_skitter_mux_sel : 3; + uint64_t skitter_timer_start_mux_sel : 3; + uint64_t disable_skitter_qualification_mode : 1; + uint64_t skitter_timer_enable_freerun_mode : 1; + uint64_t skitter_timer_range_select : 4; + uint64_t _reserved0 : 49; +#else + uint64_t _reserved0 : 49; + uint64_t skitter_timer_range_select : 4; + uint64_t skitter_timer_enable_freerun_mode : 1; + uint64_t disable_skitter_qualification_mode : 1; + uint64_t skitter_timer_start_mux_sel : 3; + uint64_t stop_skitter_mux_sel : 3; + uint64_t start_skitter_mux_sel : 3; +#endif // _BIG_ENDIAN + } fields; +} oha_skitter_ctrl_mode_reg_t; + + + +typedef union oha_cpm_ctrl_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t cpm_bit_sel : 2; + uint64_t cpm_bit_sel_trig_0 : 3; + uint64_t cpm_bit_sel_trig_1 : 3; + uint64_t scom_marker : 8; + uint64_t cpm_mark_select : 2; + uint64_t cpm_htm_mode : 1; + uint64_t cpm_scom_mask : 8; + uint64_t cpm_scom_mode : 2; + uint64_t cpm_data_mode : 1; + uint64_t _reserved0 : 34; +#else + uint64_t _reserved0 : 34; + uint64_t cpm_data_mode : 1; + uint64_t cpm_scom_mode : 2; + uint64_t cpm_scom_mask : 8; + uint64_t cpm_htm_mode : 1; + uint64_t cpm_mark_select : 2; + uint64_t scom_marker : 8; + uint64_t cpm_bit_sel_trig_1 : 3; + uint64_t cpm_bit_sel_trig_0 : 3; + uint64_t cpm_bit_sel : 2; +#endif // _BIG_ENDIAN + } fields; +} oha_cpm_ctrl_reg_t; + + + +typedef union oha_cpm_hist_reset_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t hist_reset : 1; + uint64_t pconly_special_wakeup : 1; + uint64_t _reserved0 : 62; +#else + uint64_t _reserved0 : 62; + uint64_t pconly_special_wakeup : 1; + uint64_t hist_reset : 1; +#endif // _BIG_ENDIAN + } fields; +} oha_cpm_hist_reset_reg_t; + +#endif // __ASSEMBLER__ +#define OHA_CPM_HIST_RESET_REG_HIST_RESET SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define OHA_CPM_HIST_RESET_REG_PCONLY_SPECIAL_WAKEUP SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#ifndef __ASSEMBLER__ + + +typedef union oha_ro_status_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t low_activity_detect_bit : 1; + uint64_t special_wakeup_completed : 1; + uint64_t architected_idle_state_from_core : 3; + uint64_t core_access_impossible : 1; + uint64_t eco_access_impossible : 1; + uint64_t spare_6bit : 6; + uint64_t current_aiss_fsm_state_vector : 7; + uint64_t eff_idle_state : 3; + uint64_t spare_1bit : 1; + uint64_t pc_tc_deep_idle_thread_state : 8; + uint64_t lpar_id : 12; + uint64_t ppt_fsm_l : 4; + uint64_t _reserved0 : 16; +#else + uint64_t _reserved0 : 16; + uint64_t ppt_fsm_l : 4; + uint64_t lpar_id : 12; + uint64_t pc_tc_deep_idle_thread_state : 8; + uint64_t spare_1bit : 1; + uint64_t eff_idle_state : 3; + uint64_t current_aiss_fsm_state_vector : 7; + uint64_t spare_6bit : 6; + uint64_t eco_access_impossible : 1; + uint64_t core_access_impossible : 1; + uint64_t architected_idle_state_from_core : 3; + uint64_t special_wakeup_completed : 1; + uint64_t low_activity_detect_bit : 1; +#endif // _BIG_ENDIAN + } fields; +} oha_ro_status_reg_t; + +#endif // __ASSEMBLER__ +#define OHA_RO_STATUS_REG_LOW_ACTIVITY_DETECT_BIT SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define OHA_RO_STATUS_REG_SPECIAL_WAKEUP_COMPLETED SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#define OHA_RO_STATUS_REG_ARCHITECTED_IDLE_STATE_FROM_CORE_MASK SIXTYFOUR_BIT_CONSTANT(0x3800000000000000) +#define OHA_RO_STATUS_REG_CORE_ACCESS_IMPOSSIBLE SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) +#define OHA_RO_STATUS_REG_ECO_ACCESS_IMPOSSIBLE SIXTYFOUR_BIT_CONSTANT(0x0200000000000000) +#define OHA_RO_STATUS_REG_SPARE_6BIT_MASK SIXTYFOUR_BIT_CONSTANT(0x01f8000000000000) +#define OHA_RO_STATUS_REG_CURRENT_AISS_FSM_STATE_VECTOR_MASK SIXTYFOUR_BIT_CONSTANT(0x0007f00000000000) +#define OHA_RO_STATUS_REG_EFF_IDLE_STATE_MASK SIXTYFOUR_BIT_CONSTANT(0x00000e0000000000) +#define OHA_RO_STATUS_REG_SPARE_1BIT SIXTYFOUR_BIT_CONSTANT(0x0000010000000000) +#define OHA_RO_STATUS_REG_PC_TC_DEEP_IDLE_THREAD_STATE_MASK SIXTYFOUR_BIT_CONSTANT(0x000000ff00000000) +#define OHA_RO_STATUS_REG_LPAR_ID_MASK SIXTYFOUR_BIT_CONSTANT(0x00000000fff00000) +#define OHA_RO_STATUS_REG_PPT_FSM_L_MASK SIXTYFOUR_BIT_CONSTANT(0x00000000000f0000) +#ifndef __ASSEMBLER__ + + +typedef union oha_mode_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t enable_ignore_recov_errors : 1; + uint64_t enable_arch_idle_mode_sequencer : 1; + uint64_t treat_sleep_as_nap : 1; + uint64_t treat_winkle_as_sleep : 1; + uint64_t enable_pstate_tracing : 1; + uint64_t enable_suppress_purges_and_pcb_fence : 1; + uint64_t idle_state_override_en : 1; + uint64_t idle_state_override_value : 3; + uint64_t disable_aiss_core_handshake : 1; + uint64_t aiss_hang_detect_timer_sel : 4; + uint64_t enable_l2_purge_abort : 1; + uint64_t enable_l3_purge_abort : 1; + uint64_t tod_pulse_count_match_val : 14; + uint64_t trace_debug_mode_select : 2; + uint64_t lpft_mode : 1; + uint64_t _reserved0 : 30; +#else + uint64_t _reserved0 : 30; + uint64_t lpft_mode : 1; + uint64_t trace_debug_mode_select : 2; + uint64_t tod_pulse_count_match_val : 14; + uint64_t enable_l3_purge_abort : 1; + uint64_t enable_l2_purge_abort : 1; + uint64_t aiss_hang_detect_timer_sel : 4; + uint64_t disable_aiss_core_handshake : 1; + uint64_t idle_state_override_value : 3; + uint64_t idle_state_override_en : 1; + uint64_t enable_suppress_purges_and_pcb_fence : 1; + uint64_t enable_pstate_tracing : 1; + uint64_t treat_winkle_as_sleep : 1; + uint64_t treat_sleep_as_nap : 1; + uint64_t enable_arch_idle_mode_sequencer : 1; + uint64_t enable_ignore_recov_errors : 1; +#endif // _BIG_ENDIAN + } fields; +} oha_mode_reg_t; + + + +typedef union oha_error_and_error_mask_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oha_error_mask : 8; + uint64_t oha_chiplet_errors : 8; + uint64_t _reserved0 : 48; +#else + uint64_t _reserved0 : 48; + uint64_t oha_chiplet_errors : 8; + uint64_t oha_error_mask : 8; +#endif // _BIG_ENDIAN + } fields; +} oha_error_and_error_mask_reg_t; + + + +typedef union oha_arch_idle_state_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t aiss_thold_sequence_select : 1; + uint64_t disable_waiting_on_l3 : 1; + uint64_t idle_seq_timer_select : 2; + uint64_t allow_aiss_interrupts : 1; + uint64_t enable_reset_of_counters_while_sleepwinkle : 1; + uint64_t select_p7p_seq_wait_time : 1; + uint64_t disable_auto_sleep_entry : 1; + uint64_t disable_auto_winkle_entry : 1; + uint64_t reset_idle_state_sequencer : 1; + uint64_t _reserved0 : 54; +#else + uint64_t _reserved0 : 54; + uint64_t reset_idle_state_sequencer : 1; + uint64_t disable_auto_winkle_entry : 1; + uint64_t disable_auto_sleep_entry : 1; + uint64_t select_p7p_seq_wait_time : 1; + uint64_t enable_reset_of_counters_while_sleepwinkle : 1; + uint64_t allow_aiss_interrupts : 1; + uint64_t idle_seq_timer_select : 2; + uint64_t disable_waiting_on_l3 : 1; + uint64_t aiss_thold_sequence_select : 1; +#endif // _BIG_ENDIAN + } fields; +} oha_arch_idle_state_reg_t; + + + +typedef union oha_pmu_config_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pmu_pstate_threshold_a : 8; + uint64_t pmu_pstate_threshold_b : 8; + uint64_t pmu_configuration : 3; + uint64_t _reserved0 : 45; +#else + uint64_t _reserved0 : 45; + uint64_t pmu_configuration : 3; + uint64_t pmu_pstate_threshold_b : 8; + uint64_t pmu_pstate_threshold_a : 8; +#endif // _BIG_ENDIAN + } fields; +} oha_pmu_config_reg_t; + + + +typedef union oha_aiss_io_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t spare_2bits_b : 2; + uint64_t tc_tp_chiplet_pm_state : 4; + uint64_t tc_pb_sleep : 1; + uint64_t tc_tc_pm_thold_ctrl : 3; + uint64_t tc_l3_fence_lco : 1; + uint64_t tc_ncu_fence : 1; + uint64_t chksw_hw237039dis : 1; + uint64_t tc_l3_init_dram : 1; + uint64_t tc_pb_purge : 1; + uint64_t tc_pc_pm_wake_up : 1; + uint64_t spare_entry_for_config_bit : 1; + uint64_t reset_of_counters_while_sleepwinkle : 1; + uint64_t tc_chtm_purge : 1; + uint64_t tc_tp_terminate_pcb : 1; + uint64_t tc_oha_therm_purge_lvl : 1; + uint64_t pscom_core_fence_lvl : 1; + uint64_t pb_eco_fence_lvl : 1; + uint64_t core2cache_fence_req : 1; + uint64_t cache2core_fence_req : 1; + uint64_t pervasive_eco_fence_req : 1; + uint64_t tc_oha_pmx_fence_req_lvl_l : 1; + uint64_t updateohafreq : 1; + uint64_t req_idle_state_change : 1; + uint64_t tc_l2_purge : 1; + uint64_t tc_l3_purge : 1; + uint64_t tc_ncu_purge : 1; + uint64_t tc_l2_purge_abort : 1; + uint64_t tc_l3_purge_abort : 1; + uint64_t pc_tc_pm_state : 3; + uint64_t l2_purge_is_done : 1; + uint64_t l3_ncu_chtm_purge_done : 3; + uint64_t tc_tc_xstop_err : 1; + uint64_t tc_tc_recov_err : 1; + uint64_t pb_tc_purge_active_lvl : 1; + uint64_t l3_tc_dram_ready_lvl : 1; + uint64_t core_fsm_non_idle : 1; + uint64_t tc_pscom_core_fence_done : 1; + uint64_t tc_pmx_oha_fence_done : 1; + uint64_t l2_purge_abort_sticky : 1; + uint64_t l3_purge_abort_sticky : 1; + uint64_t _reserved0 : 14; +#else + uint64_t _reserved0 : 14; + uint64_t l3_purge_abort_sticky : 1; + uint64_t l2_purge_abort_sticky : 1; + uint64_t tc_pmx_oha_fence_done : 1; + uint64_t tc_pscom_core_fence_done : 1; + uint64_t core_fsm_non_idle : 1; + uint64_t l3_tc_dram_ready_lvl : 1; + uint64_t pb_tc_purge_active_lvl : 1; + uint64_t tc_tc_recov_err : 1; + uint64_t tc_tc_xstop_err : 1; + uint64_t l3_ncu_chtm_purge_done : 3; + uint64_t l2_purge_is_done : 1; + uint64_t pc_tc_pm_state : 3; + uint64_t tc_l3_purge_abort : 1; + uint64_t tc_l2_purge_abort : 1; + uint64_t tc_ncu_purge : 1; + uint64_t tc_l3_purge : 1; + uint64_t tc_l2_purge : 1; + uint64_t req_idle_state_change : 1; + uint64_t updateohafreq : 1; + uint64_t tc_oha_pmx_fence_req_lvl_l : 1; + uint64_t pervasive_eco_fence_req : 1; + uint64_t cache2core_fence_req : 1; + uint64_t core2cache_fence_req : 1; + uint64_t pb_eco_fence_lvl : 1; + uint64_t pscom_core_fence_lvl : 1; + uint64_t tc_oha_therm_purge_lvl : 1; + uint64_t tc_tp_terminate_pcb : 1; + uint64_t tc_chtm_purge : 1; + uint64_t reset_of_counters_while_sleepwinkle : 1; + uint64_t spare_entry_for_config_bit : 1; + uint64_t tc_pc_pm_wake_up : 1; + uint64_t tc_pb_purge : 1; + uint64_t tc_l3_init_dram : 1; + uint64_t chksw_hw237039dis : 1; + uint64_t tc_ncu_fence : 1; + uint64_t tc_l3_fence_lco : 1; + uint64_t tc_tc_pm_thold_ctrl : 3; + uint64_t tc_pb_sleep : 1; + uint64_t tc_tp_chiplet_pm_state : 4; + uint64_t spare_2bits_b : 2; +#endif // _BIG_ENDIAN + } fields; +} oha_aiss_io_reg_t; + + + +typedef union oha_ppt_bar_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t ppt_bar : 46; + uint64_t ppt_size_mask : 7; + uint64_t ppt_address_scope : 3; + uint64_t _reserved0 : 8; +#else + uint64_t _reserved0 : 8; + uint64_t ppt_address_scope : 3; + uint64_t ppt_size_mask : 7; + uint64_t ppt_bar : 46; +#endif // _BIG_ENDIAN + } fields; +} oha_ppt_bar_reg_t; + + + +typedef union oha_l2_vcs_directory_read_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l2_vcs_directory_read_weight_t; + + + +typedef union oha_l2_vcs_directory_write_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l2_vcs_directory_write_weight_t; + + + +typedef union oha_l2_vcs_cache_full_read_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l2_vcs_cache_full_read_weight_t; + + + +typedef union oha_l2_vcs_cache_targeted_read_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l2_vcs_cache_targeted_read_weight_t; + + + +typedef union oha_l2_vcs_cache_write_cnt_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l2_vcs_cache_write_cnt_weight_t; + + + +typedef union oha_l3_vcs_directory_read_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l3_vcs_directory_read_weight_t; + + + +typedef union oha_l3_vcs_directory_write_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l3_vcs_directory_write_weight_t; + + + +typedef union oha_l3_vcs_cache_access_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l3_vcs_cache_access_weight_t; + + + +typedef union oha_l2_vdd_directory_read_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l2_vdd_directory_read_weight_t; + + + +typedef union oha_l2_vdd_directory_write_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l2_vdd_directory_write_weight_t; + + + +typedef union oha_l2_vdd_cache_full_read_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l2_vdd_cache_full_read_weight_t; + + + +typedef union oha_l2_vdd_cache_targeted_read_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l2_vdd_cache_targeted_read_weight_t; + + + +typedef union oha_l2_vdd_cache_write_cnt_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l2_vdd_cache_write_cnt_weight_t; + + + +typedef union oha_l3_vdd_directory_read_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l3_vdd_directory_read_weight_t; + + + +typedef union oha_l3_vdd_directory_write_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l3_vdd_directory_write_weight_t; + + + +typedef union oha_l3_vdd_cache_access_weight { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 6; + uint64_t _reserved0 : 58; +#else + uint64_t _reserved0 : 58; + uint64_t value : 6; +#endif // _BIG_ENDIAN + } fields; +} oha_l3_vdd_cache_access_weight_t; + + + +typedef union oha_chksw_hw132623dis { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 1; + uint64_t _reserved0 : 63; +#else + uint64_t _reserved0 : 63; + uint64_t value : 1; +#endif // _BIG_ENDIAN + } fields; +} oha_chksw_hw132623dis_t; + + + +typedef union oha_activity_scale_factor_array { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 56; + uint64_t _reserved0 : 8; +#else + uint64_t _reserved0 : 8; + uint64_t value : 56; +#endif // _BIG_ENDIAN + } fields; +} oha_activity_scale_factor_array_t; + + + +typedef union oha_activity_scale_shift_factor_array { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 42; + uint64_t _reserved0 : 22; +#else + uint64_t _reserved0 : 22; + uint64_t value : 42; +#endif // _BIG_ENDIAN + } fields; +} oha_activity_scale_shift_factor_array_t; + + +#endif // __ASSEMBLER__ +#endif // __OHA_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/oha_register_addresses.h b/src/ssx/pgp/registers/oha_register_addresses.h new file mode 100755 index 0000000..1f07b37 --- /dev/null +++ b/src/ssx/pgp/registers/oha_register_addresses.h @@ -0,0 +1,39 @@ +#ifndef __OHA_REGISTER_ADDRESSES_H__ +#define __OHA_REGISTER_ADDRESSES_H__ + +// $Id: oha_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/oha_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file oha_register_addresses.h +/// \brief Symbolic addresses for the OHA unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define OHA_PCB_BASE 0x10020000 +#define OHA_ACTIVITY_SAMPLE_MODE_REG 0x10020000 +#define OHA_VCS_ACTIVITY_CNT_REG 0x10020001 +#define OHA_VDD_ACTIVITY_CNT_REG 0x10020002 +#define OHA_LOW_ACTIVITY_DETECT_MODE_REG 0x10020003 +#define OHA_ACTIVITY_AND_FREQU_REG 0x10020004 +#define OHA_COUNTER_REG 0x10020005 +#define OHA_PROXY_REG 0x10020006 +#define OHA_PROXY_LEGACY_REG 0x10020007 +#define OHA_SKITTER_CTRL_MODE_REG 0x10020008 +#define OHA_CPM_CTRL_REG 0x1002000a +#define OHA_CPM_HIST_RESET_REG 0x10020013 +#define OHA_RO_STATUS_REG 0x1002000b +#define OHA_MODE_REG 0x1002000d +#define OHA_ERROR_AND_ERROR_MASK_REG 0x1002000e +#define OHA_ARCH_IDLE_STATE_REG 0x10020011 +#define OHA_PMU_CONFIG_REG 0x10020012 +#define OHA_AISS_IO_REG 0x10020014 +#define OHA_PPT_BAR_REG 0x10020015 + +#endif // __OHA_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/pba_firmware_registers.h b/src/ssx/pgp/registers/pba_firmware_registers.h new file mode 100755 index 0000000..502ef51 --- /dev/null +++ b/src/ssx/pgp/registers/pba_firmware_registers.h @@ -0,0 +1,2184 @@ +#ifndef __PBA_FIRMWARE_REGISTERS_H__ +#define __PBA_FIRMWARE_REGISTERS_H__ + +// $Id: pba_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pba_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file pba_firmware_registers.h +/// \brief C register structs for the PBA unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union pba_barn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t cmd_scope : 3; + uint64_t reserved0 : 1; + uint64_t reserved1 : 10; + uint64_t addr : 30; + uint64_t _reserved0 : 20; +#else + uint64_t _reserved0 : 20; + uint64_t addr : 30; + uint64_t reserved1 : 10; + uint64_t reserved0 : 1; + uint64_t cmd_scope : 3; +#endif // _BIG_ENDIAN + } fields; +} pba_barn_t; + +#endif // __ASSEMBLER__ +#define PBA_BARN_CMD_SCOPE_MASK SIXTYFOUR_BIT_CONSTANT(0xe000000000000000) +#define PBA_BARN_ADDR_MASK SIXTYFOUR_BIT_CONSTANT(0x0003fffffff00000) +#ifndef __ASSEMBLER__ + + +typedef union pba_barmskn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved0 : 23; + uint64_t mask : 21; + uint64_t _reserved0 : 20; +#else + uint64_t _reserved0 : 20; + uint64_t mask : 21; + uint64_t reserved0 : 23; +#endif // _BIG_ENDIAN + } fields; +} pba_barmskn_t; + +#endif // __ASSEMBLER__ +#define PBA_BARMSKN_MASK_MASK SIXTYFOUR_BIT_CONSTANT(0x000001fffff00000) +#ifndef __ASSEMBLER__ + + +typedef union pba_fir { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_apar_err : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_ce_fw : 1; + uint64_t oci_slave_init : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_rereqto : 1; + uint64_t pb_unexpcresp : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_crespto : 1; + uint64_t bcue_setup_err : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t internal_err : 1; + uint64_t illegal_cache_op : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t axpush_wrerr : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axflow_err : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_rsverr : 1; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t reserved41 : 3; + uint64_t fir_parity_err2 : 1; + uint64_t fir_parity_err : 1; + uint64_t _reserved0 : 18; +#else + uint64_t _reserved0 : 18; + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err2 : 1; + uint64_t reserved41 : 3; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t axsnd_rsverr : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axflow_err : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axpush_wrerr : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t illegal_cache_op : 1; + uint64_t internal_err : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_setup_err : 1; + uint64_t pb_crespto : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_unexpcresp : 1; + uint64_t oci_rereqto : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_slave_init : 1; + uint64_t pb_ce_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t oci_apar_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_fir_t; + +#endif // __ASSEMBLER__ +#define PBA_FIR_OCI_APAR_ERR SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define PBA_FIR_PB_RDADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#define PBA_FIR_PB_RDDATATO_FW SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) +#define PBA_FIR_PB_SUE_FW SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) +#define PBA_FIR_PB_UE_FW SIXTYFOUR_BIT_CONSTANT(0x0800000000000000) +#define PBA_FIR_PB_CE_FW SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) +#define PBA_FIR_OCI_SLAVE_INIT SIXTYFOUR_BIT_CONSTANT(0x0200000000000000) +#define PBA_FIR_OCI_WRPAR_ERR SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) +#define PBA_FIR_OCI_REREQTO SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) +#define PBA_FIR_PB_UNEXPCRESP SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) +#define PBA_FIR_PB_UNEXPDATA SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) +#define PBA_FIR_PB_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) +#define PBA_FIR_PB_WRADRERR_FW SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) +#define PBA_FIR_PB_BADCRESP SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) +#define PBA_FIR_PB_ACKDEAD_FW SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) +#define PBA_FIR_PB_CRESPTO SIXTYFOUR_BIT_CONSTANT(0x0001000000000000) +#define PBA_FIR_BCUE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000800000000000) +#define PBA_FIR_BCUE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000400000000000) +#define PBA_FIR_BCUE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000200000000000) +#define PBA_FIR_BCUE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000100000000000) +#define PBA_FIR_BCDE_SETUP_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000) +#define PBA_FIR_BCDE_PB_ACK_DEAD SIXTYFOUR_BIT_CONSTANT(0x0000040000000000) +#define PBA_FIR_BCDE_PB_ADRERR SIXTYFOUR_BIT_CONSTANT(0x0000020000000000) +#define PBA_FIR_BCDE_RDDATATO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000010000000000) +#define PBA_FIR_BCDE_SUE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000008000000000) +#define PBA_FIR_BCDE_UE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000004000000000) +#define PBA_FIR_BCDE_CE SIXTYFOUR_BIT_CONSTANT(0x0000002000000000) +#define PBA_FIR_BCDE_OCI_DATAERR SIXTYFOUR_BIT_CONSTANT(0x0000001000000000) +#define PBA_FIR_INTERNAL_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000800000000) +#define PBA_FIR_ILLEGAL_CACHE_OP SIXTYFOUR_BIT_CONSTANT(0x0000000400000000) +#define PBA_FIR_OCI_BAD_REG_ADDR SIXTYFOUR_BIT_CONSTANT(0x0000000200000000) +#define PBA_FIR_AXPUSH_WRERR SIXTYFOUR_BIT_CONSTANT(0x0000000100000000) +#define PBA_FIR_AXRCV_DLO_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000080000000) +#define PBA_FIR_AXRCV_DLO_TO SIXTYFOUR_BIT_CONSTANT(0x0000000040000000) +#define PBA_FIR_AXRCV_RSVDATA_TO SIXTYFOUR_BIT_CONSTANT(0x0000000020000000) +#define PBA_FIR_AXFLOW_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000010000000) +#define PBA_FIR_AXSND_DHI_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000008000000) +#define PBA_FIR_AXSND_DLO_RTYTO SIXTYFOUR_BIT_CONSTANT(0x0000000004000000) +#define PBA_FIR_AXSND_RSVTO SIXTYFOUR_BIT_CONSTANT(0x0000000002000000) +#define PBA_FIR_AXSND_RSVERR SIXTYFOUR_BIT_CONSTANT(0x0000000001000000) +#define PBA_FIR_PB_ACKDEAD_FW_WR SIXTYFOUR_BIT_CONSTANT(0x0000000000800000) +#define PBA_FIR_FIR_PARITY_ERR2 SIXTYFOUR_BIT_CONSTANT(0x0000000000080000) +#define PBA_FIR_FIR_PARITY_ERR SIXTYFOUR_BIT_CONSTANT(0x0000000000040000) +#ifndef __ASSEMBLER__ + + +typedef union pba_fir_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_apar_err : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_ce_fw : 1; + uint64_t oci_slave_init : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_rereqto : 1; + uint64_t pb_unexpcresp : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_crespto : 1; + uint64_t bcue_setup_err : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t internal_err : 1; + uint64_t illegal_cache_op : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t axpush_wrerr : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axflow_err : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_rsverr : 1; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t reserved41 : 3; + uint64_t fir_parity_err2 : 1; + uint64_t fir_parity_err : 1; + uint64_t _reserved0 : 18; +#else + uint64_t _reserved0 : 18; + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err2 : 1; + uint64_t reserved41 : 3; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t axsnd_rsverr : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axflow_err : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axpush_wrerr : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t illegal_cache_op : 1; + uint64_t internal_err : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_setup_err : 1; + uint64_t pb_crespto : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_unexpcresp : 1; + uint64_t oci_rereqto : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_slave_init : 1; + uint64_t pb_ce_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t oci_apar_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_fir_and_t; + + + +typedef union pba_fir_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_apar_err : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_ce_fw : 1; + uint64_t oci_slave_init : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_rereqto : 1; + uint64_t pb_unexpcresp : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_crespto : 1; + uint64_t bcue_setup_err : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t internal_err : 1; + uint64_t illegal_cache_op : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t axpush_wrerr : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axflow_err : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_rsverr : 1; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t reserved41 : 3; + uint64_t fir_parity_err2 : 1; + uint64_t fir_parity_err : 1; + uint64_t _reserved0 : 18; +#else + uint64_t _reserved0 : 18; + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err2 : 1; + uint64_t reserved41 : 3; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t axsnd_rsverr : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axflow_err : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axpush_wrerr : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t illegal_cache_op : 1; + uint64_t internal_err : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_setup_err : 1; + uint64_t pb_crespto : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_unexpcresp : 1; + uint64_t oci_rereqto : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_slave_init : 1; + uint64_t pb_ce_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t oci_apar_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_fir_or_t; + + + +typedef union pba_firmask { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_apar_err : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_ce_fw : 1; + uint64_t oci_slave_init : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_rereqto : 1; + uint64_t pb_unexpcresp : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_crespto : 1; + uint64_t bcue_setup_err : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t internal_err : 1; + uint64_t illegal_cache_op : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t axpush_wrerr : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axflow_err : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_rsverr : 1; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t reserved41 : 3; + uint64_t fir_parity_err2 : 1; + uint64_t fir_parity_err : 1; + uint64_t _reserved0 : 18; +#else + uint64_t _reserved0 : 18; + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err2 : 1; + uint64_t reserved41 : 3; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t axsnd_rsverr : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axflow_err : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axpush_wrerr : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t illegal_cache_op : 1; + uint64_t internal_err : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_setup_err : 1; + uint64_t pb_crespto : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_unexpcresp : 1; + uint64_t oci_rereqto : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_slave_init : 1; + uint64_t pb_ce_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t oci_apar_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_firmask_t; + + + +typedef union pba_firmask_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_apar_err : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_ce_fw : 1; + uint64_t oci_slave_init : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_rereqto : 1; + uint64_t pb_unexpcresp : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_crespto : 1; + uint64_t bcue_setup_err : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t internal_err : 1; + uint64_t illegal_cache_op : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t axpush_wrerr : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axflow_err : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_rsverr : 1; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t reserved41 : 3; + uint64_t fir_parity_err2 : 1; + uint64_t fir_parity_err : 1; + uint64_t _reserved0 : 18; +#else + uint64_t _reserved0 : 18; + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err2 : 1; + uint64_t reserved41 : 3; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t axsnd_rsverr : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axflow_err : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axpush_wrerr : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t illegal_cache_op : 1; + uint64_t internal_err : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_setup_err : 1; + uint64_t pb_crespto : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_unexpcresp : 1; + uint64_t oci_rereqto : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_slave_init : 1; + uint64_t pb_ce_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t oci_apar_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_firmask_and_t; + + + +typedef union pba_firmask_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_apar_err : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_ce_fw : 1; + uint64_t oci_slave_init : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_rereqto : 1; + uint64_t pb_unexpcresp : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_crespto : 1; + uint64_t bcue_setup_err : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t internal_err : 1; + uint64_t illegal_cache_op : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t axpush_wrerr : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axflow_err : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_rsverr : 1; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t reserved41 : 3; + uint64_t fir_parity_err2 : 1; + uint64_t fir_parity_err : 1; + uint64_t _reserved0 : 18; +#else + uint64_t _reserved0 : 18; + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err2 : 1; + uint64_t reserved41 : 3; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t axsnd_rsverr : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axflow_err : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axpush_wrerr : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t illegal_cache_op : 1; + uint64_t internal_err : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_setup_err : 1; + uint64_t pb_crespto : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_unexpcresp : 1; + uint64_t oci_rereqto : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_slave_init : 1; + uint64_t pb_ce_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t oci_apar_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_firmask_or_t; + + + +typedef union pba_firact0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_apar_err : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_ce_fw : 1; + uint64_t oci_slave_init : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_rereqto : 1; + uint64_t pb_unexpcresp : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_crespto : 1; + uint64_t bcue_setup_err : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t internal_err : 1; + uint64_t illegal_cache_op : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t axpush_wrerr : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axflow_err : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_rsverr : 1; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t reserved41 : 3; + uint64_t fir_parity_err2 : 1; + uint64_t fir_parity_err : 1; + uint64_t _reserved0 : 18; +#else + uint64_t _reserved0 : 18; + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err2 : 1; + uint64_t reserved41 : 3; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t axsnd_rsverr : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axflow_err : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axpush_wrerr : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t illegal_cache_op : 1; + uint64_t internal_err : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_setup_err : 1; + uint64_t pb_crespto : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_unexpcresp : 1; + uint64_t oci_rereqto : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_slave_init : 1; + uint64_t pb_ce_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t oci_apar_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_firact0_t; + + + +typedef union pba_firact1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_apar_err : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_ce_fw : 1; + uint64_t oci_slave_init : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_rereqto : 1; + uint64_t pb_unexpcresp : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_crespto : 1; + uint64_t bcue_setup_err : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t internal_err : 1; + uint64_t illegal_cache_op : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t axpush_wrerr : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axflow_err : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_rsverr : 1; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t reserved41 : 3; + uint64_t fir_parity_err2 : 1; + uint64_t fir_parity_err : 1; + uint64_t _reserved0 : 18; +#else + uint64_t _reserved0 : 18; + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err2 : 1; + uint64_t reserved41 : 3; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t axsnd_rsverr : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axflow_err : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axpush_wrerr : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t illegal_cache_op : 1; + uint64_t internal_err : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_setup_err : 1; + uint64_t pb_crespto : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_unexpcresp : 1; + uint64_t oci_rereqto : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_slave_init : 1; + uint64_t pb_ce_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t oci_apar_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_firact1_t; + + + +typedef union pba_occact { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t oci_apar_err : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_ce_fw : 1; + uint64_t oci_slave_init : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_rereqto : 1; + uint64_t pb_unexpcresp : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_crespto : 1; + uint64_t bcue_setup_err : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t internal_err : 1; + uint64_t illegal_cache_op : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t axpush_wrerr : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axflow_err : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_rsverr : 1; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t reserved41 : 3; + uint64_t fir_parity_err2 : 1; + uint64_t fir_parity_err : 1; + uint64_t _reserved0 : 18; +#else + uint64_t _reserved0 : 18; + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err2 : 1; + uint64_t reserved41 : 3; + uint64_t pb_ackdead_fw_wr : 1; + uint64_t axsnd_rsverr : 1; + uint64_t axsnd_rsvto : 1; + uint64_t axsnd_dlo_rtyto : 1; + uint64_t axsnd_dhi_rtyto : 1; + uint64_t axflow_err : 1; + uint64_t axrcv_rsvdata_to : 1; + uint64_t axrcv_dlo_to : 1; + uint64_t axrcv_dlo_err : 1; + uint64_t axpush_wrerr : 1; + uint64_t oci_bad_reg_addr : 1; + uint64_t illegal_cache_op : 1; + uint64_t internal_err : 1; + uint64_t bcde_oci_dataerr : 1; + uint64_t bcde_ce : 1; + uint64_t bcde_ue_err : 1; + uint64_t bcde_sue_err : 1; + uint64_t bcde_rddatato_err : 1; + uint64_t bcde_pb_adrerr : 1; + uint64_t bcde_pb_ack_dead : 1; + uint64_t bcde_setup_err : 1; + uint64_t bcue_oci_dataerr : 1; + uint64_t bcue_pb_adrerr : 1; + uint64_t bcue_pb_ack_dead : 1; + uint64_t bcue_setup_err : 1; + uint64_t pb_crespto : 1; + uint64_t pb_ackdead_fw : 1; + uint64_t pb_badcresp : 1; + uint64_t pb_wradrerr_fw : 1; + uint64_t pb_parity_err : 1; + uint64_t pb_unexpdata : 1; + uint64_t pb_unexpcresp : 1; + uint64_t oci_rereqto : 1; + uint64_t oci_wrpar_err : 1; + uint64_t oci_slave_init : 1; + uint64_t pb_ce_fw : 1; + uint64_t pb_ue_fw : 1; + uint64_t pb_sue_fw : 1; + uint64_t pb_rddatato_fw : 1; + uint64_t pb_rdadrerr_fw : 1; + uint64_t oci_apar_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_occact_t; + + + +typedef union pba_cfg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pbreq_slvfw_max_priority : 2; + uint64_t pbreq_bce_max_priority : 2; + uint64_t pbreq_data_hang_div : 5; + uint64_t pbreq_oper_hang_div : 5; + uint64_t pbreq_drop_priority_mask : 6; + uint64_t reserved20 : 4; + uint64_t chsw_hang_on_adrerror : 1; + uint64_t chsw_dis_ociabuspar_check : 1; + uint64_t chsw_dis_ocibepar_check : 1; + uint64_t chsw_hang_on_derror : 1; + uint64_t chsw_hang_on_rereq_timeout : 1; + uint64_t chsw_dis_write_match_rearb : 1; + uint64_t chsw_dis_ocidatapar_gen : 1; + uint64_t chsw_dis_ocidatapar_check : 1; + uint64_t chsw_dis_oper_hang : 1; + uint64_t chsw_dis_data_hang : 1; + uint64_t chsw_dis_ecc_check : 1; + uint64_t chsw_dis_retry_backoff : 1; + uint64_t chsw_hang_on_invalid_cresp : 1; + uint64_t chsw_en_scopeinc_on_bkill_inc : 1; + uint64_t chsw_dis_group_scope : 1; + uint64_t chsw_dis_rtag_parity_chk : 1; + uint64_t chsw_dis_pb_parity_chk : 1; + uint64_t _reserved0 : 23; +#else + uint64_t _reserved0 : 23; + uint64_t chsw_dis_pb_parity_chk : 1; + uint64_t chsw_dis_rtag_parity_chk : 1; + uint64_t chsw_dis_group_scope : 1; + uint64_t chsw_en_scopeinc_on_bkill_inc : 1; + uint64_t chsw_hang_on_invalid_cresp : 1; + uint64_t chsw_dis_retry_backoff : 1; + uint64_t chsw_dis_ecc_check : 1; + uint64_t chsw_dis_data_hang : 1; + uint64_t chsw_dis_oper_hang : 1; + uint64_t chsw_dis_ocidatapar_check : 1; + uint64_t chsw_dis_ocidatapar_gen : 1; + uint64_t chsw_dis_write_match_rearb : 1; + uint64_t chsw_hang_on_rereq_timeout : 1; + uint64_t chsw_hang_on_derror : 1; + uint64_t chsw_dis_ocibepar_check : 1; + uint64_t chsw_dis_ociabuspar_check : 1; + uint64_t chsw_hang_on_adrerror : 1; + uint64_t reserved20 : 4; + uint64_t pbreq_drop_priority_mask : 6; + uint64_t pbreq_oper_hang_div : 5; + uint64_t pbreq_data_hang_div : 5; + uint64_t pbreq_bce_max_priority : 2; + uint64_t pbreq_slvfw_max_priority : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_cfg_t; + + + +typedef union pba_errpt0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t cerr_pb_rddatato_fw : 6; + uint64_t cerr_pb_rdadrerr_fw : 6; + uint64_t cerr_pb_wradrerr_fw : 4; + uint64_t cerr_pb_ackdead_fw_rd : 6; + uint64_t cerr_pb_ackdead_fw_wr : 2; + uint64_t cerr_pb_unexpcresp : 11; + uint64_t cerr_pb_unexpdata : 6; + uint64_t _reserved0 : 23; +#else + uint64_t _reserved0 : 23; + uint64_t cerr_pb_unexpdata : 6; + uint64_t cerr_pb_unexpcresp : 11; + uint64_t cerr_pb_ackdead_fw_wr : 2; + uint64_t cerr_pb_ackdead_fw_rd : 6; + uint64_t cerr_pb_wradrerr_fw : 4; + uint64_t cerr_pb_rdadrerr_fw : 6; + uint64_t cerr_pb_rddatato_fw : 6; +#endif // _BIG_ENDIAN + } fields; +} pba_errpt0_t; + + + +typedef union pba_errpt1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t cerr_pb_badcresp : 12; + uint64_t cerr_pb_crespto : 12; + uint64_t cerr_oci_rereqto : 6; + uint64_t cerr_bcde_setup_err : 2; + uint64_t cerr_bcue_setup_err : 2; + uint64_t cerr_bcue_oci_dataerr : 2; + uint64_t _reserved0 : 28; +#else + uint64_t _reserved0 : 28; + uint64_t cerr_bcue_oci_dataerr : 2; + uint64_t cerr_bcue_setup_err : 2; + uint64_t cerr_bcde_setup_err : 2; + uint64_t cerr_oci_rereqto : 6; + uint64_t cerr_pb_crespto : 12; + uint64_t cerr_pb_badcresp : 12; +#endif // _BIG_ENDIAN + } fields; +} pba_errpt1_t; + + + +typedef union pba_errpt2 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t cerr_slv_internal_err : 8; + uint64_t cerr_bcde_internal_err : 4; + uint64_t cerr_bcue_internal_err : 4; + uint64_t cerr_bar_parity_err : 1; + uint64_t cerr_scomtb_err : 1; + uint64_t reserved18 : 2; + uint64_t cerr_pbdout_parity_err : 1; + uint64_t cerr_pb_parity_err : 3; + uint64_t cerr_axflow_err : 5; + uint64_t cerr_axpush_wrerr : 2; + uint64_t _reserved0 : 33; +#else + uint64_t _reserved0 : 33; + uint64_t cerr_axpush_wrerr : 2; + uint64_t cerr_axflow_err : 5; + uint64_t cerr_pb_parity_err : 3; + uint64_t cerr_pbdout_parity_err : 1; + uint64_t reserved18 : 2; + uint64_t cerr_scomtb_err : 1; + uint64_t cerr_bar_parity_err : 1; + uint64_t cerr_bcue_internal_err : 4; + uint64_t cerr_bcde_internal_err : 4; + uint64_t cerr_slv_internal_err : 8; +#endif // _BIG_ENDIAN + } fields; +} pba_errpt2_t; + + + +typedef union pba_rbufvaln { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t rd_slvnum : 2; + uint64_t cur_rd_addr : 23; + uint64_t spare1 : 3; + uint64_t prefetch : 1; + uint64_t spare2 : 2; + uint64_t abort : 1; + uint64_t spare3 : 1; + uint64_t buffer_status : 7; + uint64_t spare4 : 1; + uint64_t masterid : 3; + uint64_t _reserved0 : 20; +#else + uint64_t _reserved0 : 20; + uint64_t masterid : 3; + uint64_t spare4 : 1; + uint64_t buffer_status : 7; + uint64_t spare3 : 1; + uint64_t abort : 1; + uint64_t spare2 : 2; + uint64_t prefetch : 1; + uint64_t spare1 : 3; + uint64_t cur_rd_addr : 23; + uint64_t rd_slvnum : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_rbufvaln_t; + + + +typedef union pba_wbufvaln { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t wr_slvnum : 2; + uint64_t start_wr_addr : 30; + uint64_t spare1 : 3; + uint64_t wr_buffer_status : 5; + uint64_t spare2 : 1; + uint64_t wr_byte_count : 7; + uint64_t spare3 : 16; +#else + uint64_t spare3 : 16; + uint64_t wr_byte_count : 7; + uint64_t spare2 : 1; + uint64_t wr_buffer_status : 5; + uint64_t spare1 : 3; + uint64_t start_wr_addr : 30; + uint64_t wr_slvnum : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_wbufvaln_t; + + + +typedef union pba_mode { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved0 : 4; + uint64_t dis_rearb : 1; + uint64_t dis_mstid_match_pref_inv : 1; + uint64_t dis_slave_rdpipe : 1; + uint64_t dis_slave_wrpipe : 1; + uint64_t en_marker_ack : 1; + uint64_t dis_slvmatch_order : 1; + uint64_t en_second_wrbuf : 1; + uint64_t dis_rerequest_to : 1; + uint64_t inject_type : 2; + uint64_t inject_mode : 2; + uint64_t pba_region : 2; + uint64_t oci_marker_space : 3; + uint64_t bcde_ocitrans : 2; + uint64_t bcue_ocitrans : 2; + uint64_t dis_master_rd_pipe : 1; + uint64_t dis_master_wr_pipe : 1; + uint64_t en_slave_fairness : 1; + uint64_t en_event_count : 1; + uint64_t pb_noci_event_sel : 1; + uint64_t slv_event_mux : 2; + uint64_t enable_debug_bus : 1; + uint64_t debug_pb_not_oci : 1; + uint64_t debug_oci_mode : 5; + uint64_t reserved2 : 1; + uint64_t ocislv_fairness_mask : 5; + uint64_t ocislv_rereq_hang_div : 5; + uint64_t dis_chgrate_count : 1; + uint64_t pbreq_event_mux : 2; + uint64_t _reserved0 : 11; +#else + uint64_t _reserved0 : 11; + uint64_t pbreq_event_mux : 2; + uint64_t dis_chgrate_count : 1; + uint64_t ocislv_rereq_hang_div : 5; + uint64_t ocislv_fairness_mask : 5; + uint64_t reserved2 : 1; + uint64_t debug_oci_mode : 5; + uint64_t debug_pb_not_oci : 1; + uint64_t enable_debug_bus : 1; + uint64_t slv_event_mux : 2; + uint64_t pb_noci_event_sel : 1; + uint64_t en_event_count : 1; + uint64_t en_slave_fairness : 1; + uint64_t dis_master_wr_pipe : 1; + uint64_t dis_master_rd_pipe : 1; + uint64_t bcue_ocitrans : 2; + uint64_t bcde_ocitrans : 2; + uint64_t oci_marker_space : 3; + uint64_t pba_region : 2; + uint64_t inject_mode : 2; + uint64_t inject_type : 2; + uint64_t dis_rerequest_to : 1; + uint64_t en_second_wrbuf : 1; + uint64_t dis_slvmatch_order : 1; + uint64_t en_marker_ack : 1; + uint64_t dis_slave_wrpipe : 1; + uint64_t dis_slave_rdpipe : 1; + uint64_t dis_mstid_match_pref_inv : 1; + uint64_t dis_rearb : 1; + uint64_t reserved0 : 4; +#endif // _BIG_ENDIAN + } fields; +} pba_mode_t; + + + +typedef union pba_slvrst { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t set : 3; + uint64_t notimp1 : 1; + uint64_t in_prog : 4; + uint64_t busy_status : 4; + uint64_t _reserved0 : 52; +#else + uint64_t _reserved0 : 52; + uint64_t busy_status : 4; + uint64_t in_prog : 4; + uint64_t notimp1 : 1; + uint64_t set : 3; +#endif // _BIG_ENDIAN + } fields; +} pba_slvrst_t; + + + +typedef union pba_slvctln { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t enable : 1; + uint64_t mid_match_value : 3; + uint64_t _reserved0 : 1; + uint64_t mid_care_mask : 3; + uint64_t write_ttype : 3; + uint64_t _reserved1 : 4; + uint64_t read_ttype : 1; + uint64_t read_prefetch_ctl : 2; + uint64_t buf_invalidate_ctl : 1; + uint64_t buf_alloc_w : 1; + uint64_t buf_alloc_a : 1; + uint64_t buf_alloc_b : 1; + uint64_t buf_alloc_c : 1; + uint64_t _reserved2 : 1; + uint64_t dis_write_gather : 1; + uint64_t wr_gather_timeout : 3; + uint64_t write_tsize : 7; + uint64_t extaddr : 14; + uint64_t _reserved3 : 15; +#else + uint64_t _reserved3 : 15; + uint64_t extaddr : 14; + uint64_t write_tsize : 7; + uint64_t wr_gather_timeout : 3; + uint64_t dis_write_gather : 1; + uint64_t _reserved2 : 1; + uint64_t buf_alloc_c : 1; + uint64_t buf_alloc_b : 1; + uint64_t buf_alloc_a : 1; + uint64_t buf_alloc_w : 1; + uint64_t buf_invalidate_ctl : 1; + uint64_t read_prefetch_ctl : 2; + uint64_t read_ttype : 1; + uint64_t _reserved1 : 4; + uint64_t write_ttype : 3; + uint64_t mid_care_mask : 3; + uint64_t _reserved0 : 1; + uint64_t mid_match_value : 3; + uint64_t enable : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_slvctln_t; + + + +typedef union pba_bcde_ctl { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t stop : 1; + uint64_t start : 1; + uint64_t _reserved0 : 62; +#else + uint64_t _reserved0 : 62; + uint64_t start : 1; + uint64_t stop : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_bcde_ctl_t; + +#endif // __ASSEMBLER__ +#define PBA_BCDE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define PBA_BCDE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#ifndef __ASSEMBLER__ + + +typedef union pba_bcde_set { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 2; + uint64_t copy_length : 6; + uint64_t _reserved1 : 56; +#else + uint64_t _reserved1 : 56; + uint64_t copy_length : 6; + uint64_t _reserved0 : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_bcde_set_t; + + + +typedef union pba_bcde_stat { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t running : 1; + uint64_t waiting : 1; + uint64_t wrcmp : 6; + uint64_t _reserved0 : 6; + uint64_t rdcmp : 6; + uint64_t debug : 9; + uint64_t stopped : 1; + uint64_t error : 1; + uint64_t done : 1; + uint64_t _reserved1 : 32; +#else + uint64_t _reserved1 : 32; + uint64_t done : 1; + uint64_t error : 1; + uint64_t stopped : 1; + uint64_t debug : 9; + uint64_t rdcmp : 6; + uint64_t _reserved0 : 6; + uint64_t wrcmp : 6; + uint64_t waiting : 1; + uint64_t running : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_bcde_stat_t; + + + +typedef union pba_bcde_pbadr { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 2; + uint64_t pb_offset : 23; + uint64_t _reserved1 : 2; + uint64_t extaddr : 14; + uint64_t _reserved2 : 23; +#else + uint64_t _reserved2 : 23; + uint64_t extaddr : 14; + uint64_t _reserved1 : 2; + uint64_t pb_offset : 23; + uint64_t _reserved0 : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_bcde_pbadr_t; + + + +typedef union pba_bcde_ocibar { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t addr : 25; + uint64_t _reserved0 : 39; +#else + uint64_t _reserved0 : 39; + uint64_t addr : 25; +#endif // _BIG_ENDIAN + } fields; +} pba_bcde_ocibar_t; + + + +typedef union pba_bcue_ctl { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t stop : 1; + uint64_t start : 1; + uint64_t _reserved0 : 62; +#else + uint64_t _reserved0 : 62; + uint64_t start : 1; + uint64_t stop : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_bcue_ctl_t; + +#endif // __ASSEMBLER__ +#define PBA_BCUE_CTL_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define PBA_BCUE_CTL_START SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#ifndef __ASSEMBLER__ + + +typedef union pba_bcue_set { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 2; + uint64_t copy_length : 6; + uint64_t _reserved1 : 56; +#else + uint64_t _reserved1 : 56; + uint64_t copy_length : 6; + uint64_t _reserved0 : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_bcue_set_t; + + + +typedef union pba_bcue_stat { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t running : 1; + uint64_t waiting : 1; + uint64_t wrcmp : 6; + uint64_t _reserved0 : 6; + uint64_t rdcmp : 6; + uint64_t debug : 9; + uint64_t stopped : 1; + uint64_t error : 1; + uint64_t done : 1; + uint64_t _reserved1 : 32; +#else + uint64_t _reserved1 : 32; + uint64_t done : 1; + uint64_t error : 1; + uint64_t stopped : 1; + uint64_t debug : 9; + uint64_t rdcmp : 6; + uint64_t _reserved0 : 6; + uint64_t wrcmp : 6; + uint64_t waiting : 1; + uint64_t running : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_bcue_stat_t; + + + +typedef union pba_bcue_pbadr { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 2; + uint64_t pb_offset : 23; + uint64_t _reserved1 : 2; + uint64_t extaddr : 14; + uint64_t _reserved2 : 23; +#else + uint64_t _reserved2 : 23; + uint64_t extaddr : 14; + uint64_t _reserved1 : 2; + uint64_t pb_offset : 23; + uint64_t _reserved0 : 2; +#endif // _BIG_ENDIAN + } fields; +} pba_bcue_pbadr_t; + + + +typedef union pba_bcue_ocibar { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t addr : 25; + uint64_t _reserved0 : 39; +#else + uint64_t _reserved0 : 39; + uint64_t addr : 25; +#endif // _BIG_ENDIAN + } fields; +} pba_bcue_ocibar_t; + + + +typedef union pba_pbocrn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 16; + uint64_t event : 16; + uint64_t _reserved1 : 12; + uint64_t accum : 20; +#else + uint64_t accum : 20; + uint64_t _reserved1 : 12; + uint64_t event : 16; + uint64_t _reserved0 : 16; +#endif // _BIG_ENDIAN + } fields; +} pba_pbocrn_t; + + + +typedef union pba_xsndtx { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t snd_scope : 3; + uint64_t snd_qid : 1; + uint64_t snd_type : 1; + uint64_t snd_reservation : 1; + uint64_t spare6 : 2; + uint64_t snd_nodeid : 3; + uint64_t snd_chipid : 3; + uint64_t spare14 : 2; + uint64_t _reserved0 : 48; +#else + uint64_t _reserved0 : 48; + uint64_t spare14 : 2; + uint64_t snd_chipid : 3; + uint64_t snd_nodeid : 3; + uint64_t spare6 : 2; + uint64_t snd_reservation : 1; + uint64_t snd_type : 1; + uint64_t snd_qid : 1; + uint64_t snd_scope : 3; +#endif // _BIG_ENDIAN + } fields; +} pba_xsndtx_t; + + + +typedef union pba_xcfg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pbax_en : 1; + uint64_t reservation_en : 1; + uint64_t snd_reset : 1; + uint64_t rcv_reset : 1; + uint64_t rcv_nodeid : 3; + uint64_t rcv_chipid : 3; + uint64_t spare10 : 2; + uint64_t rcv_brdcst_group : 8; + uint64_t rcv_datato_div : 5; + uint64_t spare25 : 2; + uint64_t snd_retry_count_overcom : 1; + uint64_t snd_retry_thresh : 8; + uint64_t snd_rsvto_div : 5; + uint64_t _reserved0 : 23; +#else + uint64_t _reserved0 : 23; + uint64_t snd_rsvto_div : 5; + uint64_t snd_retry_thresh : 8; + uint64_t snd_retry_count_overcom : 1; + uint64_t spare25 : 2; + uint64_t rcv_datato_div : 5; + uint64_t rcv_brdcst_group : 8; + uint64_t spare10 : 2; + uint64_t rcv_chipid : 3; + uint64_t rcv_nodeid : 3; + uint64_t rcv_reset : 1; + uint64_t snd_reset : 1; + uint64_t reservation_en : 1; + uint64_t pbax_en : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_xcfg_t; + + + +typedef union pba_xsndstat { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t snd_in_progress : 1; + uint64_t snd_error : 1; + uint64_t snd_status : 6; + uint64_t snd_retry_count : 8; + uint64_t _reserved0 : 48; +#else + uint64_t _reserved0 : 48; + uint64_t snd_retry_count : 8; + uint64_t snd_status : 6; + uint64_t snd_error : 1; + uint64_t snd_in_progress : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_xsndstat_t; + + + +typedef union pba_xsnddat { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pbax_datahi : 32; + uint64_t pbax_datalo : 32; +#else + uint64_t pbax_datalo : 32; + uint64_t pbax_datahi : 32; +#endif // _BIG_ENDIAN + } fields; +} pba_xsnddat_t; + + + +typedef union pba_xrcvstat { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t rcv_in_progress : 1; + uint64_t rcv_error : 1; + uint64_t rcv_write_in_progress : 1; + uint64_t rcv_reservation_set : 1; + uint64_t rcv_capture : 14; + uint64_t _reserved0 : 46; +#else + uint64_t _reserved0 : 46; + uint64_t rcv_capture : 14; + uint64_t rcv_reservation_set : 1; + uint64_t rcv_write_in_progress : 1; + uint64_t rcv_error : 1; + uint64_t rcv_in_progress : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_xrcvstat_t; + + + +typedef union pba_xshbrn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t push_start : 29; + uint64_t _reserved0 : 35; +#else + uint64_t _reserved0 : 35; + uint64_t push_start : 29; +#endif // _BIG_ENDIAN + } fields; +} pba_xshbrn_t; + + + +typedef union pba_xshcsn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t push_full : 1; + uint64_t push_empty : 1; + uint64_t spare1 : 2; + uint64_t push_intr_action : 2; + uint64_t push_length : 5; + uint64_t notimp1 : 2; + uint64_t push_write_ptr : 5; + uint64_t notimp2 : 3; + uint64_t push_read_ptr : 5; + uint64_t notimp3 : 5; + uint64_t push_enable : 1; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t push_enable : 1; + uint64_t notimp3 : 5; + uint64_t push_read_ptr : 5; + uint64_t notimp2 : 3; + uint64_t push_write_ptr : 5; + uint64_t notimp1 : 2; + uint64_t push_length : 5; + uint64_t push_intr_action : 2; + uint64_t spare1 : 2; + uint64_t push_empty : 1; + uint64_t push_full : 1; +#endif // _BIG_ENDIAN + } fields; +} pba_xshcsn_t; + + + +typedef union pba_xshincn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved : 64; +#else + uint64_t reserved : 64; +#endif // _BIG_ENDIAN + } fields; +} pba_xshincn_t; + + +#endif // __ASSEMBLER__ +#endif // __PBA_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/pba_register_addresses.h b/src/ssx/pgp/registers/pba_register_addresses.h new file mode 100755 index 0000000..1703629 --- /dev/null +++ b/src/ssx/pgp/registers/pba_register_addresses.h @@ -0,0 +1,94 @@ +#ifndef __PBA_REGISTER_ADDRESSES_H__ +#define __PBA_REGISTER_ADDRESSES_H__ + +// $Id: pba_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pba_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file pba_register_addresses.h +/// \brief Symbolic addresses for the PBA unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define TRUSTEDPIB_BASE 0x02013f00 +#define PBA_BARN(n) (PBA_BAR0 + ((PBA_BAR1 - PBA_BAR0) * (n))) +#define PBA_BAR0 0x02013f00 +#define PBA_BAR1 0x02013f01 +#define PBA_BAR2 0x02013f02 +#define PBA_BAR3 0x02013f03 +#define PBA_BARMSKN(n) (PBA_BARMSK0 + ((PBA_BARMSK1 - PBA_BARMSK0) * (n))) +#define PBA_BARMSK0 0x02013f04 +#define PBA_BARMSK1 0x02013f05 +#define PBA_BARMSK2 0x02013f06 +#define PBA_BARMSK3 0x02013f07 +#define PIB_BASE 0x02010840 +#define PBA_FIR 0x02010840 +#define PBA_FIR_AND 0x02010841 +#define PBA_FIR_OR 0x02010842 +#define PBA_FIRMASK 0x02010843 +#define PBA_FIRMASK_AND 0x02010844 +#define PBA_FIRMASK_OR 0x02010845 +#define PBA_FIRACT0 0x02010846 +#define PBA_FIRACT1 0x02010847 +#define PBA_OCCACT 0x0201084a +#define PBA_CFG 0x0201084b +#define PBA_ERRPT0 0x0201084c +#define PBA_ERRPT1 0x0201084d +#define PBA_ERRPT2 0x0201084e +#define PBA_RBUFVALN(n) (PBA_RBUFVAL0 + ((PBA_RBUFVAL1 - PBA_RBUFVAL0) * (n))) +#define PBA_RBUFVAL0 0x02010850 +#define PBA_RBUFVAL1 0x02010851 +#define PBA_RBUFVAL2 0x02010852 +#define PBA_RBUFVAL3 0x02010853 +#define PBA_RBUFVAL4 0x02010854 +#define PBA_RBUFVAL5 0x02010855 +#define PBA_WBUFVALN(n) (PBA_WBUFVAL0 + ((PBA_WBUFVAL1 - PBA_WBUFVAL0) * (n))) +#define PBA_WBUFVAL0 0x02010858 +#define PBA_WBUFVAL1 0x02010859 +#define OCI_BASE 0x40020000 +#define PBA_MODE 0x40020000 +#define PBA_SLVRST 0x40020008 +#define PBA_SLVCTLN(n) (PBA_SLVCTL0 + ((PBA_SLVCTL1 - PBA_SLVCTL0) * (n))) +#define PBA_SLVCTL0 0x40020020 +#define PBA_SLVCTL1 0x40020028 +#define PBA_SLVCTL2 0x40020030 +#define PBA_SLVCTL3 0x40020038 +#define PBA_BCDE_CTL 0x40020080 +#define PBA_BCDE_SET 0x40020088 +#define PBA_BCDE_STAT 0x40020090 +#define PBA_BCDE_PBADR 0x40020098 +#define PBA_BCDE_OCIBAR 0x400200a0 +#define PBA_BCUE_CTL 0x400200a8 +#define PBA_BCUE_SET 0x400200b0 +#define PBA_BCUE_STAT 0x400200b8 +#define PBA_BCUE_PBADR 0x400200c0 +#define PBA_BCUE_OCIBAR 0x400200c8 +#define PBA_PBOCRN(n) (PBA_PBOCR0 + ((PBA_PBOCR1 - PBA_PBOCR0) * (n))) +#define PBA_PBOCR0 0x400200d0 +#define PBA_PBOCR1 0x400200d8 +#define PBA_PBOCR2 0x400200e0 +#define PBA_PBOCR3 0x400200e8 +#define PBA_PBOCR4 0x400200f0 +#define PBA_PBOCR5 0x400200f8 +#define PBA_XSNDTX 0x40020100 +#define PBA_XCFG 0x40020108 +#define PBA_XSNDSTAT 0x40020110 +#define PBA_XSNDDAT 0x40020118 +#define PBA_XRCVSTAT 0x40020120 +#define PBA_XSHBRN(n) (PBA_XSHBR0 + ((PBA_XSHBR1 - PBA_XSHBR0) * (n))) +#define PBA_XSHBR0 0x40020130 +#define PBA_XSHBR1 0x40020150 +#define PBA_XSHCSN(n) (PBA_XSHCS0 + ((PBA_XSHCS1 - PBA_XSHCS0) * (n))) +#define PBA_XSHCS0 0x40020138 +#define PBA_XSHCS1 0x40020158 +#define PBA_XSHINCN(n) (PBA_XSHINC0 + ((PBA_XSHINC1 - PBA_XSHINC0) * (n))) +#define PBA_XSHINC0 0x40020140 +#define PBA_XSHINC1 0x40020160 + +#endif // __PBA_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/pc_firmware_registers.h b/src/ssx/pgp/registers/pc_firmware_registers.h new file mode 100755 index 0000000..2c86308 --- /dev/null +++ b/src/ssx/pgp/registers/pc_firmware_registers.h @@ -0,0 +1,442 @@ +#ifndef __PC_FIRMWARE_REGISTERS_H__ +#define __PC_FIRMWARE_REGISTERS_H__ + +// $Id: pc_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pc_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file pc_firmware_registers.h +/// \brief C register structs for the PC unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union pc_pfth_modereg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pfth_cntr_dis : 1; + uint64_t pfth_charac_mode : 1; + uint64_t pfth_cntr_run_latch_gate_dis : 1; + uint64_t sprd_pfth_tx_run_latches : 8; + uint64_t tx_threads_stopped : 8; + uint64_t _reserved0 : 45; +#else + uint64_t _reserved0 : 45; + uint64_t tx_threads_stopped : 8; + uint64_t sprd_pfth_tx_run_latches : 8; + uint64_t pfth_cntr_run_latch_gate_dis : 1; + uint64_t pfth_charac_mode : 1; + uint64_t pfth_cntr_dis : 1; +#endif // _BIG_ENDIAN + } fields; +} pc_pfth_modereg_t; + + + +typedef union pc_occ_sprc { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved0 : 53; + uint64_t autoinc : 1; + uint64_t sprn : 7; + uint64_t reserved1 : 3; +#else + uint64_t reserved1 : 3; + uint64_t sprn : 7; + uint64_t autoinc : 1; + uint64_t reserved0 : 53; +#endif // _BIG_ENDIAN + } fields; +} pc_occ_sprc_t; + + + +typedef union pc_occ_sprd { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} pc_occ_sprd_t; + + + +typedef union pc_pfth_oha_instr_cnt_sel { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 62; + uint64_t value : 2; +#else + uint64_t value : 2; + uint64_t _reserved0 : 62; +#endif // _BIG_ENDIAN + } fields; +} pc_pfth_oha_instr_cnt_sel_t; + + + +typedef union pc_pfth_throt_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t didt_trigger_enable : 1; + uint64_t isu_trigger_enable : 1; + uint64_t didt_throttle : 2; + uint64_t uthrottle : 2; + uint64_t force_suppress_speedup : 1; + uint64_t suppress_speedup_on_throttle : 1; + uint64_t core_slowdown : 1; + uint64_t suppress_on_slowdown : 1; + uint64_t isu_only_count_mode : 1; + uint64_t spare : 5; + uint64_t reserved : 48; +#else + uint64_t reserved : 48; + uint64_t spare : 5; + uint64_t isu_only_count_mode : 1; + uint64_t suppress_on_slowdown : 1; + uint64_t core_slowdown : 1; + uint64_t suppress_speedup_on_throttle : 1; + uint64_t force_suppress_speedup : 1; + uint64_t uthrottle : 2; + uint64_t didt_throttle : 2; + uint64_t isu_trigger_enable : 1; + uint64_t didt_trigger_enable : 1; +#endif // _BIG_ENDIAN + } fields; +} pc_pfth_throt_reg_t; + + + +typedef union pc_direct_controln { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved0 : 42; + uint64_t dc_prestart_sleep : 1; + uint64_t dc_prestart_winkle : 1; + uint64_t dc_clear_maint : 1; + uint64_t dc_ntc_flush : 1; + uint64_t reserved46 : 1; + uint64_t dc_prestart_nap : 1; + uint64_t dc_cancel_lost : 1; + uint64_t dc_reset_maint : 1; + uint64_t reserved50 : 1; + uint64_t dc_set_maint : 1; + uint64_t dc_goto_quiesce_state : 1; + uint64_t reserved53 : 1; + uint64_t dc_inj_test_hang : 2; + uint64_t dc_core_running : 1; + uint64_t dc_hang_inject : 1; + uint64_t dc_smt_start_suppress : 1; + uint64_t reserved59 : 1; + uint64_t dc_sreset_request : 1; + uint64_t dc_core_step : 1; + uint64_t dc_core_start : 1; + uint64_t dc_core_stop : 1; +#else + uint64_t dc_core_stop : 1; + uint64_t dc_core_start : 1; + uint64_t dc_core_step : 1; + uint64_t dc_sreset_request : 1; + uint64_t reserved59 : 1; + uint64_t dc_smt_start_suppress : 1; + uint64_t dc_hang_inject : 1; + uint64_t dc_core_running : 1; + uint64_t dc_inj_test_hang : 2; + uint64_t reserved53 : 1; + uint64_t dc_goto_quiesce_state : 1; + uint64_t dc_set_maint : 1; + uint64_t reserved50 : 1; + uint64_t dc_reset_maint : 1; + uint64_t dc_cancel_lost : 1; + uint64_t dc_prestart_nap : 1; + uint64_t reserved46 : 1; + uint64_t dc_ntc_flush : 1; + uint64_t dc_clear_maint : 1; + uint64_t dc_prestart_winkle : 1; + uint64_t dc_prestart_sleep : 1; + uint64_t reserved0 : 42; +#endif // _BIG_ENDIAN + } fields; +} pc_direct_controln_t; + + + +typedef union pc_ras_moderegn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved0 : 43; + uint64_t mr_thread_in_debug_mode : 1; + uint64_t mr_pmon_inhibit : 1; + uint64_t mr_fence_interrupts : 1; + uint64_t mr_stop_fetch : 1; + uint64_t mr_stop_prefetch : 1; + uint64_t mr_stop_dispatch : 1; + uint64_t mr_single_decode : 1; + uint64_t mr_do_single_mode : 1; + uint64_t mr_one_ppc_mode : 1; + uint64_t mr_hang_test_ctrl : 2; + uint64_t mr_attempt_gps_hr : 3; + uint64_t mr_hang_dis : 1; + uint64_t mr_on_corehng : 1; + uint64_t mr_on_ambihng : 1; + uint64_t mr_on_nesthng : 1; + uint64_t mr_recov_enable : 1; + uint64_t mr_block_hmi_on_maint : 1; + uint64_t mr_fence_intr_on_checkstop : 1; +#else + uint64_t mr_fence_intr_on_checkstop : 1; + uint64_t mr_block_hmi_on_maint : 1; + uint64_t mr_recov_enable : 1; + uint64_t mr_on_nesthng : 1; + uint64_t mr_on_ambihng : 1; + uint64_t mr_on_corehng : 1; + uint64_t mr_hang_dis : 1; + uint64_t mr_attempt_gps_hr : 3; + uint64_t mr_hang_test_ctrl : 2; + uint64_t mr_one_ppc_mode : 1; + uint64_t mr_do_single_mode : 1; + uint64_t mr_single_decode : 1; + uint64_t mr_stop_dispatch : 1; + uint64_t mr_stop_prefetch : 1; + uint64_t mr_stop_fetch : 1; + uint64_t mr_fence_interrupts : 1; + uint64_t mr_pmon_inhibit : 1; + uint64_t mr_thread_in_debug_mode : 1; + uint64_t reserved0 : 43; +#endif // _BIG_ENDIAN + } fields; +} pc_ras_moderegn_t; + + + +typedef union pc_ras_statusn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t quiesce_status : 20; + uint64_t reserved20 : 1; + uint64_t reserved21 : 1; + uint64_t reserved22 : 1; + uint64_t other_thread_active : 1; + uint64_t hang_fsm : 3; + uint64_t reserved27 : 1; + uint64_t hang_hist0 : 1; + uint64_t hang_hist1 : 1; + uint64_t hang_hist2 : 1; + uint64_t hang_hist3 : 1; + uint64_t reserved32 : 1; + uint64_t hr_comp_cnt : 8; + uint64_t smt_dead_stop : 1; + uint64_t stop_fetch : 1; + uint64_t stop_dispatch : 1; + uint64_t stop_completion : 1; + uint64_t hold_decode : 1; + uint64_t reserved46 : 1; + uint64_t reserved47 : 1; + uint64_t thread_enabled : 1; + uint64_t pow_status_thread_state : 4; + uint64_t reserved53 : 1; + uint64_t maint_single_mode : 1; + uint64_t reserved55 : 1; + uint64_t reserved56 : 1; + uint64_t reserved57 : 7; +#else + uint64_t reserved57 : 7; + uint64_t reserved56 : 1; + uint64_t reserved55 : 1; + uint64_t maint_single_mode : 1; + uint64_t reserved53 : 1; + uint64_t pow_status_thread_state : 4; + uint64_t thread_enabled : 1; + uint64_t reserved47 : 1; + uint64_t reserved46 : 1; + uint64_t hold_decode : 1; + uint64_t stop_completion : 1; + uint64_t stop_dispatch : 1; + uint64_t stop_fetch : 1; + uint64_t smt_dead_stop : 1; + uint64_t hr_comp_cnt : 8; + uint64_t reserved32 : 1; + uint64_t hang_hist3 : 1; + uint64_t hang_hist2 : 1; + uint64_t hang_hist1 : 1; + uint64_t hang_hist0 : 1; + uint64_t reserved27 : 1; + uint64_t hang_fsm : 3; + uint64_t other_thread_active : 1; + uint64_t reserved22 : 1; + uint64_t reserved21 : 1; + uint64_t reserved20 : 1; + uint64_t quiesce_status : 20; +#endif // _BIG_ENDIAN + } fields; +} pc_ras_statusn_t; + + + +typedef union pc_pow_statusn { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t thread_state : 4; + uint64_t thread_pow_state : 2; + uint64_t smt_mode : 3; + uint64_t hmi_intr : 1; + uint64_t maybe_ext_intr : 1; + uint64_t decr_intr : 1; + uint64_t maybe_debug_intr : 1; + uint64_t hdec_intr : 1; + uint64_t maybe_pmu_intr : 1; + uint64_t sp_attn_intr : 1; + uint64_t sreset_type : 3; + uint64_t reserved19 : 1; + uint64_t sreset_pending : 1; + uint64_t debug_fetch_stop : 1; + uint64_t async_pending : 1; + uint64_t core_pow_state : 3; + uint64_t reserved26 : 3; + uint64_t _reserved0 : 35; +#else + uint64_t _reserved0 : 35; + uint64_t reserved26 : 3; + uint64_t core_pow_state : 3; + uint64_t async_pending : 1; + uint64_t debug_fetch_stop : 1; + uint64_t sreset_pending : 1; + uint64_t reserved19 : 1; + uint64_t sreset_type : 3; + uint64_t sp_attn_intr : 1; + uint64_t maybe_pmu_intr : 1; + uint64_t hdec_intr : 1; + uint64_t maybe_debug_intr : 1; + uint64_t decr_intr : 1; + uint64_t maybe_ext_intr : 1; + uint64_t hmi_intr : 1; + uint64_t smt_mode : 3; + uint64_t thread_pow_state : 2; + uint64_t thread_state : 4; +#endif // _BIG_ENDIAN + } fields; +} pc_pow_statusn_t; + + +#endif // __ASSEMBLER__ +#endif // __PC_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/pc_register_addresses.h b/src/ssx/pgp/registers/pc_register_addresses.h new file mode 100755 index 0000000..8b9baf2 --- /dev/null +++ b/src/ssx/pgp/registers/pc_register_addresses.h @@ -0,0 +1,61 @@ +#ifndef __PC_REGISTER_ADDRESSES_H__ +#define __PC_REGISTER_ADDRESSES_H__ + +// $Id: pc_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pc_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file pc_register_addresses.h +/// \brief Symbolic addresses for the PC unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define PC_PCB_BASE 0x10010000 +#define PC_PFTH_MODEREG 0x100132a7 +#define PC_OCC_SPRC 0x100132ab +#define PC_OCC_SPRD 0x100132ac +#define PC_PFTH_THROT_REG 0x100132ad +#define PC_DIRECT_CONTROLN(n) (PC_DIRECT_CONTROL0 + ((PC_DIRECT_CONTROL1 - PC_DIRECT_CONTROL0) * (n))) +#define PC_DIRECT_CONTROL0 0x10013000 +#define PC_DIRECT_CONTROL1 0x10013010 +#define PC_DIRECT_CONTROL2 0x10013020 +#define PC_DIRECT_CONTROL3 0x10013030 +#define PC_DIRECT_CONTROL4 0x10013040 +#define PC_DIRECT_CONTROL5 0x10013050 +#define PC_DIRECT_CONTROL6 0x10013060 +#define PC_DIRECT_CONTROL7 0x10013070 +#define PC_RAS_MODEREGN(n) (PC_RAS_MODEREG0 + ((PC_RAS_MODEREG1 - PC_RAS_MODEREG0) * (n))) +#define PC_RAS_MODEREG0 0x10013001 +#define PC_RAS_MODEREG1 0x10013011 +#define PC_RAS_MODEREG2 0x10013021 +#define PC_RAS_MODEREG3 0x10013031 +#define PC_RAS_MODEREG4 0x10013041 +#define PC_RAS_MODEREG5 0x10013051 +#define PC_RAS_MODEREG6 0x10013061 +#define PC_RAS_MODEREG7 0x10013071 +#define PC_RAS_STATUSN(n) (PC_RAS_STATUS0 + ((PC_RAS_STATUS1 - PC_RAS_STATUS0) * (n))) +#define PC_RAS_STATUS0 0x10013002 +#define PC_RAS_STATUS1 0x10013012 +#define PC_RAS_STATUS2 0x10013022 +#define PC_RAS_STATUS3 0x10013032 +#define PC_RAS_STATUS4 0x10013042 +#define PC_RAS_STATUS5 0x10013052 +#define PC_RAS_STATUS6 0x10013062 +#define PC_RAS_STATUS7 0x10013072 +#define PC_POW_STATUSN(n) (PC_POW_STATUS0 + ((PC_POW_STATUS1 - PC_POW_STATUS0) * (n))) +#define PC_POW_STATUS0 0x10013004 +#define PC_POW_STATUS1 0x10013014 +#define PC_POW_STATUS2 0x10013024 +#define PC_POW_STATUS3 0x10013034 +#define PC_POW_STATUS4 0x10013044 +#define PC_POW_STATUS5 0x10013054 +#define PC_POW_STATUS6 0x10013064 +#define PC_POW_STATUS7 0x10013074 + +#endif // __PC_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/pcbs_firmware_registers.h b/src/ssx/pgp/registers/pcbs_firmware_registers.h new file mode 100755 index 0000000..1d268a2 --- /dev/null +++ b/src/ssx/pgp/registers/pcbs_firmware_registers.h @@ -0,0 +1,2477 @@ +#ifndef __PCBS_FIRMWARE_REGISTERS_H__ +#define __PCBS_FIRMWARE_REGISTERS_H__ + +// $Id: pcbs_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pcbs_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file pcbs_firmware_registers.h +/// \brief C register structs for the PCBS unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union pcbs_pmgp0_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pm_disable : 1; + uint64_t pmgp0_spare_bit1 : 1; + uint64_t tp_tc_restart_core_domain : 1; + uint64_t dpll_thold : 1; + uint64_t perv_thold : 1; + uint64_t cpm_cal_set_override_en : 1; + uint64_t cpm_cal_set_val : 1; + uint64_t pm_dpll_timer_ena : 1; + uint64_t dpll_lock_sense : 1; + uint64_t pmgp0_spare2 : 1; + uint64_t dpll_reset : 1; + uint64_t pmgp0_spare_bit11 : 1; + uint64_t dpll_testout_ctl : 8; + uint64_t tp_tc_cache2core_fence : 1; + uint64_t tp_tc_core2cache_fence : 1; + uint64_t tp_tc_pervasive_eco_fence : 1; + uint64_t chksw_hw257424_disable : 1; + uint64_t tp_clk_async_reset_dc : 3; + uint64_t tp_clkglm_sel_dc : 3; + uint64_t tp_clkglm_eco_sel_dc : 1; + uint64_t special_wkup_done : 1; + uint64_t tp_clkglm_core_sel_dc : 2; + uint64_t tp_clkglm_const_dc : 1; + uint64_t thold_timer_sel : 2; + uint64_t block_all_wakeup_sources : 1; + uint64_t tp_tc_dpll_testmode_dc : 1; + uint64_t pm_slv_winkle_fence : 1; + uint64_t l3_enable_switch : 1; + uint64_t tp_cplt_ivrm_refbypass_dc : 1; + uint64_t chksw_hw241939_disable : 1; + uint64_t chksw_hw273115_disable : 1; + uint64_t chksw_hw245103_disable : 1; + uint64_t chksw_hw257534_disable : 1; + uint64_t chksw_hw259509_enable : 1; + uint64_t pmgp0_spare3 : 1; + uint64_t wakeup_int_type : 2; + uint64_t dpll_lock : 1; + uint64_t special_wkup_all_sources_ored : 1; + uint64_t regular_wkup_available : 1; + uint64_t block_reg_wkup_sources : 1; + uint64_t _reserved0 : 10; +#else + uint64_t _reserved0 : 10; + uint64_t block_reg_wkup_sources : 1; + uint64_t regular_wkup_available : 1; + uint64_t special_wkup_all_sources_ored : 1; + uint64_t dpll_lock : 1; + uint64_t wakeup_int_type : 2; + uint64_t pmgp0_spare3 : 1; + uint64_t chksw_hw259509_enable : 1; + uint64_t chksw_hw257534_disable : 1; + uint64_t chksw_hw245103_disable : 1; + uint64_t chksw_hw273115_disable : 1; + uint64_t chksw_hw241939_disable : 1; + uint64_t tp_cplt_ivrm_refbypass_dc : 1; + uint64_t l3_enable_switch : 1; + uint64_t pm_slv_winkle_fence : 1; + uint64_t tp_tc_dpll_testmode_dc : 1; + uint64_t block_all_wakeup_sources : 1; + uint64_t thold_timer_sel : 2; + uint64_t tp_clkglm_const_dc : 1; + uint64_t tp_clkglm_core_sel_dc : 2; + uint64_t special_wkup_done : 1; + uint64_t tp_clkglm_eco_sel_dc : 1; + uint64_t tp_clkglm_sel_dc : 3; + uint64_t tp_clk_async_reset_dc : 3; + uint64_t chksw_hw257424_disable : 1; + uint64_t tp_tc_pervasive_eco_fence : 1; + uint64_t tp_tc_core2cache_fence : 1; + uint64_t tp_tc_cache2core_fence : 1; + uint64_t dpll_testout_ctl : 8; + uint64_t pmgp0_spare_bit11 : 1; + uint64_t dpll_reset : 1; + uint64_t pmgp0_spare2 : 1; + uint64_t dpll_lock_sense : 1; + uint64_t pm_dpll_timer_ena : 1; + uint64_t cpm_cal_set_val : 1; + uint64_t cpm_cal_set_override_en : 1; + uint64_t perv_thold : 1; + uint64_t dpll_thold : 1; + uint64_t tp_tc_restart_core_domain : 1; + uint64_t pmgp0_spare_bit1 : 1; + uint64_t pm_disable : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmgp0_reg_t; + + + +typedef union pcbs_pmgp0_reg_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pm_disable : 1; + uint64_t pmgp0_spare_bit1 : 1; + uint64_t tp_tc_restart_core_domain : 1; + uint64_t dpll_thold : 1; + uint64_t perv_thold : 1; + uint64_t cpm_cal_set_override_en : 1; + uint64_t cpm_cal_set_val : 1; + uint64_t pm_dpll_timer_ena : 1; + uint64_t dpll_lock_sense : 1; + uint64_t pmgp0_spare2 : 1; + uint64_t dpll_reset : 1; + uint64_t pmgp0_spare_bit11 : 1; + uint64_t dpll_testout_ctl : 8; + uint64_t tp_tc_cache2core_fence : 1; + uint64_t tp_tc_core2cache_fence : 1; + uint64_t tp_tc_pervasive_eco_fence : 1; + uint64_t chksw_hw257424_disable : 1; + uint64_t tp_clk_async_reset_dc : 3; + uint64_t tp_clkglm_sel_dc : 3; + uint64_t tp_clkglm_eco_sel_dc : 1; + uint64_t special_wkup_done : 1; + uint64_t tp_clkglm_core_sel_dc : 2; + uint64_t tp_clkglm_const_dc : 1; + uint64_t thold_timer_sel : 2; + uint64_t block_all_wakeup_sources : 1; + uint64_t tp_tc_dpll_testmode_dc : 1; + uint64_t pm_slv_winkle_fence : 1; + uint64_t l3_enable_switch : 1; + uint64_t tp_cplt_ivrm_refbypass_dc : 1; + uint64_t chksw_hw241939_disable : 1; + uint64_t chksw_hw273115_disable : 1; + uint64_t chksw_hw245103_disable : 1; + uint64_t chksw_hw257534_disable : 1; + uint64_t chksw_hw259509_enable : 1; + uint64_t pmgp0_spare3 : 1; + uint64_t wakeup_int_type : 2; + uint64_t dpll_lock : 1; + uint64_t special_wkup_all_sources_ored : 1; + uint64_t regular_wkup_available : 1; + uint64_t block_reg_wkup_sources : 1; + uint64_t _reserved0 : 10; +#else + uint64_t _reserved0 : 10; + uint64_t block_reg_wkup_sources : 1; + uint64_t regular_wkup_available : 1; + uint64_t special_wkup_all_sources_ored : 1; + uint64_t dpll_lock : 1; + uint64_t wakeup_int_type : 2; + uint64_t pmgp0_spare3 : 1; + uint64_t chksw_hw259509_enable : 1; + uint64_t chksw_hw257534_disable : 1; + uint64_t chksw_hw245103_disable : 1; + uint64_t chksw_hw273115_disable : 1; + uint64_t chksw_hw241939_disable : 1; + uint64_t tp_cplt_ivrm_refbypass_dc : 1; + uint64_t l3_enable_switch : 1; + uint64_t pm_slv_winkle_fence : 1; + uint64_t tp_tc_dpll_testmode_dc : 1; + uint64_t block_all_wakeup_sources : 1; + uint64_t thold_timer_sel : 2; + uint64_t tp_clkglm_const_dc : 1; + uint64_t tp_clkglm_core_sel_dc : 2; + uint64_t special_wkup_done : 1; + uint64_t tp_clkglm_eco_sel_dc : 1; + uint64_t tp_clkglm_sel_dc : 3; + uint64_t tp_clk_async_reset_dc : 3; + uint64_t chksw_hw257424_disable : 1; + uint64_t tp_tc_pervasive_eco_fence : 1; + uint64_t tp_tc_core2cache_fence : 1; + uint64_t tp_tc_cache2core_fence : 1; + uint64_t dpll_testout_ctl : 8; + uint64_t pmgp0_spare_bit11 : 1; + uint64_t dpll_reset : 1; + uint64_t pmgp0_spare2 : 1; + uint64_t dpll_lock_sense : 1; + uint64_t pm_dpll_timer_ena : 1; + uint64_t cpm_cal_set_val : 1; + uint64_t cpm_cal_set_override_en : 1; + uint64_t perv_thold : 1; + uint64_t dpll_thold : 1; + uint64_t tp_tc_restart_core_domain : 1; + uint64_t pmgp0_spare_bit1 : 1; + uint64_t pm_disable : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmgp0_reg_and_t; + + + +typedef union pcbs_pmgp0_reg_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pm_disable : 1; + uint64_t pmgp0_spare_bit1 : 1; + uint64_t tp_tc_restart_core_domain : 1; + uint64_t dpll_thold : 1; + uint64_t perv_thold : 1; + uint64_t cpm_cal_set_override_en : 1; + uint64_t cpm_cal_set_val : 1; + uint64_t pm_dpll_timer_ena : 1; + uint64_t dpll_lock_sense : 1; + uint64_t pmgp0_spare2 : 1; + uint64_t dpll_reset : 1; + uint64_t pmgp0_spare_bit11 : 1; + uint64_t dpll_testout_ctl : 8; + uint64_t tp_tc_cache2core_fence : 1; + uint64_t tp_tc_core2cache_fence : 1; + uint64_t tp_tc_pervasive_eco_fence : 1; + uint64_t chksw_hw257424_disable : 1; + uint64_t tp_clk_async_reset_dc : 3; + uint64_t tp_clkglm_sel_dc : 3; + uint64_t tp_clkglm_eco_sel_dc : 1; + uint64_t special_wkup_done : 1; + uint64_t tp_clkglm_core_sel_dc : 2; + uint64_t tp_clkglm_const_dc : 1; + uint64_t thold_timer_sel : 2; + uint64_t block_all_wakeup_sources : 1; + uint64_t tp_tc_dpll_testmode_dc : 1; + uint64_t pm_slv_winkle_fence : 1; + uint64_t l3_enable_switch : 1; + uint64_t tp_cplt_ivrm_refbypass_dc : 1; + uint64_t chksw_hw241939_disable : 1; + uint64_t chksw_hw273115_disable : 1; + uint64_t chksw_hw245103_disable : 1; + uint64_t chksw_hw257534_disable : 1; + uint64_t chksw_hw259509_enable : 1; + uint64_t pmgp0_spare3 : 1; + uint64_t wakeup_int_type : 2; + uint64_t dpll_lock : 1; + uint64_t special_wkup_all_sources_ored : 1; + uint64_t regular_wkup_available : 1; + uint64_t block_reg_wkup_sources : 1; + uint64_t _reserved0 : 10; +#else + uint64_t _reserved0 : 10; + uint64_t block_reg_wkup_sources : 1; + uint64_t regular_wkup_available : 1; + uint64_t special_wkup_all_sources_ored : 1; + uint64_t dpll_lock : 1; + uint64_t wakeup_int_type : 2; + uint64_t pmgp0_spare3 : 1; + uint64_t chksw_hw259509_enable : 1; + uint64_t chksw_hw257534_disable : 1; + uint64_t chksw_hw245103_disable : 1; + uint64_t chksw_hw273115_disable : 1; + uint64_t chksw_hw241939_disable : 1; + uint64_t tp_cplt_ivrm_refbypass_dc : 1; + uint64_t l3_enable_switch : 1; + uint64_t pm_slv_winkle_fence : 1; + uint64_t tp_tc_dpll_testmode_dc : 1; + uint64_t block_all_wakeup_sources : 1; + uint64_t thold_timer_sel : 2; + uint64_t tp_clkglm_const_dc : 1; + uint64_t tp_clkglm_core_sel_dc : 2; + uint64_t special_wkup_done : 1; + uint64_t tp_clkglm_eco_sel_dc : 1; + uint64_t tp_clkglm_sel_dc : 3; + uint64_t tp_clk_async_reset_dc : 3; + uint64_t chksw_hw257424_disable : 1; + uint64_t tp_tc_pervasive_eco_fence : 1; + uint64_t tp_tc_core2cache_fence : 1; + uint64_t tp_tc_cache2core_fence : 1; + uint64_t dpll_testout_ctl : 8; + uint64_t pmgp0_spare_bit11 : 1; + uint64_t dpll_reset : 1; + uint64_t pmgp0_spare2 : 1; + uint64_t dpll_lock_sense : 1; + uint64_t pm_dpll_timer_ena : 1; + uint64_t cpm_cal_set_val : 1; + uint64_t cpm_cal_set_override_en : 1; + uint64_t perv_thold : 1; + uint64_t dpll_thold : 1; + uint64_t tp_tc_restart_core_domain : 1; + uint64_t pmgp0_spare_bit1 : 1; + uint64_t pm_disable : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmgp0_reg_or_t; + + + +typedef union pcbs_pmgp1_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t sleep_power_down_en : 1; + uint64_t sleep_power_up_en : 1; + uint64_t sleep_power_off_sel : 1; + uint64_t winkle_power_down_en : 1; + uint64_t winkle_power_up_en : 1; + uint64_t winkle_power_off_sel : 1; + uint64_t oha_wkup_override_en : 1; + uint64_t oha_pm_wkup_override : 1; + uint64_t oha_spc_wkup_override : 1; + uint64_t endp_reset_pm_only : 1; + uint64_t dpll_freq_override_enable : 1; + uint64_t pm_spr_override_en : 1; + uint64_t force_safe_mode : 1; + uint64_t ivrm_safe_mode_en : 1; + uint64_t ivrm_safe_mode_force_active : 1; + uint64_t pmicr_latency_en : 1; + uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1; + uint64_t serialize_pfet_powerdown : 1; + uint64_t serialize_pfet_powerup : 1; + uint64_t disable_force_deep_to_fast_sleep : 1; + uint64_t disable_force_deep_to_fast_winkle : 1; + uint64_t _reserved0 : 43; +#else + uint64_t _reserved0 : 43; + uint64_t disable_force_deep_to_fast_winkle : 1; + uint64_t disable_force_deep_to_fast_sleep : 1; + uint64_t serialize_pfet_powerup : 1; + uint64_t serialize_pfet_powerdown : 1; + uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1; + uint64_t pmicr_latency_en : 1; + uint64_t ivrm_safe_mode_force_active : 1; + uint64_t ivrm_safe_mode_en : 1; + uint64_t force_safe_mode : 1; + uint64_t pm_spr_override_en : 1; + uint64_t dpll_freq_override_enable : 1; + uint64_t endp_reset_pm_only : 1; + uint64_t oha_spc_wkup_override : 1; + uint64_t oha_pm_wkup_override : 1; + uint64_t oha_wkup_override_en : 1; + uint64_t winkle_power_off_sel : 1; + uint64_t winkle_power_up_en : 1; + uint64_t winkle_power_down_en : 1; + uint64_t sleep_power_off_sel : 1; + uint64_t sleep_power_up_en : 1; + uint64_t sleep_power_down_en : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmgp1_reg_t; + + + +typedef union pcbs_pmgp1_reg_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t sleep_power_down_en : 1; + uint64_t sleep_power_up_en : 1; + uint64_t sleep_power_off_sel : 1; + uint64_t winkle_power_down_en : 1; + uint64_t winkle_power_up_en : 1; + uint64_t winkle_power_off_sel : 1; + uint64_t oha_wkup_override_en : 1; + uint64_t oha_pm_wkup_override : 1; + uint64_t oha_spc_wkup_override : 1; + uint64_t endp_reset_pm_only : 1; + uint64_t dpll_freq_override_enable : 1; + uint64_t pm_spr_override_en : 1; + uint64_t force_safe_mode : 1; + uint64_t ivrm_safe_mode_en : 1; + uint64_t ivrm_safe_mode_force_active : 1; + uint64_t pmicr_latency_en : 1; + uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1; + uint64_t serialize_pfet_powerdown : 1; + uint64_t serialize_pfet_powerup : 1; + uint64_t disable_force_deep_to_fast_sleep : 1; + uint64_t disable_force_deep_to_fast_winkle : 1; + uint64_t _reserved0 : 43; +#else + uint64_t _reserved0 : 43; + uint64_t disable_force_deep_to_fast_winkle : 1; + uint64_t disable_force_deep_to_fast_sleep : 1; + uint64_t serialize_pfet_powerup : 1; + uint64_t serialize_pfet_powerdown : 1; + uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1; + uint64_t pmicr_latency_en : 1; + uint64_t ivrm_safe_mode_force_active : 1; + uint64_t ivrm_safe_mode_en : 1; + uint64_t force_safe_mode : 1; + uint64_t pm_spr_override_en : 1; + uint64_t dpll_freq_override_enable : 1; + uint64_t endp_reset_pm_only : 1; + uint64_t oha_spc_wkup_override : 1; + uint64_t oha_pm_wkup_override : 1; + uint64_t oha_wkup_override_en : 1; + uint64_t winkle_power_off_sel : 1; + uint64_t winkle_power_up_en : 1; + uint64_t winkle_power_down_en : 1; + uint64_t sleep_power_off_sel : 1; + uint64_t sleep_power_up_en : 1; + uint64_t sleep_power_down_en : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmgp1_reg_and_t; + + + +typedef union pcbs_pmgp1_reg_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t sleep_power_down_en : 1; + uint64_t sleep_power_up_en : 1; + uint64_t sleep_power_off_sel : 1; + uint64_t winkle_power_down_en : 1; + uint64_t winkle_power_up_en : 1; + uint64_t winkle_power_off_sel : 1; + uint64_t oha_wkup_override_en : 1; + uint64_t oha_pm_wkup_override : 1; + uint64_t oha_spc_wkup_override : 1; + uint64_t endp_reset_pm_only : 1; + uint64_t dpll_freq_override_enable : 1; + uint64_t pm_spr_override_en : 1; + uint64_t force_safe_mode : 1; + uint64_t ivrm_safe_mode_en : 1; + uint64_t ivrm_safe_mode_force_active : 1; + uint64_t pmicr_latency_en : 1; + uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1; + uint64_t serialize_pfet_powerdown : 1; + uint64_t serialize_pfet_powerup : 1; + uint64_t disable_force_deep_to_fast_sleep : 1; + uint64_t disable_force_deep_to_fast_winkle : 1; + uint64_t _reserved0 : 43; +#else + uint64_t _reserved0 : 43; + uint64_t disable_force_deep_to_fast_winkle : 1; + uint64_t disable_force_deep_to_fast_sleep : 1; + uint64_t serialize_pfet_powerup : 1; + uint64_t serialize_pfet_powerdown : 1; + uint64_t enable_occ_ctrl_for_local_pstate_eff_req : 1; + uint64_t pmicr_latency_en : 1; + uint64_t ivrm_safe_mode_force_active : 1; + uint64_t ivrm_safe_mode_en : 1; + uint64_t force_safe_mode : 1; + uint64_t pm_spr_override_en : 1; + uint64_t dpll_freq_override_enable : 1; + uint64_t endp_reset_pm_only : 1; + uint64_t oha_spc_wkup_override : 1; + uint64_t oha_pm_wkup_override : 1; + uint64_t oha_wkup_override_en : 1; + uint64_t winkle_power_off_sel : 1; + uint64_t winkle_power_up_en : 1; + uint64_t winkle_power_down_en : 1; + uint64_t sleep_power_off_sel : 1; + uint64_t sleep_power_up_en : 1; + uint64_t sleep_power_down_en : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmgp1_reg_or_t; + + + +typedef union pcbs_pfvddcntlstat_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t core_vdd_pfet_force_state : 2; + uint64_t eco_vdd_pfet_force_state : 2; + uint64_t core_vdd_pfet_val_override : 1; + uint64_t core_vdd_pfet_sel_override : 1; + uint64_t eco_vdd_pfet_val_override : 1; + uint64_t eco_vdd_pfet_sel_override : 1; + uint64_t core_vdd_pfet_enable_regulation_finger : 1; + uint64_t eco_vdd_pfet_enable_regulation_finger : 1; + uint64_t core_vdd_pfet_enable_value : 12; + uint64_t core_vdd_pfet_sel_value : 4; + uint64_t eco_vdd_pfet_enable_value : 12; + uint64_t eco_vdd_pfet_sel_value : 4; + uint64_t core_vdd_pg_state : 4; + uint64_t core_vdd_pg_sel : 4; + uint64_t eco_vdd_pg_state : 4; + uint64_t eco_vdd_pg_sel : 4; + uint64_t _reserved0 : 6; +#else + uint64_t _reserved0 : 6; + uint64_t eco_vdd_pg_sel : 4; + uint64_t eco_vdd_pg_state : 4; + uint64_t core_vdd_pg_sel : 4; + uint64_t core_vdd_pg_state : 4; + uint64_t eco_vdd_pfet_sel_value : 4; + uint64_t eco_vdd_pfet_enable_value : 12; + uint64_t core_vdd_pfet_sel_value : 4; + uint64_t core_vdd_pfet_enable_value : 12; + uint64_t eco_vdd_pfet_enable_regulation_finger : 1; + uint64_t core_vdd_pfet_enable_regulation_finger : 1; + uint64_t eco_vdd_pfet_sel_override : 1; + uint64_t eco_vdd_pfet_val_override : 1; + uint64_t core_vdd_pfet_sel_override : 1; + uint64_t core_vdd_pfet_val_override : 1; + uint64_t eco_vdd_pfet_force_state : 2; + uint64_t core_vdd_pfet_force_state : 2; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pfvddcntlstat_reg_t; + + + +typedef union pcbs_pfvcscntlstat_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t core_vcs_pfet_force_state : 2; + uint64_t eco_vcs_pfet_force_state : 2; + uint64_t core_vcs_pfet_val_override : 1; + uint64_t core_vcs_pfet_sel_override : 1; + uint64_t eco_vcs_pfet_val_override : 1; + uint64_t eco_vcs_pfet_sel_override : 1; + uint64_t core_vcs_pfet_enable_regulation_finger : 1; + uint64_t eco_vcs_pfet_enable_regulation_finger : 1; + uint64_t core_vcs_pfet_enable_value : 12; + uint64_t core_vcs_pfet_sel_value : 4; + uint64_t eco_vcs_pfet_enable_value : 12; + uint64_t eco_vcs_pfet_sel_value : 4; + uint64_t core_vcs_pg_state : 4; + uint64_t core_vcs_pg_sel : 4; + uint64_t eco_vcs_pg_state : 4; + uint64_t eco_vcs_pg_sel : 4; + uint64_t _reserved0 : 6; +#else + uint64_t _reserved0 : 6; + uint64_t eco_vcs_pg_sel : 4; + uint64_t eco_vcs_pg_state : 4; + uint64_t core_vcs_pg_sel : 4; + uint64_t core_vcs_pg_state : 4; + uint64_t eco_vcs_pfet_sel_value : 4; + uint64_t eco_vcs_pfet_enable_value : 12; + uint64_t core_vcs_pfet_sel_value : 4; + uint64_t core_vcs_pfet_enable_value : 12; + uint64_t eco_vcs_pfet_enable_regulation_finger : 1; + uint64_t core_vcs_pfet_enable_regulation_finger : 1; + uint64_t eco_vcs_pfet_sel_override : 1; + uint64_t eco_vcs_pfet_val_override : 1; + uint64_t core_vcs_pfet_sel_override : 1; + uint64_t core_vcs_pfet_val_override : 1; + uint64_t eco_vcs_pfet_force_state : 2; + uint64_t core_vcs_pfet_force_state : 2; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pfvcscntlstat_reg_t; + + + +typedef union pcbs_pfsense_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t tp_core_vdd_pfet_enable_sense : 12; + uint64_t tp_eco_vdd_pfet_enable_sense : 12; + uint64_t tp_core_vcs_pfet_enable_sense : 12; + uint64_t tp_eco_vcs_pfet_enable_sense : 12; + uint64_t _reserved0 : 16; +#else + uint64_t _reserved0 : 16; + uint64_t tp_eco_vcs_pfet_enable_sense : 12; + uint64_t tp_core_vcs_pfet_enable_sense : 12; + uint64_t tp_eco_vdd_pfet_enable_sense : 12; + uint64_t tp_core_vdd_pfet_enable_sense : 12; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pfsense_reg_t; + + + +typedef union pcbs_pmerrsum_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pm_error : 1; + uint64_t _reserved0 : 63; +#else + uint64_t _reserved0 : 63; + uint64_t pm_error : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmerrsum_reg_t; + + + +typedef union pcbs_pmerr_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pcbs_sleep_entry_notify_pmc_hang_err : 1; + uint64_t pcbs_sleep_entry_notify_pmc_assist_hang_err : 1; + uint64_t pcbs_sleep_entry_notify_pmc_err : 1; + uint64_t pcbs_sleep_exit_invoke_pore_err : 1; + uint64_t pcbs_winkle_entry_notify_pmc_err : 1; + uint64_t pcbs_winkle_entry_send_int_assist_err : 1; + uint64_t pcbs_winkle_exit_notify_pmc_err : 1; + uint64_t pcbs_wait_dpll_lock_err : 1; + uint64_t pcbs_spare8_err : 1; + uint64_t pcbs_winkle_exit_send_int_assist_err : 1; + uint64_t pcbs_winkle_exit_send_int_powup_assist_err : 1; + uint64_t pcbs_write_fsm_goto_reg_in_invalid_state_err : 1; + uint64_t pcbs_write_pmgp0_in_invalid_state_err : 1; + uint64_t pcbs_freq_overflow_in_pstate_mode_err : 1; + uint64_t pcbs_eco_rs_bypass_confusion_err : 1; + uint64_t pcbs_core_rs_bypass_confusion_err : 1; + uint64_t pcbs_read_lpst_in_pstate_mode_err : 1; + uint64_t pcbs_lpst_read_corr_err : 1; + uint64_t pcbs_lpst_read_uncorr_err : 1; + uint64_t pcbs_pfet_strength_overflow_err : 1; + uint64_t pcbs_vds_lookup_err : 1; + uint64_t pcbs_idle_interrupt_timeout_err : 1; + uint64_t pcbs_pstate_interrupt_timeout_err : 1; + uint64_t pcbs_global_actual_sync_interrupt_timeout_err : 1; + uint64_t pcbs_pmax_sync_interrupt_timeout_err : 1; + uint64_t pcbs_global_actual_pstate_protocol_err : 1; + uint64_t pcbs_pmax_protocol_err : 1; + uint64_t pcbs_ivrm_gross_or_fine_err : 1; + uint64_t pcbs_ivrm_range_err : 1; + uint64_t pcbs_dpll_cpm_fmin_err : 1; + uint64_t pcbs_dpll_dco_full_err : 1; + uint64_t pcbs_dpll_dco_empty_err : 1; + uint64_t pcbs_dpll_int_err : 1; + uint64_t pcbs_fmin_and_not_cpmbit_err : 1; + uint64_t pcbs_dpll_faster_than_fmax_plus_delta1_err : 1; + uint64_t pcbs_dpll_slower_than_fmin_minus_delta2_err : 1; + uint64_t pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err : 1; + uint64_t pcbs_reslkc_band_boundary_chg_in_invalid_state_err : 1; + uint64_t pcbs_occ_heartbeat_loss_err : 1; + uint64_t pcbs_spare39_err : 1; + uint64_t pcbs_spare40_err : 1; + uint64_t pcbs_spare41_err : 1; + uint64_t pcbs_spare42_err : 1; + uint64_t _reserved0 : 21; +#else + uint64_t _reserved0 : 21; + uint64_t pcbs_spare42_err : 1; + uint64_t pcbs_spare41_err : 1; + uint64_t pcbs_spare40_err : 1; + uint64_t pcbs_spare39_err : 1; + uint64_t pcbs_occ_heartbeat_loss_err : 1; + uint64_t pcbs_reslkc_band_boundary_chg_in_invalid_state_err : 1; + uint64_t pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err : 1; + uint64_t pcbs_dpll_slower_than_fmin_minus_delta2_err : 1; + uint64_t pcbs_dpll_faster_than_fmax_plus_delta1_err : 1; + uint64_t pcbs_fmin_and_not_cpmbit_err : 1; + uint64_t pcbs_dpll_int_err : 1; + uint64_t pcbs_dpll_dco_empty_err : 1; + uint64_t pcbs_dpll_dco_full_err : 1; + uint64_t pcbs_dpll_cpm_fmin_err : 1; + uint64_t pcbs_ivrm_range_err : 1; + uint64_t pcbs_ivrm_gross_or_fine_err : 1; + uint64_t pcbs_pmax_protocol_err : 1; + uint64_t pcbs_global_actual_pstate_protocol_err : 1; + uint64_t pcbs_pmax_sync_interrupt_timeout_err : 1; + uint64_t pcbs_global_actual_sync_interrupt_timeout_err : 1; + uint64_t pcbs_pstate_interrupt_timeout_err : 1; + uint64_t pcbs_idle_interrupt_timeout_err : 1; + uint64_t pcbs_vds_lookup_err : 1; + uint64_t pcbs_pfet_strength_overflow_err : 1; + uint64_t pcbs_lpst_read_uncorr_err : 1; + uint64_t pcbs_lpst_read_corr_err : 1; + uint64_t pcbs_read_lpst_in_pstate_mode_err : 1; + uint64_t pcbs_core_rs_bypass_confusion_err : 1; + uint64_t pcbs_eco_rs_bypass_confusion_err : 1; + uint64_t pcbs_freq_overflow_in_pstate_mode_err : 1; + uint64_t pcbs_write_pmgp0_in_invalid_state_err : 1; + uint64_t pcbs_write_fsm_goto_reg_in_invalid_state_err : 1; + uint64_t pcbs_winkle_exit_send_int_powup_assist_err : 1; + uint64_t pcbs_winkle_exit_send_int_assist_err : 1; + uint64_t pcbs_spare8_err : 1; + uint64_t pcbs_wait_dpll_lock_err : 1; + uint64_t pcbs_winkle_exit_notify_pmc_err : 1; + uint64_t pcbs_winkle_entry_send_int_assist_err : 1; + uint64_t pcbs_winkle_entry_notify_pmc_err : 1; + uint64_t pcbs_sleep_exit_invoke_pore_err : 1; + uint64_t pcbs_sleep_entry_notify_pmc_err : 1; + uint64_t pcbs_sleep_entry_notify_pmc_assist_hang_err : 1; + uint64_t pcbs_sleep_entry_notify_pmc_hang_err : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmerr_reg_t; + + + +typedef union pcbs_pmerrmask_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pcbs_sleep_entry_notify_pmc_hang_err_mask : 1; + uint64_t pcbs_sleep_entry_notify_pmc_assist_hang_err_mask : 1; + uint64_t pcbs_sleep_entry_notify_pmc_err_mask : 1; + uint64_t pcbs_sleep_exit_invoke_pore_err_mask : 1; + uint64_t pcbs_winkle_entry_notify_pmc_err_mask : 1; + uint64_t pcbs_winkle_entry_send_int_assist_err_mask : 1; + uint64_t pcbs_winkle_exit_notify_pmc_err_mask : 1; + uint64_t pcbs_wait_dpll_lock_err_mask : 1; + uint64_t pcbs_spare8_err_mask : 1; + uint64_t pcbs_winkle_exit_send_int_assist_err_mask : 1; + uint64_t pcbs_winkle_exit_send_int_powup_assist_err_mask : 1; + uint64_t pcbs_write_fsm_goto_reg_in_invalid_state_err_mask : 1; + uint64_t pcbs_write_pmgp0_in_invalid_state_err_mask : 1; + uint64_t pcbs_freq_overflow_in_pstate_mode_err_mask : 1; + uint64_t pcbs_eco_rs_bypass_confusion_err_mask : 1; + uint64_t pcbs_core_rs_bypass_confusion_err_mask : 1; + uint64_t pcbs_read_lpst_in_pstate_mode_err_mask : 1; + uint64_t pcbs_lpst_read_corr_err_mask : 1; + uint64_t pcbs_lpst_read_uncorr_err_mask : 1; + uint64_t pcbs_pfet_strength_overflow_err_mask : 1; + uint64_t pcbs_vds_lookup_err_mask : 1; + uint64_t pcbs_idle_interrupt_timeout_err_mask : 1; + uint64_t pcbs_pstate_interrupt_timeout_err_mask : 1; + uint64_t pcbs_global_actual_sync_interrupt_timeout_err_mask : 1; + uint64_t pcbs_pmax_sync_interrupt_timeout_err_mask : 1; + uint64_t pcbs_global_actual_pstate_protocol_err_mask : 1; + uint64_t pcbs_pmax_protocol_err_mask : 1; + uint64_t pcbs_ivrm_gross_or_fine_err_mask : 1; + uint64_t pcbs_ivrm_range_err_mask : 1; + uint64_t pcbs_dpll_cpm_fmin_err_mask : 1; + uint64_t pcbs_dpll_dco_full_err_mask : 1; + uint64_t pcbs_dpll_dco_empty_err_mask : 1; + uint64_t pcbs_dpll_int_err_mask : 1; + uint64_t pcbs_fmin_and_not_cpmbit_err_mask : 1; + uint64_t pcbs_dpll_faster_than_fmax_plus_delta1_err_mask : 1; + uint64_t pcbs_dpll_slower_than_fmin_minus_delta2_err_mask : 1; + uint64_t pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err_mask : 1; + uint64_t pcbs_reslkc_band_boundary_chg_in_invalid_state_err_mask : 1; + uint64_t pcbs_occ_heartbeat_loss_err_mask : 1; + uint64_t pcbs_spare39_err_mask : 1; + uint64_t pcbs_spare40_err_mask : 1; + uint64_t pcbs_spare41_err_mask : 1; + uint64_t pcbs_spare42_err_mask : 1; + uint64_t _reserved0 : 21; +#else + uint64_t _reserved0 : 21; + uint64_t pcbs_spare42_err_mask : 1; + uint64_t pcbs_spare41_err_mask : 1; + uint64_t pcbs_spare40_err_mask : 1; + uint64_t pcbs_spare39_err_mask : 1; + uint64_t pcbs_occ_heartbeat_loss_err_mask : 1; + uint64_t pcbs_reslkc_band_boundary_chg_in_invalid_state_err_mask : 1; + uint64_t pcbs_resclk_csb_instr_vector_chg_in_invalid_state_err_mask : 1; + uint64_t pcbs_dpll_slower_than_fmin_minus_delta2_err_mask : 1; + uint64_t pcbs_dpll_faster_than_fmax_plus_delta1_err_mask : 1; + uint64_t pcbs_fmin_and_not_cpmbit_err_mask : 1; + uint64_t pcbs_dpll_int_err_mask : 1; + uint64_t pcbs_dpll_dco_empty_err_mask : 1; + uint64_t pcbs_dpll_dco_full_err_mask : 1; + uint64_t pcbs_dpll_cpm_fmin_err_mask : 1; + uint64_t pcbs_ivrm_range_err_mask : 1; + uint64_t pcbs_ivrm_gross_or_fine_err_mask : 1; + uint64_t pcbs_pmax_protocol_err_mask : 1; + uint64_t pcbs_global_actual_pstate_protocol_err_mask : 1; + uint64_t pcbs_pmax_sync_interrupt_timeout_err_mask : 1; + uint64_t pcbs_global_actual_sync_interrupt_timeout_err_mask : 1; + uint64_t pcbs_pstate_interrupt_timeout_err_mask : 1; + uint64_t pcbs_idle_interrupt_timeout_err_mask : 1; + uint64_t pcbs_vds_lookup_err_mask : 1; + uint64_t pcbs_pfet_strength_overflow_err_mask : 1; + uint64_t pcbs_lpst_read_uncorr_err_mask : 1; + uint64_t pcbs_lpst_read_corr_err_mask : 1; + uint64_t pcbs_read_lpst_in_pstate_mode_err_mask : 1; + uint64_t pcbs_core_rs_bypass_confusion_err_mask : 1; + uint64_t pcbs_eco_rs_bypass_confusion_err_mask : 1; + uint64_t pcbs_freq_overflow_in_pstate_mode_err_mask : 1; + uint64_t pcbs_write_pmgp0_in_invalid_state_err_mask : 1; + uint64_t pcbs_write_fsm_goto_reg_in_invalid_state_err_mask : 1; + uint64_t pcbs_winkle_exit_send_int_powup_assist_err_mask : 1; + uint64_t pcbs_winkle_exit_send_int_assist_err_mask : 1; + uint64_t pcbs_spare8_err_mask : 1; + uint64_t pcbs_wait_dpll_lock_err_mask : 1; + uint64_t pcbs_winkle_exit_notify_pmc_err_mask : 1; + uint64_t pcbs_winkle_entry_send_int_assist_err_mask : 1; + uint64_t pcbs_winkle_entry_notify_pmc_err_mask : 1; + uint64_t pcbs_sleep_exit_invoke_pore_err_mask : 1; + uint64_t pcbs_sleep_entry_notify_pmc_err_mask : 1; + uint64_t pcbs_sleep_entry_notify_pmc_assist_hang_err_mask : 1; + uint64_t pcbs_sleep_entry_notify_pmc_hang_err_mask : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmerrmask_reg_t; + + + +typedef union pcbs_pmspcwkupfsp_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t fsp_special_wakeup : 1; + uint64_t _reserved0 : 63; +#else + uint64_t _reserved0 : 63; + uint64_t fsp_special_wakeup : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmspcwkupfsp_reg_t; + + + +typedef union pcbs_pmspcwkupocc_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t occ_special_wakeup : 1; + uint64_t _reserved0 : 63; +#else + uint64_t _reserved0 : 63; + uint64_t occ_special_wakeup : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmspcwkupocc_reg_t; + + + +typedef union pcbs_pmspcwkupphyp_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t phyp_special_wakeup : 1; + uint64_t _reserved0 : 63; +#else + uint64_t _reserved0 : 63; + uint64_t phyp_special_wakeup : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmspcwkupphyp_reg_t; + + + +typedef union pcbs_pmstatehistphyp_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t phyp_pm_state : 3; + uint64_t phyp_past_core_instruct_stop : 1; + uint64_t phyp_past_core_clk_stop : 1; + uint64_t phyp_past_core_pwr_off : 1; + uint64_t phyp_past_eco_clk_stop : 1; + uint64_t phyp_past_eco_pwr_off : 1; + uint64_t _reserved0 : 56; +#else + uint64_t _reserved0 : 56; + uint64_t phyp_past_eco_pwr_off : 1; + uint64_t phyp_past_eco_clk_stop : 1; + uint64_t phyp_past_core_pwr_off : 1; + uint64_t phyp_past_core_clk_stop : 1; + uint64_t phyp_past_core_instruct_stop : 1; + uint64_t phyp_pm_state : 3; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmstatehistphyp_reg_t; + + + +typedef union pcbs_pmstatehistfsp_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t fsp_pm_state : 3; + uint64_t fsp_past_core_instruct_stop : 1; + uint64_t fsp_past_core_clk_stop : 1; + uint64_t fsp_past_core_pwr_off : 1; + uint64_t fsp_past_eco_clk_stop : 1; + uint64_t fsp_past_eco_pwr_off : 1; + uint64_t _reserved0 : 56; +#else + uint64_t _reserved0 : 56; + uint64_t fsp_past_eco_pwr_off : 1; + uint64_t fsp_past_eco_clk_stop : 1; + uint64_t fsp_past_core_pwr_off : 1; + uint64_t fsp_past_core_clk_stop : 1; + uint64_t fsp_past_core_instruct_stop : 1; + uint64_t fsp_pm_state : 3; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmstatehistfsp_reg_t; + + + +typedef union pcbs_pmstatehistocc_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t occ_pm_state : 3; + uint64_t occ_past_core_instruct_stop : 1; + uint64_t occ_past_core_clk_stop : 1; + uint64_t occ_past_core_pwr_off : 1; + uint64_t occ_past_eco_clk_stop : 1; + uint64_t occ_past_eco_pwr_off : 1; + uint64_t _reserved0 : 56; +#else + uint64_t _reserved0 : 56; + uint64_t occ_past_eco_pwr_off : 1; + uint64_t occ_past_eco_clk_stop : 1; + uint64_t occ_past_core_pwr_off : 1; + uint64_t occ_past_core_clk_stop : 1; + uint64_t occ_past_core_instruct_stop : 1; + uint64_t occ_pm_state : 3; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmstatehistocc_reg_t; + + + +typedef union pcbs_pmstatehistperf_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t perf_pm_state : 3; + uint64_t perf_past_core_instruct_stop : 1; + uint64_t perf_past_core_clk_stop : 1; + uint64_t perf_past_core_pwr_off : 1; + uint64_t perf_past_eco_clk_stop : 1; + uint64_t perf_past_eco_pwr_off : 1; + uint64_t _reserved0 : 56; +#else + uint64_t _reserved0 : 56; + uint64_t perf_past_eco_pwr_off : 1; + uint64_t perf_past_eco_clk_stop : 1; + uint64_t perf_past_core_pwr_off : 1; + uint64_t perf_past_core_clk_stop : 1; + uint64_t perf_past_core_instruct_stop : 1; + uint64_t perf_pm_state : 3; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmstatehistperf_reg_t; + + + +typedef union pcbs_idlefsmgotocmd_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t idle_fsm_goto_cmd : 2; + uint64_t babystp_trigger_sleep_entry : 1; + uint64_t babystp_trigger_winkle_entry : 1; + uint64_t babystp_trigger_wakeup : 1; + uint64_t _reserved0 : 59; +#else + uint64_t _reserved0 : 59; + uint64_t babystp_trigger_wakeup : 1; + uint64_t babystp_trigger_winkle_entry : 1; + uint64_t babystp_trigger_sleep_entry : 1; + uint64_t idle_fsm_goto_cmd : 2; +#endif // _BIG_ENDIAN + } fields; +} pcbs_idlefsmgotocmd_reg_t; + + + +typedef union pcbs_corepfpudly_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t core_powup_dly0 : 4; + uint64_t core_powup_dly1 : 4; + uint64_t core_power_up_delay_sel : 12; + uint64_t _reserved0 : 44; +#else + uint64_t _reserved0 : 44; + uint64_t core_power_up_delay_sel : 12; + uint64_t core_powup_dly1 : 4; + uint64_t core_powup_dly0 : 4; +#endif // _BIG_ENDIAN + } fields; +} pcbs_corepfpudly_reg_t; + + + +typedef union pcbs_corepfpddly_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t core_powdn_dly0 : 4; + uint64_t core_powdn_dly1 : 4; + uint64_t core_power_dn_delay_sel : 12; + uint64_t _reserved0 : 44; +#else + uint64_t _reserved0 : 44; + uint64_t core_power_dn_delay_sel : 12; + uint64_t core_powdn_dly1 : 4; + uint64_t core_powdn_dly0 : 4; +#endif // _BIG_ENDIAN + } fields; +} pcbs_corepfpddly_reg_t; + + + +typedef union pcbs_corepfvret_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t core_vret_sel : 4; + uint64_t core_voff_sel : 4; + uint64_t _reserved0 : 56; +#else + uint64_t _reserved0 : 56; + uint64_t core_voff_sel : 4; + uint64_t core_vret_sel : 4; +#endif // _BIG_ENDIAN + } fields; +} pcbs_corepfvret_reg_t; + + + +typedef union pcbs_ecopfpudly_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t eco_powup_dly0 : 4; + uint64_t eco_powup_dly1 : 4; + uint64_t eco_power_up_delay_sel : 12; + uint64_t _reserved0 : 44; +#else + uint64_t _reserved0 : 44; + uint64_t eco_power_up_delay_sel : 12; + uint64_t eco_powup_dly1 : 4; + uint64_t eco_powup_dly0 : 4; +#endif // _BIG_ENDIAN + } fields; +} pcbs_ecopfpudly_reg_t; + + + +typedef union pcbs_ecopfpddly_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t eco_powdn_dly0 : 4; + uint64_t eco_powdn_dly1 : 4; + uint64_t eco_power_dn_delay_sel : 12; + uint64_t _reserved0 : 44; +#else + uint64_t _reserved0 : 44; + uint64_t eco_power_dn_delay_sel : 12; + uint64_t eco_powdn_dly1 : 4; + uint64_t eco_powdn_dly0 : 4; +#endif // _BIG_ENDIAN + } fields; +} pcbs_ecopfpddly_reg_t; + + + +typedef union pcbs_ecopfvret_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t eco_vret_sel : 4; + uint64_t eco_voff_sel : 4; + uint64_t _reserved0 : 56; +#else + uint64_t _reserved0 : 56; + uint64_t eco_voff_sel : 4; + uint64_t eco_vret_sel : 4; +#endif // _BIG_ENDIAN + } fields; +} pcbs_ecopfvret_reg_t; + + + +typedef union pcbs_freq_ctrl_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t dpll_fmin : 9; + uint64_t dpll_fmax : 9; + uint64_t dpll_fmax_bias : 4; + uint64_t frequ_at_pstate0 : 9; + uint64_t _reserved0 : 33; +#else + uint64_t _reserved0 : 33; + uint64_t frequ_at_pstate0 : 9; + uint64_t dpll_fmax_bias : 4; + uint64_t dpll_fmax : 9; + uint64_t dpll_fmin : 9; +#endif // _BIG_ENDIAN + } fields; +} pcbs_freq_ctrl_reg_t; + + + +typedef union pcbs_dpll_cpm_parm_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t lf_slewratexpi : 8; + uint64_t lf_use_cpmxpi : 1; + uint64_t ff_use_cpmxpi : 1; + uint64_t cpm_filter_enable : 1; + uint64_t ff_bypassxpi : 1; + uint64_t dco_override : 1; + uint64_t dco_incr : 1; + uint64_t dco_decr : 1; + uint64_t dpll_lock_timer_replacement_value : 9; + uint64_t pre_vret_pstate : 8; + uint64_t override_pcbs_dpll_synchronizer : 1; + uint64_t dpll_char_delta1 : 4; + uint64_t dpll_char_delta2 : 4; + uint64_t _reserved0 : 23; +#else + uint64_t _reserved0 : 23; + uint64_t dpll_char_delta2 : 4; + uint64_t dpll_char_delta1 : 4; + uint64_t override_pcbs_dpll_synchronizer : 1; + uint64_t pre_vret_pstate : 8; + uint64_t dpll_lock_timer_replacement_value : 9; + uint64_t dco_decr : 1; + uint64_t dco_incr : 1; + uint64_t dco_override : 1; + uint64_t ff_bypassxpi : 1; + uint64_t cpm_filter_enable : 1; + uint64_t ff_use_cpmxpi : 1; + uint64_t lf_use_cpmxpi : 1; + uint64_t lf_slewratexpi : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_dpll_cpm_parm_reg_t; + + + +typedef union pcbs_power_management_status_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + int64_t global_pstate_actual : 8; + int64_t local_pstate_actual : 8; + int64_t pv_min : 8; + int64_t pvf_max : 8; + uint64_t spr_em_disabled : 1; + uint64_t psafe_mode_active : 1; + uint64_t ivrm_safe_mode_active : 1; + uint64_t ivrm_enable : 1; + uint64_t all_fsms_in_safe_state : 1; + uint64_t pmsr_spares : 4; + uint64_t _reserved0 : 23; +#else + uint64_t _reserved0 : 23; + uint64_t pmsr_spares : 4; + uint64_t all_fsms_in_safe_state : 1; + uint64_t ivrm_enable : 1; + uint64_t ivrm_safe_mode_active : 1; + uint64_t psafe_mode_active : 1; + uint64_t spr_em_disabled : 1; + int64_t pvf_max : 8; + int64_t pv_min : 8; + int64_t local_pstate_actual : 8; + int64_t global_pstate_actual : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_power_management_status_reg_t; + + + +typedef union pcbs_ivrm_control_status_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t ivrm_fsm_enable : 1; + uint64_t use_ivrm_for_vret : 1; + uint64_t binsearch_cal_ena : 1; + uint64_t pvref_en : 1; + uint64_t ivrm_core_vdd_bypass_b : 1; + uint64_t ivrm_core_vdd_poweron : 1; + uint64_t ivrm_core_vcs_bypass_b : 1; + uint64_t ivrm_core_vcs_poweron : 1; + uint64_t ivrm_eco_vdd_bypass_b : 1; + uint64_t ivrm_eco_vdd_poweron : 1; + uint64_t ivrm_eco_vcs_bypass_b : 1; + uint64_t ivrm_eco_vcs_poweron : 1; + uint64_t ivrm_vret_vdd : 7; + uint64_t ivrm_vret_vcs : 7; + uint64_t ivrm_vret_core_vdd_pfet_strength : 5; + uint64_t ivrm_vret_core_vcs_pfet_strength : 5; + uint64_t ivrm_vret_eco_vdd_pfet_strength : 5; + uint64_t ivrm_vret_eco_vcs_pfet_strength : 5; + uint64_t pvref_fail : 1; + uint64_t ivrm_pref_error_gross : 1; + uint64_t ivrm_pref_error_fine : 1; + uint64_t ivrm_core_vdd_range_hi : 1; + uint64_t ivrm_core_vdd_range_lo : 1; + uint64_t ivrm_eco_vdd_range_hi : 1; + uint64_t ivrm_eco_vdd_range_lo : 1; + uint64_t ivrm_core_vcs_range_hi : 1; + uint64_t ivrm_core_vcs_range_lo : 1; + uint64_t ivrm_eco_vcs_range_hi : 1; + uint64_t ivrm_eco_vcs_range_lo : 1; + uint64_t binsearch_cal_done : 1; + uint64_t ivrm_core_vdd_pfet_low_vout : 1; + uint64_t ivrm_core_vcs_pfet_low_vout : 1; + uint64_t ivrm_eco_vdd_pfet_low_vout : 1; + uint64_t ivrm_eco_vcs_pfet_low_vout : 1; + uint64_t ivrm_power_down_disable : 1; + uint64_t _reserved0 : 1; +#else + uint64_t _reserved0 : 1; + uint64_t ivrm_power_down_disable : 1; + uint64_t ivrm_eco_vcs_pfet_low_vout : 1; + uint64_t ivrm_eco_vdd_pfet_low_vout : 1; + uint64_t ivrm_core_vcs_pfet_low_vout : 1; + uint64_t ivrm_core_vdd_pfet_low_vout : 1; + uint64_t binsearch_cal_done : 1; + uint64_t ivrm_eco_vcs_range_lo : 1; + uint64_t ivrm_eco_vcs_range_hi : 1; + uint64_t ivrm_core_vcs_range_lo : 1; + uint64_t ivrm_core_vcs_range_hi : 1; + uint64_t ivrm_eco_vdd_range_lo : 1; + uint64_t ivrm_eco_vdd_range_hi : 1; + uint64_t ivrm_core_vdd_range_lo : 1; + uint64_t ivrm_core_vdd_range_hi : 1; + uint64_t ivrm_pref_error_fine : 1; + uint64_t ivrm_pref_error_gross : 1; + uint64_t pvref_fail : 1; + uint64_t ivrm_vret_eco_vcs_pfet_strength : 5; + uint64_t ivrm_vret_eco_vdd_pfet_strength : 5; + uint64_t ivrm_vret_core_vcs_pfet_strength : 5; + uint64_t ivrm_vret_core_vdd_pfet_strength : 5; + uint64_t ivrm_vret_vcs : 7; + uint64_t ivrm_vret_vdd : 7; + uint64_t ivrm_eco_vcs_poweron : 1; + uint64_t ivrm_eco_vcs_bypass_b : 1; + uint64_t ivrm_eco_vdd_poweron : 1; + uint64_t ivrm_eco_vdd_bypass_b : 1; + uint64_t ivrm_core_vcs_poweron : 1; + uint64_t ivrm_core_vcs_bypass_b : 1; + uint64_t ivrm_core_vdd_poweron : 1; + uint64_t ivrm_core_vdd_bypass_b : 1; + uint64_t pvref_en : 1; + uint64_t binsearch_cal_ena : 1; + uint64_t use_ivrm_for_vret : 1; + uint64_t ivrm_fsm_enable : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_ivrm_control_status_reg_t; + + + +typedef union pcbs_ivrm_value_setting_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t ivrm_core_vdd_ivid : 8; + uint64_t ivrm_core_vcs_ivid : 8; + uint64_t ivrm_eco_vdd_ivid : 8; + uint64_t ivrm_eco_vcs_ivid : 8; + uint64_t ivrm_core_vdd_pfet_strength : 5; + uint64_t ivrm_core_vcs_pfet_strength : 5; + uint64_t ivrm_eco_vdd_pfet_strength : 5; + uint64_t ivrm_eco_vcs_pfet_strength : 5; + uint64_t ivrm_vdd_core_pfetstr_valid : 1; + uint64_t ivrm_vcs_core_pfetstr_valid : 1; + uint64_t ivrm_vdd_eco_pfetstr_valid : 1; + uint64_t ivrm_vcs_eco_pfetstr_valid : 1; + uint64_t core_vdd_vpump_en : 1; + uint64_t core_vcs_vpump_en : 1; + uint64_t eco_vdd_vpump_en : 1; + uint64_t eco_vcs_vpump_en : 1; + uint64_t _reserved0 : 4; +#else + uint64_t _reserved0 : 4; + uint64_t eco_vcs_vpump_en : 1; + uint64_t eco_vdd_vpump_en : 1; + uint64_t core_vcs_vpump_en : 1; + uint64_t core_vdd_vpump_en : 1; + uint64_t ivrm_vcs_eco_pfetstr_valid : 1; + uint64_t ivrm_vdd_eco_pfetstr_valid : 1; + uint64_t ivrm_vcs_core_pfetstr_valid : 1; + uint64_t ivrm_vdd_core_pfetstr_valid : 1; + uint64_t ivrm_eco_vcs_pfet_strength : 5; + uint64_t ivrm_eco_vdd_pfet_strength : 5; + uint64_t ivrm_core_vcs_pfet_strength : 5; + uint64_t ivrm_core_vdd_pfet_strength : 5; + uint64_t ivrm_eco_vcs_ivid : 8; + uint64_t ivrm_eco_vdd_ivid : 8; + uint64_t ivrm_core_vcs_ivid : 8; + uint64_t ivrm_core_vdd_ivid : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_ivrm_value_setting_reg_t; + + + +typedef union pcbs_pcbspm_mode_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t enable_pstate_mode : 1; + uint64_t global_pstate_change_for_idle_state_enabled : 1; + uint64_t enable_global_pstate_req : 1; + uint64_t enable_winkle_with_cpm_mode : 1; + uint64_t enable_clipping_of_global_pstate_req : 1; + uint64_t chksw_hw214553 : 1; + uint64_t enable_pmc_pmax_sync_notification : 1; + uint64_t dpll_lock_replacement_timer_mode_en : 1; + uint64_t dpll_freqout_mode_en : 1; + uint64_t dpll_flock_mode_en : 1; + uint64_t enable_sense_delay_characterization : 1; + uint64_t sense_delay_timer_val : 7; + uint64_t cpm_fmin_clip_error_sel : 2; + uint64_t dbg_trace_sel : 4; + uint64_t trace_data_sel : 2; + uint64_t tp_cplt_ivrm_vpp_tune : 4; + uint64_t _reserved0 : 34; +#else + uint64_t _reserved0 : 34; + uint64_t tp_cplt_ivrm_vpp_tune : 4; + uint64_t trace_data_sel : 2; + uint64_t dbg_trace_sel : 4; + uint64_t cpm_fmin_clip_error_sel : 2; + uint64_t sense_delay_timer_val : 7; + uint64_t enable_sense_delay_characterization : 1; + uint64_t dpll_flock_mode_en : 1; + uint64_t dpll_freqout_mode_en : 1; + uint64_t dpll_lock_replacement_timer_mode_en : 1; + uint64_t enable_pmc_pmax_sync_notification : 1; + uint64_t chksw_hw214553 : 1; + uint64_t enable_clipping_of_global_pstate_req : 1; + uint64_t enable_winkle_with_cpm_mode : 1; + uint64_t enable_global_pstate_req : 1; + uint64_t global_pstate_change_for_idle_state_enabled : 1; + uint64_t enable_pstate_mode : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pcbspm_mode_reg_t; + +#endif // __ASSEMBLER__ +#define PCBS_PCBSPM_MODE_REG_ENABLE_PSTATE_MODE SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define PCBS_PCBSPM_MODE_REG_GLOBAL_PSTATE_CHANGE_FOR_IDLE_STATE_ENABLED SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#define PCBS_PCBSPM_MODE_REG_ENABLE_GLOBAL_PSTATE_REQ SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) +#define PCBS_PCBSPM_MODE_REG_ENABLE_WINKLE_WITH_CPM_MODE SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) +#define PCBS_PCBSPM_MODE_REG_ENABLE_CLIPPING_OF_GLOBAL_PSTATE_REQ SIXTYFOUR_BIT_CONSTANT(0x0800000000000000) +#define PCBS_PCBSPM_MODE_REG_CHKSW_HW214553 SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) +#define PCBS_PCBSPM_MODE_REG_ENABLE_PMC_PMAX_SYNC_NOTIFICATION SIXTYFOUR_BIT_CONSTANT(0x0200000000000000) +#define PCBS_PCBSPM_MODE_REG_DPLL_LOCK_REPLACEMENT_TIMER_MODE_EN SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) +#define PCBS_PCBSPM_MODE_REG_DPLL_FREQOUT_MODE_EN SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) +#define PCBS_PCBSPM_MODE_REG_DPLL_FLOCK_MODE_EN SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) +#define PCBS_PCBSPM_MODE_REG_ENABLE_SENSE_DELAY_CHARACTERIZATION SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) +#define PCBS_PCBSPM_MODE_REG_SENSE_DELAY_TIMER_VAL_MASK SIXTYFOUR_BIT_CONSTANT(0x001fc00000000000) +#define PCBS_PCBSPM_MODE_REG_CPM_FMIN_CLIP_ERROR_SEL_MASK SIXTYFOUR_BIT_CONSTANT(0x0000300000000000) +#define PCBS_PCBSPM_MODE_REG_DBG_TRACE_SEL_MASK SIXTYFOUR_BIT_CONSTANT(0x00000f0000000000) +#define PCBS_PCBSPM_MODE_REG_TRACE_DATA_SEL_MASK SIXTYFOUR_BIT_CONSTANT(0x000000c000000000) +#define PCBS_PCBSPM_MODE_REG_TP_CPLT_IVRM_VPP_TUNE_MASK SIXTYFOUR_BIT_CONSTANT(0x0000003c00000000) +#ifndef __ASSEMBLER__ + + +typedef union pcbs_ivrm_pfetstr_sense_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t ivrm_core_vdd_pfetstr_sns : 5; + uint64_t ivrm_core_vcs_pfetstr_sns : 5; + uint64_t ivrm_eco_vdd_pfetstr_sns : 5; + uint64_t ivrm_eco_vcs_pfetstr_sns : 5; + uint64_t ivrm_vdd_core_pfetstr_valid_sns : 1; + uint64_t ivrm_vcs_core_pfetstr_valid_sns : 1; + uint64_t ivrm_vdd_eco_pfetstr_valid_sns : 1; + uint64_t ivrm_vcs_eco_pfetstr_valid_sns : 1; + uint64_t core_vdd_bypass_b_sense : 1; + uint64_t core_vcs_bypass_b_sense : 1; + uint64_t eco_vdd_bypass_b_sense : 1; + uint64_t eco_vcs_bypass_b_sense : 1; + uint64_t core_vdd_poweron_sense : 1; + uint64_t core_vcs_poweron_sense : 1; + uint64_t eco_vdd_poweron_sense : 1; + uint64_t eco_vcs_poweron_sense : 1; + uint64_t core_vdd_vpump_en_sense : 1; + uint64_t core_vcs_vpump_en_sense : 1; + uint64_t eco_vdd_vpump_en_sense : 1; + uint64_t eco_vcs_vpump_en_sense : 1; + uint64_t core_vdd_pfet_low_vout_sns : 1; + uint64_t core_vcs_pfet_low_vout_sns : 1; + uint64_t eco_vdd_pfet_low_vout_sns : 1; + uint64_t eco_vcs_pfet_low_vout_sns : 1; + uint64_t _reserved0 : 24; +#else + uint64_t _reserved0 : 24; + uint64_t eco_vcs_pfet_low_vout_sns : 1; + uint64_t eco_vdd_pfet_low_vout_sns : 1; + uint64_t core_vcs_pfet_low_vout_sns : 1; + uint64_t core_vdd_pfet_low_vout_sns : 1; + uint64_t eco_vcs_vpump_en_sense : 1; + uint64_t eco_vdd_vpump_en_sense : 1; + uint64_t core_vcs_vpump_en_sense : 1; + uint64_t core_vdd_vpump_en_sense : 1; + uint64_t eco_vcs_poweron_sense : 1; + uint64_t eco_vdd_poweron_sense : 1; + uint64_t core_vcs_poweron_sense : 1; + uint64_t core_vdd_poweron_sense : 1; + uint64_t eco_vcs_bypass_b_sense : 1; + uint64_t eco_vdd_bypass_b_sense : 1; + uint64_t core_vcs_bypass_b_sense : 1; + uint64_t core_vdd_bypass_b_sense : 1; + uint64_t ivrm_vcs_eco_pfetstr_valid_sns : 1; + uint64_t ivrm_vdd_eco_pfetstr_valid_sns : 1; + uint64_t ivrm_vcs_core_pfetstr_valid_sns : 1; + uint64_t ivrm_vdd_core_pfetstr_valid_sns : 1; + uint64_t ivrm_eco_vcs_pfetstr_sns : 5; + uint64_t ivrm_eco_vdd_pfetstr_sns : 5; + uint64_t ivrm_core_vcs_pfetstr_sns : 5; + uint64_t ivrm_core_vdd_pfetstr_sns : 5; +#endif // _BIG_ENDIAN + } fields; +} pcbs_ivrm_pfetstr_sense_reg_t; + + + +typedef union pcbs_power_management_idle_control_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + int64_t nap_pstate_req : 8; + uint64_t nap_pstate_en : 1; + uint64_t nap_global_en : 1; + uint64_t nap_latency : 2; + uint64_t reserved_ppmicr_0 : 4; + int64_t sleep_pstate_req : 8; + uint64_t sleep_pstate_en : 1; + uint64_t sleep_global_en : 1; + uint64_t sleep_latency : 2; + uint64_t reserved_ppmicr_1 : 4; + int64_t winkle_pstate_req : 8; + uint64_t winkle_pstate_en : 1; + uint64_t winkle_global_en : 1; + uint64_t winkle_latency : 2; + uint64_t reserved_ppmicr_2 : 4; + uint64_t _reserved0 : 16; +#else + uint64_t _reserved0 : 16; + uint64_t reserved_ppmicr_2 : 4; + uint64_t winkle_latency : 2; + uint64_t winkle_global_en : 1; + uint64_t winkle_pstate_en : 1; + int64_t winkle_pstate_req : 8; + uint64_t reserved_ppmicr_1 : 4; + uint64_t sleep_latency : 2; + uint64_t sleep_global_en : 1; + uint64_t sleep_pstate_en : 1; + int64_t sleep_pstate_req : 8; + uint64_t reserved_ppmicr_0 : 4; + uint64_t nap_latency : 2; + uint64_t nap_global_en : 1; + uint64_t nap_pstate_en : 1; + int64_t nap_pstate_req : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_power_management_idle_control_reg_t; + + + +typedef union pcbs_power_management_control_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + int64_t global_pstate_req : 8; + int64_t local_pstate_req : 8; + uint64_t auto_override0_pstate_limit_en : 1; + uint64_t auto_override1_pstate_limit_en : 1; + uint64_t reserved_ppmcr : 6; + int64_t auto_override_pstate0 : 8; + int64_t auto_override_pstate1 : 8; + uint64_t _reserved0 : 24; +#else + uint64_t _reserved0 : 24; + int64_t auto_override_pstate1 : 8; + int64_t auto_override_pstate0 : 8; + uint64_t reserved_ppmcr : 6; + uint64_t auto_override1_pstate_limit_en : 1; + uint64_t auto_override0_pstate_limit_en : 1; + int64_t local_pstate_req : 8; + int64_t global_pstate_req : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_power_management_control_reg_t; + + + +typedef union pcbs_pmc_vf_ctrl_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + int64_t pglobal_actual : 8; + uint64_t maxregvcs : 8; + uint64_t maxregvdd : 8; + uint64_t evidvcs_eff : 8; + uint64_t evidvdd_eff : 8; + uint64_t _reserved0 : 24; +#else + uint64_t _reserved0 : 24; + uint64_t evidvdd_eff : 8; + uint64_t evidvcs_eff : 8; + uint64_t maxregvdd : 8; + uint64_t maxregvcs : 8; + int64_t pglobal_actual : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pmc_vf_ctrl_reg_t; + + + +typedef union pcbs_undervolting_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + int64_t puv_min : 8; + int64_t puv_max : 8; + uint64_t kuv : 6; + uint64_t _reserved0 : 42; +#else + uint64_t _reserved0 : 42; + uint64_t kuv : 6; + int64_t puv_max : 8; + int64_t puv_min : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_undervolting_reg_t; + + + +typedef union pcbs_pstate_index_bound_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t lpsi_min : 8; + uint64_t lpsi_entries_minus_1 : 7; + uint64_t _reserved0 : 49; +#else + uint64_t _reserved0 : 49; + uint64_t lpsi_entries_minus_1 : 7; + uint64_t lpsi_min : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pstate_index_bound_reg_t; + + + +typedef union pcbs_power_management_bounds_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + int64_t pmin_clip : 8; + int64_t pmax_clip : 8; + uint64_t _reserved0 : 48; +#else + uint64_t _reserved0 : 48; + int64_t pmax_clip : 8; + int64_t pmin_clip : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_power_management_bounds_reg_t; + + + +typedef union pcbs_pstate_table_ctrl_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pstate_table_address : 7; + uint64_t _reserved0 : 57; +#else + uint64_t _reserved0 : 57; + uint64_t pstate_table_address : 7; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pstate_table_ctrl_reg_t; + + + +typedef union pcbs_pstate_table_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pstate_data : 64; +#else + uint64_t pstate_data : 64; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pstate_table_reg_t; + + + +typedef union pcbs_pstate_step_target_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + int64_t local_pstate_eff_req : 8; + int64_t local_pstate_target : 8; + int64_t local_core_pstate_step_target : 8; + int64_t local_eco_pstate_step_target : 8; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + int64_t local_eco_pstate_step_target : 8; + int64_t local_core_pstate_step_target : 8; + int64_t local_pstate_target : 8; + int64_t local_pstate_eff_req : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_pstate_step_target_reg_t; + + + +typedef union pcbs_dpll_status_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t dpll_ff_freqout : 15; + uint64_t dpll_frequ_change : 1; + uint64_t dpll_status_spare_bit1 : 1; + uint64_t pmax_sync_pending : 1; + uint64_t ga_ack_pending : 1; + int64_t capped_global_pstate_req : 8; + uint64_t dpll_fmax_and_cpmbit2 : 1; + uint64_t dpll_fmax_and_cpmbit3 : 1; + uint64_t dpll_fmax_and_cpmbit4 : 1; + uint64_t dpll_fmin_and_not_cpmbit2 : 1; + uint64_t dpll_fmin_and_not_cpmbit1 : 1; + uint64_t dpll_fmin_and_not_cpmbit0 : 1; + uint64_t dpll_faster_than_fmax_plus_delta1 : 1; + uint64_t dpll_slower_than_fmin_minus_delta2 : 1; + uint64_t dpll_max_freqout_after_last_read : 14; + uint64_t dpll_min_freqout_after_last_read : 14; + uint64_t _reserved0 : 1; +#else + uint64_t _reserved0 : 1; + uint64_t dpll_min_freqout_after_last_read : 14; + uint64_t dpll_max_freqout_after_last_read : 14; + uint64_t dpll_slower_than_fmin_minus_delta2 : 1; + uint64_t dpll_faster_than_fmax_plus_delta1 : 1; + uint64_t dpll_fmin_and_not_cpmbit0 : 1; + uint64_t dpll_fmin_and_not_cpmbit1 : 1; + uint64_t dpll_fmin_and_not_cpmbit2 : 1; + uint64_t dpll_fmax_and_cpmbit4 : 1; + uint64_t dpll_fmax_and_cpmbit3 : 1; + uint64_t dpll_fmax_and_cpmbit2 : 1; + int64_t capped_global_pstate_req : 8; + uint64_t ga_ack_pending : 1; + uint64_t pmax_sync_pending : 1; + uint64_t dpll_status_spare_bit1 : 1; + uint64_t dpll_frequ_change : 1; + uint64_t dpll_ff_freqout : 15; +#endif // _BIG_ENDIAN + } fields; +} pcbs_dpll_status_reg_t; + + + +typedef union pcbs_ivrm_vid_control_reg0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t ivrm_req_pstate_stepdelay_rising : 8; + uint64_t ivrm_req_pstate_stepdelay_lowering : 8; + uint64_t _reserved0 : 48; +#else + uint64_t _reserved0 : 48; + uint64_t ivrm_req_pstate_stepdelay_lowering : 8; + uint64_t ivrm_req_pstate_stepdelay_rising : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_ivrm_vid_control_reg0_t; + + + +typedef union pcbs_ivrm_vid_control_reg1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t ivrm_stabilize_delay_run : 8; + uint64_t ivrm_stabilize_delay_idle : 8; + uint64_t ivrm_pfstr_prop_delay : 8; + uint64_t ivrm_pfstrvalid_prop_delay : 8; + uint64_t ivrm_vpump_poweron_time : 8; + uint64_t ivrm_bypass_delay : 8; + uint64_t pfet_vpump_enable_delay : 8; + uint64_t ivrm_vid_vout_threshold : 7; + uint64_t _reserved0 : 1; +#else + uint64_t _reserved0 : 1; + uint64_t ivrm_vid_vout_threshold : 7; + uint64_t pfet_vpump_enable_delay : 8; + uint64_t ivrm_bypass_delay : 8; + uint64_t ivrm_vpump_poweron_time : 8; + uint64_t ivrm_pfstrvalid_prop_delay : 8; + uint64_t ivrm_pfstr_prop_delay : 8; + uint64_t ivrm_stabilize_delay_idle : 8; + uint64_t ivrm_stabilize_delay_run : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_ivrm_vid_control_reg1_t; + + + +typedef union pcbs_occ_heartbeat_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t occ_heartbeat_time : 8; + uint64_t occ_heartbeat_enable : 1; + uint64_t occ_heartbeat_reg_addr_offset : 8; + int64_t psafe : 8; + uint64_t _reserved0 : 39; +#else + uint64_t _reserved0 : 39; + int64_t psafe : 8; + uint64_t occ_heartbeat_reg_addr_offset : 8; + uint64_t occ_heartbeat_enable : 1; + uint64_t occ_heartbeat_time : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_occ_heartbeat_reg_t; + + + +typedef union pcbs_resonant_clock_control_reg0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t resclk_dis : 1; + uint64_t resclk_control_mode : 1; + uint64_t resclk_sync_pw : 3; + uint64_t res_sync_delay_cnt : 7; + uint64_t res_csb_str_instr_lo : 15; + uint64_t res_csb_str_instr_hi : 15; + uint64_t _reserved0 : 22; +#else + uint64_t _reserved0 : 22; + uint64_t res_csb_str_instr_hi : 15; + uint64_t res_csb_str_instr_lo : 15; + uint64_t res_sync_delay_cnt : 7; + uint64_t resclk_sync_pw : 3; + uint64_t resclk_control_mode : 1; + uint64_t resclk_dis : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_resonant_clock_control_reg0_t; + + + +typedef union pcbs_resonant_clock_control_reg1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + int64_t full_csb_ps : 8; + int64_t res_low_lower_ps : 8; + int64_t res_low_upper_ps : 8; + int64_t res_high_lower_ps : 8; + int64_t res_high_upper_ps : 8; + uint64_t nonres_csb_value_ti : 4; + uint64_t full_csb_value_ti : 4; + uint64_t resclk_value : 9; + uint64_t resclk_core_sync_value : 1; + uint64_t csb_eco_sync_value : 1; + uint64_t _reserved0 : 5; +#else + uint64_t _reserved0 : 5; + uint64_t csb_eco_sync_value : 1; + uint64_t resclk_core_sync_value : 1; + uint64_t resclk_value : 9; + uint64_t full_csb_value_ti : 4; + uint64_t nonres_csb_value_ti : 4; + int64_t res_high_upper_ps : 8; + int64_t res_high_lower_ps : 8; + int64_t res_low_upper_ps : 8; + int64_t res_low_lower_ps : 8; + int64_t full_csb_ps : 8; +#endif // _BIG_ENDIAN + } fields; +} pcbs_resonant_clock_control_reg1_t; + + + +typedef union pcbs_resonant_clock_status_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t resclk_state : 1; + uint64_t res_hi_induct_en : 1; + uint64_t resclk_inprogress : 1; + uint64_t resclk_full_csb : 1; + uint64_t _reserved0 : 60; +#else + uint64_t _reserved0 : 60; + uint64_t resclk_full_csb : 1; + uint64_t resclk_inprogress : 1; + uint64_t res_hi_induct_en : 1; + uint64_t resclk_state : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_resonant_clock_status_reg_t; + + + +typedef union pcbs_local_pstate_frequency_target_control_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t delay_time : 3; + uint64_t record_transitions : 1; + uint64_t multiplier : 15; + uint64_t enable_lpft_function : 1; + uint64_t _reserved0 : 44; +#else + uint64_t _reserved0 : 44; + uint64_t enable_lpft_function : 1; + uint64_t multiplier : 15; + uint64_t record_transitions : 1; + uint64_t delay_time : 3; +#endif // _BIG_ENDIAN + } fields; +} pcbs_local_pstate_frequency_target_control_reg_t; + + + +typedef union pcbs_local_pstate_frequency_target_status_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t valid : 1; + uint64_t cpm_dpll : 1; + uint64_t ivrm : 1; + uint64_t transition : 1; + uint64_t stable : 1; + uint64_t delta : 24; + uint64_t cumulative : 24; + uint64_t pstate : 8; + uint64_t _reserved0 : 3; +#else + uint64_t _reserved0 : 3; + uint64_t pstate : 8; + uint64_t cumulative : 24; + uint64_t delta : 24; + uint64_t stable : 1; + uint64_t transition : 1; + uint64_t ivrm : 1; + uint64_t cpm_dpll : 1; + uint64_t valid : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_local_pstate_frequency_target_status_reg_t; + + + +typedef union pcbs_fsm_monitor1_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t babystep_main_fsm : 7; + uint64_t babystep_slave_fsm : 5; + uint64_t core_railstepper_main_fsm : 5; + uint64_t eco_railstepper_main_fsm : 5; + uint64_t core_railstepper_sub_fsm : 4; + uint64_t eco_railstepper_sub_fsm : 4; + uint64_t core_railstepper_byp_fsm : 5; + uint64_t eco_railstepper_byp_fsm : 5; + uint64_t ivrm_core_vdd_sequencer_fsm : 6; + uint64_t ivrm_core_vcs_sequencer_fsm : 6; + uint64_t ivrm_eco_vdd_sequencer_fsm : 6; + uint64_t ivrm_eco_vcs_sequencer_fsm : 6; +#else + uint64_t ivrm_eco_vcs_sequencer_fsm : 6; + uint64_t ivrm_eco_vdd_sequencer_fsm : 6; + uint64_t ivrm_core_vcs_sequencer_fsm : 6; + uint64_t ivrm_core_vdd_sequencer_fsm : 6; + uint64_t eco_railstepper_byp_fsm : 5; + uint64_t core_railstepper_byp_fsm : 5; + uint64_t eco_railstepper_sub_fsm : 4; + uint64_t core_railstepper_sub_fsm : 4; + uint64_t eco_railstepper_main_fsm : 5; + uint64_t core_railstepper_main_fsm : 5; + uint64_t babystep_slave_fsm : 5; + uint64_t babystep_main_fsm : 7; +#endif // _BIG_ENDIAN + } fields; +} pcbs_fsm_monitor1_reg_t; + + + +typedef union pcbs_fsm_monitor2_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t resclk_band_fsm : 7; + uint64_t resclk_lowres_fsm : 4; + uint64_t resclk_highres_fsm : 4; + uint64_t resclk_fullcsb_fsm : 4; + uint64_t resclk_update_fsm : 4; + uint64_t idle_transition_fsm : 7; + uint64_t peco_step_target_uv : 8; + uint64_t pcore_step_target_uv : 8; + uint64_t _reserved0 : 18; +#else + uint64_t _reserved0 : 18; + uint64_t pcore_step_target_uv : 8; + uint64_t peco_step_target_uv : 8; + uint64_t idle_transition_fsm : 7; + uint64_t resclk_update_fsm : 4; + uint64_t resclk_fullcsb_fsm : 4; + uint64_t resclk_highres_fsm : 4; + uint64_t resclk_lowres_fsm : 4; + uint64_t resclk_band_fsm : 7; +#endif // _BIG_ENDIAN + } fields; +} pcbs_fsm_monitor2_reg_t; + + + +typedef union pcbs_chksw_unassisted_interrupts { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 1; + uint64_t _reserved0 : 63; +#else + uint64_t _reserved0 : 63; + uint64_t value : 1; +#endif // _BIG_ENDIAN + } fields; +} pcbs_chksw_unassisted_interrupts_t; + + +#endif // __ASSEMBLER__ +#endif // __PCBS_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/pcbs_register_addresses.h b/src/ssx/pgp/registers/pcbs_register_addresses.h new file mode 100755 index 0000000..8c465d1 --- /dev/null +++ b/src/ssx/pgp/registers/pcbs_register_addresses.h @@ -0,0 +1,74 @@ +#ifndef __PCBS_REGISTER_ADDRESSES_H__ +#define __PCBS_REGISTER_ADDRESSES_H__ + +// $Id: pcbs_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pcbs_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file pcbs_register_addresses.h +/// \brief Symbolic addresses for the PCBS unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define PCBS_PIB_BASE 0x100f0100 +#define PCBS_PMGP0_REG 0x100f0100 +#define PCBS_PMGP0_REG_AND 0x100f0101 +#define PCBS_PMGP0_REG_OR 0x100f0102 +#define PCBS_PMGP1_REG 0x100f0103 +#define PCBS_PMGP1_REG_AND 0x100f0104 +#define PCBS_PMGP1_REG_OR 0x100f0105 +#define PCBS_PFVDDCNTLSTAT_REG 0x100f0106 +#define PCBS_PFVCSCNTLSTAT_REG 0x100f010e +#define PCBS_PFSENSE_REG 0x100f0107 +#define PCBS_PMERRSUM_REG 0x100f0108 +#define PCBS_PMERR_REG 0x100f0109 +#define PCBS_PMERRMASK_REG 0x100f010a +#define PCBS_PMSPCWKUPFSP_REG 0x100f010b +#define PCBS_PMSPCWKUPOCC_REG 0x100f010c +#define PCBS_PMSPCWKUPPHYP_REG 0x100f010d +#define PCBS_PMSTATEHISTPHYP_REG 0x100f0110 +#define PCBS_PMSTATEHISTFSP_REG 0x100f0111 +#define PCBS_PMSTATEHISTOCC_REG 0x100f0112 +#define PCBS_PMSTATEHISTPERF_REG 0x100f0113 +#define PCBS_IDLEFSMGOTOCMD_REG 0x100f0114 +#define PCBS_COREPFPUDLY_REG 0x100f012c +#define PCBS_COREPFPDDLY_REG 0x100f012d +#define PCBS_COREPFVRET_REG 0x100f0130 +#define PCBS_ECOPFPUDLY_REG 0x100f014c +#define PCBS_ECOPFPDDLY_REG 0x100f014d +#define PCBS_ECOPFVRET_REG 0x100f0150 +#define PCBS_FREQ_CTRL_REG 0x100f0151 +#define PCBS_DPLL_CPM_PARM_REG 0x100f0152 +#define PCBS_POWER_MANAGEMENT_STATUS_REG 0x100f0153 +#define PCBS_IVRM_CONTROL_STATUS_REG 0x100f0154 +#define PCBS_IVRM_VALUE_SETTING_REG 0x100f0155 +#define PCBS_PCBSPM_MODE_REG 0x100f0156 +#define PCBS_IVRM_PFETSTR_SENSE_REG 0x100f0157 +#define PCBS_POWER_MANAGEMENT_IDLE_CONTROL_REG 0x100f0158 +#define PCBS_POWER_MANAGEMENT_CONTROL_REG 0x100f0159 +#define PCBS_PMC_VF_CTRL_REG 0x100f015a +#define PCBS_UNDERVOLTING_REG 0x100f015b +#define PCBS_PSTATE_INDEX_BOUND_REG 0x100f015c +#define PCBS_POWER_MANAGEMENT_BOUNDS_REG 0x100f015d +#define PCBS_PSTATE_TABLE_CTRL_REG 0x100f015e +#define PCBS_PSTATE_TABLE_REG 0x100f015f +#define PCBS_PSTATE_STEP_TARGET_REG 0x100f0160 +#define PCBS_DPLL_STATUS_REG 0x100f0161 +#define PCBS_IVRM_VID_CONTROL_REG0 0x100f0162 +#define PCBS_IVRM_VID_CONTROL_REG1 0x100f0163 +#define PCBS_OCC_HEARTBEAT_REG 0x100f0164 +#define PCBS_RESONANT_CLOCK_CONTROL_REG0 0x100f0165 +#define PCBS_RESONANT_CLOCK_CONTROL_REG1 0x100f0166 +#define PCBS_RESONANT_CLOCK_STATUS_REG 0x100f0167 +#define PCBS_LOCAL_PSTATE_FREQUENCY_TARGET_CONTROL_REG 0x100f0168 +#define PCBS_LOCAL_PSTATE_FREQUENCY_TARGET_STATUS_REG 0x100f0169 +#define PCBS_FSM_MONITOR1_REG 0x100f0170 +#define PCBS_FSM_MONITOR2_REG 0x100f0171 + +#endif // __PCBS_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/pibmem_firmware_registers.h b/src/ssx/pgp/registers/pibmem_firmware_registers.h new file mode 100644 index 0000000..3b36fc1 --- /dev/null +++ b/src/ssx/pgp/registers/pibmem_firmware_registers.h @@ -0,0 +1,264 @@ +#ifndef __PIBMEM_FIRMWARE_REGISTERS_H__ +#define __PIBMEM_FIRMWARE_REGISTERS_H__ + +// $Id: pibmem_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pibmem_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file pibmem_firmware_registers.h +/// \brief C register structs for the PIBMEM unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union pibmem_data0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} pibmem_data0_t; + + + +typedef union pibmem_control { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t auto_pre_increment : 1; + uint64_t auto_post_decrement : 1; + uint64_t _reserved0 : 62; +#else + uint64_t _reserved0 : 62; + uint64_t auto_post_decrement : 1; + uint64_t auto_pre_increment : 1; +#endif // _BIG_ENDIAN + } fields; +} pibmem_control_t; + + + +typedef union pibmem_address { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved0 : 48; + uint64_t address : 16; +#else + uint64_t address : 16; + uint64_t reserved0 : 48; +#endif // _BIG_ENDIAN + } fields; +} pibmem_address_t; + + + +typedef union pibmem_data { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} pibmem_data_t; + + + +typedef union pibmem_data_inc { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} pibmem_data_inc_t; + + + +typedef union pibmem_data_dec { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} pibmem_data_dec_t; + + + +typedef union pibmem_status { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t addr_invalid : 1; + uint64_t write_invalid : 1; + uint64_t read_invalid : 1; + uint64_t ecc_uncorrected_error : 1; + uint64_t ecc_corrected_error : 1; + uint64_t bad_array_address : 1; + uint64_t reserved6 : 5; + uint64_t fsm_present_state : 7; + uint64_t _reserved0 : 46; +#else + uint64_t _reserved0 : 46; + uint64_t fsm_present_state : 7; + uint64_t reserved6 : 5; + uint64_t bad_array_address : 1; + uint64_t ecc_corrected_error : 1; + uint64_t ecc_uncorrected_error : 1; + uint64_t read_invalid : 1; + uint64_t write_invalid : 1; + uint64_t addr_invalid : 1; +#endif // _BIG_ENDIAN + } fields; +} pibmem_status_t; + + + +typedef union pibmem_reset { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reset_code : 2; + uint64_t _reserved0 : 62; +#else + uint64_t _reserved0 : 62; + uint64_t reset_code : 2; +#endif // _BIG_ENDIAN + } fields; +} pibmem_reset_t; + + + +typedef union pibmem_repair { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 64; +#else + uint64_t value : 64; +#endif // _BIG_ENDIAN + } fields; +} pibmem_repair_t; + + +#endif // __ASSEMBLER__ +#endif // __PIBMEM_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/pibmem_register_addresses.h b/src/ssx/pgp/registers/pibmem_register_addresses.h new file mode 100644 index 0000000..0cffaa2 --- /dev/null +++ b/src/ssx/pgp/registers/pibmem_register_addresses.h @@ -0,0 +1,30 @@ +#ifndef __PIBMEM_REGISTER_ADDRESSES_H__ +#define __PIBMEM_REGISTER_ADDRESSES_H__ + +// $Id: pibmem_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pibmem_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file pibmem_register_addresses.h +/// \brief Symbolic addresses for the PIBMEM unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define PIBMEM_PIB_BASE 0x00080000 +#define PIBMEM_DATA0 0x00080000 +#define PIBMEM_CONTROL 0x00088000 +#define PIBMEM_ADDRESS 0x00088001 +#define PIBMEM_DATA 0x00088002 +#define PIBMEM_DATA_INC 0x00088003 +#define PIBMEM_DATA_DEC 0x00088004 +#define PIBMEM_STATUS 0x00088005 +#define PIBMEM_RESET 0x00088006 +#define PIBMEM_REPAIR 0x00088007 + +#endif // __PIBMEM_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/plb_arbiter_firmware_registers.h b/src/ssx/pgp/registers/plb_arbiter_firmware_registers.h new file mode 100755 index 0000000..583e95d --- /dev/null +++ b/src/ssx/pgp/registers/plb_arbiter_firmware_registers.h @@ -0,0 +1,215 @@ +#ifndef __PLB_ARBITER_FIRMWARE_REGISTERS_H__ +#define __PLB_ARBITER_FIRMWARE_REGISTERS_H__ + +// $Id: plb_arbiter_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/plb_arbiter_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file plb_arbiter_firmware_registers.h +/// \brief C register structs for the PLB_ARBITER unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union plb_prev { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} plb_prev_t; + + + +typedef union plb_pacr { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t ppm : 1; + uint32_t ppo : 3; + uint32_t hbu : 1; + uint32_t rdp : 2; + uint32_t wrp : 1; + uint32_t _reserved0 : 24; +#else + uint32_t _reserved0 : 24; + uint32_t wrp : 1; + uint32_t rdp : 2; + uint32_t hbu : 1; + uint32_t ppo : 3; + uint32_t ppm : 1; +#endif // _BIG_ENDIAN + } fields; +} plb_pacr_t; + + + +typedef union plb_pesr { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t pte0 : 1; + uint32_t rw0 : 1; + uint32_t flk0 : 1; + uint32_t alk0 : 1; + uint32_t pte1 : 1; + uint32_t rw1 : 1; + uint32_t flk1 : 1; + uint32_t alk1 : 1; + uint32_t pte2 : 1; + uint32_t rw2 : 1; + uint32_t flk2 : 1; + uint32_t alk2 : 1; + uint32_t pte3 : 1; + uint32_t rw3 : 1; + uint32_t flk3 : 1; + uint32_t alk3 : 1; + uint32_t pte4 : 1; + uint32_t rw4 : 1; + uint32_t flk4 : 1; + uint32_t alk4 : 1; + uint32_t pte5 : 1; + uint32_t rw5 : 1; + uint32_t flk5 : 1; + uint32_t alk5 : 1; + uint32_t pte6 : 1; + uint32_t rw6 : 1; + uint32_t flk6 : 1; + uint32_t alk6 : 1; + uint32_t pte7 : 1; + uint32_t rw7 : 1; + uint32_t flk7 : 1; + uint32_t alk7 : 1; +#else + uint32_t alk7 : 1; + uint32_t flk7 : 1; + uint32_t rw7 : 1; + uint32_t pte7 : 1; + uint32_t alk6 : 1; + uint32_t flk6 : 1; + uint32_t rw6 : 1; + uint32_t pte6 : 1; + uint32_t alk5 : 1; + uint32_t flk5 : 1; + uint32_t rw5 : 1; + uint32_t pte5 : 1; + uint32_t alk4 : 1; + uint32_t flk4 : 1; + uint32_t rw4 : 1; + uint32_t pte4 : 1; + uint32_t alk3 : 1; + uint32_t flk3 : 1; + uint32_t rw3 : 1; + uint32_t pte3 : 1; + uint32_t alk2 : 1; + uint32_t flk2 : 1; + uint32_t rw2 : 1; + uint32_t pte2 : 1; + uint32_t alk1 : 1; + uint32_t flk1 : 1; + uint32_t rw1 : 1; + uint32_t pte1 : 1; + uint32_t alk0 : 1; + uint32_t flk0 : 1; + uint32_t rw0 : 1; + uint32_t pte0 : 1; +#endif // _BIG_ENDIAN + } fields; +} plb_pesr_t; + + + +typedef union plb_pearl { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} plb_pearl_t; + + + +typedef union plb_pearh { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} plb_pearh_t; + + + +typedef union plb_sto_pesr { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t icu_te : 1; + uint32_t icu_rw : 1; + uint32_t reserved2 : 2; + uint32_t dcu_te : 1; + uint32_t dcu_rw : 1; + uint32_t reserved6 : 2; + uint32_t _reserved0 : 24; +#else + uint32_t _reserved0 : 24; + uint32_t reserved6 : 2; + uint32_t dcu_rw : 1; + uint32_t dcu_te : 1; + uint32_t reserved2 : 2; + uint32_t icu_rw : 1; + uint32_t icu_te : 1; +#endif // _BIG_ENDIAN + } fields; +} plb_sto_pesr_t; + + + +typedef union plb_sto_pear { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t value : 32; +#else + uint32_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} plb_sto_pear_t; + + +#endif // __ASSEMBLER__ +#endif // __PLB_ARBITER_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/plb_arbiter_register_addresses.h b/src/ssx/pgp/registers/plb_arbiter_register_addresses.h new file mode 100755 index 0000000..2bc2f41 --- /dev/null +++ b/src/ssx/pgp/registers/plb_arbiter_register_addresses.h @@ -0,0 +1,28 @@ +#ifndef __PLB_ARBITER_REGISTER_ADDRESSES_H__ +#define __PLB_ARBITER_REGISTER_ADDRESSES_H__ + +// $Id: plb_arbiter_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/plb_arbiter_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file plb_arbiter_register_addresses.h +/// \brief Symbolic addresses for the PLB_ARBITER unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define PLB_DCR_BASE 0x90 +#define PLB_PREV 0x00000092 +#define PLB_PACR 0x00000093 +#define PLB_PESR 0x00000094 +#define PLB_PEARL 0x00000096 +#define PLB_PEARH 0x00000097 +#define PLB_STO_PESR 0x00000099 +#define PLB_STO_PEAR 0x00000098 + +#endif // __PLB_ARBITER_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/pmc_firmware_registers.h b/src/ssx/pgp/registers/pmc_firmware_registers.h new file mode 100755 index 0000000..76642a4 --- /dev/null +++ b/src/ssx/pgp/registers/pmc_firmware_registers.h @@ -0,0 +1,3140 @@ +#ifndef __PMC_FIRMWARE_REGISTERS_H__ +#define __PMC_FIRMWARE_REGISTERS_H__ + +// $Id: pmc_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pmc_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file pmc_firmware_registers.h +/// \brief C register structs for the PMC unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union pmc_mode_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t enable_hw_pstate_mode : 1; + uint32_t enable_fw_auction_pstate_mode : 1; + uint32_t enable_fw_pstate_mode : 1; + uint32_t enable_pstate_voltage_changes : 1; + uint32_t enable_global_actual_pstate_forwarding : 1; + uint32_t halt_pstate_master_fsm : 1; + uint32_t enable_interchip_interface : 1; + uint32_t interchip_mode : 1; + uint32_t enable_interchip_pstate_in_haps : 1; + uint32_t enable_pstate_stepping : 1; + uint32_t honor_oha_idle_state_requests : 1; + uint32_t vid_endianess : 1; + uint32_t reset_all_pmc_registers : 1; + uint32_t safe_mode_without_spivid : 1; + uint32_t halt_idle_state_master_fsm : 1; + uint32_t interchip_halt_if : 1; + uint32_t unfreeze_pstate_processing : 1; + uint32_t spivid_reset_if : 1; + uint32_t unfreeze_istate_processing : 1; + uint32_t _reserved0 : 13; +#else + uint32_t _reserved0 : 13; + uint32_t unfreeze_istate_processing : 1; + uint32_t spivid_reset_if : 1; + uint32_t unfreeze_pstate_processing : 1; + uint32_t interchip_halt_if : 1; + uint32_t halt_idle_state_master_fsm : 1; + uint32_t safe_mode_without_spivid : 1; + uint32_t reset_all_pmc_registers : 1; + uint32_t vid_endianess : 1; + uint32_t honor_oha_idle_state_requests : 1; + uint32_t enable_pstate_stepping : 1; + uint32_t enable_interchip_pstate_in_haps : 1; + uint32_t interchip_mode : 1; + uint32_t enable_interchip_interface : 1; + uint32_t halt_pstate_master_fsm : 1; + uint32_t enable_global_actual_pstate_forwarding : 1; + uint32_t enable_pstate_voltage_changes : 1; + uint32_t enable_fw_pstate_mode : 1; + uint32_t enable_fw_auction_pstate_mode : 1; + uint32_t enable_hw_pstate_mode : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_mode_reg_t; + + + +typedef union pmc_hardware_auction_pstate_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + int32_t haps : 8; + uint32_t kuv_actual : 8; + uint32_t kuv_received : 8; + uint32_t _reserved0 : 8; +#else + uint32_t _reserved0 : 8; + uint32_t kuv_received : 8; + uint32_t kuv_actual : 8; + int32_t haps : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_hardware_auction_pstate_reg_t; + + + +typedef union pmc_pstate_monitor_and_ctrl_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + int32_t gpst_val : 8; + int32_t gpsst : 8; + int32_t gpsa : 8; + int32_t gapr : 8; +#else + int32_t gapr : 8; + int32_t gpsa : 8; + int32_t gpsst : 8; + int32_t gpst_val : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_pstate_monitor_and_ctrl_reg_t; + + + +typedef union pmc_rail_bounds_register { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + int32_t pmin_rail : 8; + int32_t pmax_rail : 8; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + int32_t pmax_rail : 8; + int32_t pmin_rail : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_rail_bounds_register_t; + + + +typedef union pmc_global_pstate_bounds_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t gpsi_min : 8; + uint32_t gpst_number_of_entries_minus_one : 7; + uint32_t _reserved0 : 17; +#else + uint32_t _reserved0 : 17; + uint32_t gpst_number_of_entries_minus_one : 7; + uint32_t gpsi_min : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_global_pstate_bounds_reg_t; + + + +typedef union pmc_parameter_reg0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t pstate_stepsize : 7; + uint32_t vrm_stepdelay_range : 4; + uint32_t vrm_stepdelay_value : 4; + uint32_t hangpulse_predivider : 6; + uint32_t gpsa_timeout_value : 8; + uint32_t gpsa_timeout_value_sel : 1; + uint32_t _reserved0 : 2; +#else + uint32_t _reserved0 : 2; + uint32_t gpsa_timeout_value_sel : 1; + uint32_t gpsa_timeout_value : 8; + uint32_t hangpulse_predivider : 6; + uint32_t vrm_stepdelay_value : 4; + uint32_t vrm_stepdelay_range : 4; + uint32_t pstate_stepsize : 7; +#endif // _BIG_ENDIAN + } fields; +} pmc_parameter_reg0_t; + + + +typedef union pmc_parameter_reg1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t ba_sram_pstate_table : 22; + int32_t pvsafe : 8; + uint32_t _reserved0 : 2; +#else + uint32_t _reserved0 : 2; + int32_t pvsafe : 8; + uint32_t ba_sram_pstate_table : 22; +#endif // _BIG_ENDIAN + } fields; +} pmc_parameter_reg1_t; + + + +typedef union pmc_eff_global_actual_voltage_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t maxreg_vdd : 8; + uint32_t maxreg_vcs : 8; + uint32_t eff_evid_vdd : 8; + uint32_t eff_evid_vcs : 8; +#else + uint32_t eff_evid_vcs : 8; + uint32_t eff_evid_vdd : 8; + uint32_t maxreg_vcs : 8; + uint32_t maxreg_vdd : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_eff_global_actual_voltage_reg_t; + + + +typedef union pmc_global_actual_voltage_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t evid_vdd : 8; + uint32_t evid_vcs : 8; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t evid_vcs : 8; + uint32_t evid_vdd : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_global_actual_voltage_reg_t; + + + +typedef union pmc_status_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t pstate_processing_is_suspended : 1; + uint32_t gpsa_bdcst_error : 1; + uint32_t gpsa_bdcst_resp_info : 3; + uint32_t gpsa_vchg_error : 1; + uint32_t gpsa_timeout_error : 1; + uint32_t gpsa_chg_ongoing : 1; + uint32_t volt_chg_ongoing : 1; + uint32_t brd_cst_ongoing : 1; + uint32_t gps_table_error : 1; + uint32_t pstate_interchip_error : 1; + uint32_t istate_processing_is_suspended : 1; + uint32_t safe_mode_engaged : 1; + uint32_t _reserved0 : 18; +#else + uint32_t _reserved0 : 18; + uint32_t safe_mode_engaged : 1; + uint32_t istate_processing_is_suspended : 1; + uint32_t pstate_interchip_error : 1; + uint32_t gps_table_error : 1; + uint32_t brd_cst_ongoing : 1; + uint32_t volt_chg_ongoing : 1; + uint32_t gpsa_chg_ongoing : 1; + uint32_t gpsa_timeout_error : 1; + uint32_t gpsa_vchg_error : 1; + uint32_t gpsa_bdcst_resp_info : 3; + uint32_t gpsa_bdcst_error : 1; + uint32_t pstate_processing_is_suspended : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_status_reg_t; + + + +typedef union pmc_phase_enable_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t phase_enable : 4; + uint32_t _reserved0 : 28; +#else + uint32_t _reserved0 : 28; + uint32_t phase_enable : 4; +#endif // _BIG_ENDIAN + } fields; +} pmc_phase_enable_reg_t; + + + +typedef union pmc_undervolting_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + int32_t puv_min : 8; + int32_t puv_max : 8; + uint32_t kuv_request : 8; + uint32_t _reserved0 : 8; +#else + uint32_t _reserved0 : 8; + uint32_t kuv_request : 8; + int32_t puv_max : 8; + int32_t puv_min : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_undervolting_reg_t; + + + +typedef union pmc_core_deconfiguration_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t core_chiplet_deconf_vector : 16; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t core_chiplet_deconf_vector : 16; +#endif // _BIG_ENDIAN + } fields; +} pmc_core_deconfiguration_reg_t; + + + +typedef union pmc_intchp_ctrl_reg1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t interchip_ga_fsm_enable : 1; + uint32_t interchip_recv_done_valid_without_if_en : 1; + uint32_t pmcic1_reserved_2 : 1; + uint32_t interchip_cpha : 1; + uint32_t interchip_clock_divider : 10; + uint32_t pmcicr1_reserved_14_17 : 4; + uint32_t pmcicr1_reserved_18_20 : 3; + uint32_t _reserved0 : 11; +#else + uint32_t _reserved0 : 11; + uint32_t pmcicr1_reserved_18_20 : 3; + uint32_t pmcicr1_reserved_14_17 : 4; + uint32_t interchip_clock_divider : 10; + uint32_t interchip_cpha : 1; + uint32_t pmcic1_reserved_2 : 1; + uint32_t interchip_recv_done_valid_without_if_en : 1; + uint32_t interchip_ga_fsm_enable : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_intchp_ctrl_reg1_t; + + + +typedef union pmc_intchp_ctrl_reg2 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t interchip_ping_send : 1; + uint32_t interchip_ping_detect_clear : 1; + uint32_t interchip_ping_mode : 1; + uint32_t pmcic2_reserved3 : 1; + uint32_t pmcic2_reserved4 : 1; + uint32_t pmcic2_reserved5_7 : 3; + uint32_t _reserved0 : 24; +#else + uint32_t _reserved0 : 24; + uint32_t pmcic2_reserved5_7 : 3; + uint32_t pmcic2_reserved4 : 1; + uint32_t pmcic2_reserved3 : 1; + uint32_t interchip_ping_mode : 1; + uint32_t interchip_ping_detect_clear : 1; + uint32_t interchip_ping_send : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_intchp_ctrl_reg2_t; + + + +typedef union pmc_intchp_ctrl_reg4 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t interchip_ecc_gen_en : 1; + uint32_t interchip_ecc_check_en : 1; + uint32_t interchip_msg_rcv_overflow_check_en : 1; + uint32_t interchip_ecc_ue_block_en : 1; + uint32_t chksw_hw221732 : 1; + uint32_t slave_occ_timeout_forces_safe_mode_disable : 1; + uint32_t pmcic4_reserved6_7 : 2; + uint32_t _reserved0 : 24; +#else + uint32_t _reserved0 : 24; + uint32_t pmcic4_reserved6_7 : 2; + uint32_t slave_occ_timeout_forces_safe_mode_disable : 1; + uint32_t chksw_hw221732 : 1; + uint32_t interchip_ecc_ue_block_en : 1; + uint32_t interchip_msg_rcv_overflow_check_en : 1; + uint32_t interchip_ecc_check_en : 1; + uint32_t interchip_ecc_gen_en : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_intchp_ctrl_reg4_t; + + + +typedef union pmc_intchp_status_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t interchip_ga_ongoing : 1; + uint32_t interchip_ecc_ue : 1; + uint32_t interchip_ecc_ce : 1; + uint32_t interchip_ping_detected : 1; + uint32_t interchip_ping_ack_detected : 1; + uint32_t interchip_msg_send_ongoing : 1; + uint32_t interchip_msg_recv_detected : 1; + uint32_t interchip_fsm_err : 1; + uint32_t interchip_ping_detect_count : 8; + uint32_t interchip_slave_error_code : 4; + uint32_t interchip_msg_snd_overflow_detected : 1; + uint32_t interchip_msg_rcv_overflow_detected : 1; + uint32_t interchip_ecc_ue_err : 1; + uint32_t _reserved0 : 9; +#else + uint32_t _reserved0 : 9; + uint32_t interchip_ecc_ue_err : 1; + uint32_t interchip_msg_rcv_overflow_detected : 1; + uint32_t interchip_msg_snd_overflow_detected : 1; + uint32_t interchip_slave_error_code : 4; + uint32_t interchip_ping_detect_count : 8; + uint32_t interchip_fsm_err : 1; + uint32_t interchip_msg_recv_detected : 1; + uint32_t interchip_msg_send_ongoing : 1; + uint32_t interchip_ping_ack_detected : 1; + uint32_t interchip_ping_detected : 1; + uint32_t interchip_ecc_ce : 1; + uint32_t interchip_ecc_ue : 1; + uint32_t interchip_ga_ongoing : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_intchp_status_reg_t; + + + +typedef union pmc_intchp_command_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t interchip_reset_if : 1; + uint32_t interchip_halt_msg_fsm : 1; + uint32_t interchip_clear_sticky_bits : 1; + uint32_t _reserved0 : 29; +#else + uint32_t _reserved0 : 29; + uint32_t interchip_clear_sticky_bits : 1; + uint32_t interchip_halt_msg_fsm : 1; + uint32_t interchip_reset_if : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_intchp_command_reg_t; + + + +typedef union pmc_intchp_msg_wdata { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t interchip_msg_wdata : 32; +#else + uint32_t interchip_msg_wdata : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_intchp_msg_wdata_t; + + + +typedef union pmc_intchp_msg_rdata { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t interchip_msg_rdata : 32; +#else + uint32_t interchip_msg_rdata : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_intchp_msg_rdata_t; + + + +typedef union pmc_intchp_pstate_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + int32_t pstate_interchip : 8; + uint32_t _reserved0 : 24; +#else + uint32_t _reserved0 : 24; + int32_t pstate_interchip : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_intchp_pstate_reg_t; + + + +typedef union pmc_intchp_globack_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t gaack_interchip : 1; + int32_t gaack_interchip_pstate : 8; + uint32_t _reserved0 : 23; +#else + uint32_t _reserved0 : 23; + int32_t gaack_interchip_pstate : 8; + uint32_t gaack_interchip : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_intchp_globack_reg_t; + + + +typedef union pmc_fsmstate_status_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t mis_fsm_state : 3; + uint32_t mps_fsm_state : 5; + uint32_t svs_fsm_state : 4; + uint32_t o2s_fsm_state : 4; + uint32_t m2p_fsm_state : 4; + uint32_t o2p_fsm_state : 4; + uint32_t icp_msg_fsm_state : 5; + uint32_t _reserved0 : 3; +#else + uint32_t _reserved0 : 3; + uint32_t icp_msg_fsm_state : 5; + uint32_t o2p_fsm_state : 4; + uint32_t m2p_fsm_state : 4; + uint32_t o2s_fsm_state : 4; + uint32_t svs_fsm_state : 4; + uint32_t mps_fsm_state : 5; + uint32_t mis_fsm_state : 3; +#endif // _BIG_ENDIAN + } fields; +} pmc_fsmstate_status_reg_t; + + + +typedef union pmc_trace_mode_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t pmc_trace_mode : 4; + uint32_t trace_sel_data : 2; + uint32_t _reserved0 : 26; +#else + uint32_t _reserved0 : 26; + uint32_t trace_sel_data : 2; + uint32_t pmc_trace_mode : 4; +#endif // _BIG_ENDIAN + } fields; +} pmc_trace_mode_reg_t; + + + +typedef union pmc_spiv_ctrl_reg0a { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t spivid_frame_size : 6; + uint32_t spivid_out_count1 : 6; + uint32_t spivid_in_delay1 : 6; + uint32_t spivid_in_count1 : 6; + uint32_t _reserved0 : 8; +#else + uint32_t _reserved0 : 8; + uint32_t spivid_in_count1 : 6; + uint32_t spivid_in_delay1 : 6; + uint32_t spivid_out_count1 : 6; + uint32_t spivid_frame_size : 6; +#endif // _BIG_ENDIAN + } fields; +} pmc_spiv_ctrl_reg0a_t; + + + +typedef union pmc_spiv_ctrl_reg0b { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t spivid_out_count2 : 6; + uint32_t spivid_in_delay2 : 6; + uint32_t spivid_in_count2 : 6; + uint32_t _reserved0 : 14; +#else + uint32_t _reserved0 : 14; + uint32_t spivid_in_count2 : 6; + uint32_t spivid_in_delay2 : 6; + uint32_t spivid_out_count2 : 6; +#endif // _BIG_ENDIAN + } fields; +} pmc_spiv_ctrl_reg0b_t; + + + +typedef union pmc_spiv_ctrl_reg1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t spivid_fsm_enable : 1; + uint32_t pmcscr1_reserved_1 : 1; + uint32_t spivid_cpol : 1; + uint32_t spivid_cpha : 1; + uint32_t spivid_clock_divider : 10; + uint32_t pmcscr1_reserved_2 : 4; + uint32_t spivid_port_enable : 3; + uint32_t _reserved0 : 11; +#else + uint32_t _reserved0 : 11; + uint32_t spivid_port_enable : 3; + uint32_t pmcscr1_reserved_2 : 4; + uint32_t spivid_clock_divider : 10; + uint32_t spivid_cpha : 1; + uint32_t spivid_cpol : 1; + uint32_t pmcscr1_reserved_1 : 1; + uint32_t spivid_fsm_enable : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_spiv_ctrl_reg1_t; + + + +typedef union pmc_spiv_ctrl_reg2 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t spivid_inter_frame_delay_write_status : 17; + uint32_t _reserved0 : 15; +#else + uint32_t _reserved0 : 15; + uint32_t spivid_inter_frame_delay_write_status : 17; +#endif // _BIG_ENDIAN + } fields; +} pmc_spiv_ctrl_reg2_t; + + + +typedef union pmc_spiv_ctrl_reg3 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t spivid_inter_retry_delay : 17; + uint32_t pmc_100ns_pls_range : 6; + uint32_t _reserved0 : 9; +#else + uint32_t _reserved0 : 9; + uint32_t pmc_100ns_pls_range : 6; + uint32_t spivid_inter_retry_delay : 17; +#endif // _BIG_ENDIAN + } fields; +} pmc_spiv_ctrl_reg3_t; + + + +typedef union pmc_spiv_ctrl_reg4 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t spivid_crc_gen_en : 1; + uint32_t spivid_crc_check_en : 1; + uint32_t spivid_majority_vote_en : 1; + uint32_t spivid_max_retries : 5; + uint32_t spivid_crc_polynomial_enables : 8; + uint32_t spivid_crc_const_gen_enable : 1; + uint32_t spivid_crc_const_check_enable : 1; + uint32_t spivid_frame_sync_wrong_enable : 1; + uint32_t _reserved0 : 13; +#else + uint32_t _reserved0 : 13; + uint32_t spivid_frame_sync_wrong_enable : 1; + uint32_t spivid_crc_const_check_enable : 1; + uint32_t spivid_crc_const_gen_enable : 1; + uint32_t spivid_crc_polynomial_enables : 8; + uint32_t spivid_max_retries : 5; + uint32_t spivid_majority_vote_en : 1; + uint32_t spivid_crc_check_en : 1; + uint32_t spivid_crc_gen_en : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_spiv_ctrl_reg4_t; + + + +typedef union pmc_spiv_status_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t spivid_ongoing : 1; + uint32_t spivid_crc_error0 : 1; + uint32_t spivid_crc_error1 : 1; + uint32_t spivid_crc_error2 : 1; + uint32_t spivid_retry_timeout : 1; + uint32_t pmcssr_reserved_1 : 2; + uint32_t spivid_fsm_err : 1; + uint32_t spivid_majority_detected_a_minority0 : 1; + uint32_t spivid_majority_detected_a_minority1 : 1; + uint32_t spivid_majority_detected_a_minority2 : 1; + uint32_t spivid_majority_nr_of_minorities0 : 4; + uint32_t spivid_majority_nr_of_minorities1 : 4; + uint32_t spivid_majority_nr_of_minorities2 : 4; + uint32_t _reserved0 : 9; +#else + uint32_t _reserved0 : 9; + uint32_t spivid_majority_nr_of_minorities2 : 4; + uint32_t spivid_majority_nr_of_minorities1 : 4; + uint32_t spivid_majority_nr_of_minorities0 : 4; + uint32_t spivid_majority_detected_a_minority2 : 1; + uint32_t spivid_majority_detected_a_minority1 : 1; + uint32_t spivid_majority_detected_a_minority0 : 1; + uint32_t spivid_fsm_err : 1; + uint32_t pmcssr_reserved_1 : 2; + uint32_t spivid_retry_timeout : 1; + uint32_t spivid_crc_error2 : 1; + uint32_t spivid_crc_error1 : 1; + uint32_t spivid_crc_error0 : 1; + uint32_t spivid_ongoing : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_spiv_status_reg_t; + + + +typedef union pmc_spiv_command_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t spivid_halt_fsm : 1; + uint32_t _reserved0 : 31; +#else + uint32_t _reserved0 : 31; + uint32_t spivid_halt_fsm : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_spiv_command_reg_t; + + + +typedef union pmc_o2s_ctrl_reg0a { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2s_frame_size : 6; + uint32_t o2s_out_count1 : 6; + uint32_t o2s_in_delay1 : 6; + uint32_t o2s_in_count1 : 6; + uint32_t _reserved0 : 8; +#else + uint32_t _reserved0 : 8; + uint32_t o2s_in_count1 : 6; + uint32_t o2s_in_delay1 : 6; + uint32_t o2s_out_count1 : 6; + uint32_t o2s_frame_size : 6; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2s_ctrl_reg0a_t; + + + +typedef union pmc_o2s_ctrl_reg0b { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2s_out_count2 : 6; + uint32_t o2s_in_delay2 : 6; + uint32_t o2s_in_count2 : 6; + uint32_t _reserved0 : 14; +#else + uint32_t _reserved0 : 14; + uint32_t o2s_in_count2 : 6; + uint32_t o2s_in_delay2 : 6; + uint32_t o2s_out_count2 : 6; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2s_ctrl_reg0b_t; + + + +typedef union pmc_o2s_ctrl_reg1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2s_bridge_enable : 1; + uint32_t pmcocr1_reserved_1 : 1; + uint32_t o2s_cpol : 1; + uint32_t o2s_cpha : 1; + uint32_t o2s_clock_divider : 10; + uint32_t pmcocr1_reserved_2 : 3; + uint32_t o2s_nr_of_frames : 1; + uint32_t o2s_port_enable : 3; + uint32_t _reserved0 : 11; +#else + uint32_t _reserved0 : 11; + uint32_t o2s_port_enable : 3; + uint32_t o2s_nr_of_frames : 1; + uint32_t pmcocr1_reserved_2 : 3; + uint32_t o2s_clock_divider : 10; + uint32_t o2s_cpha : 1; + uint32_t o2s_cpol : 1; + uint32_t pmcocr1_reserved_1 : 1; + uint32_t o2s_bridge_enable : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2s_ctrl_reg1_t; + + + +typedef union pmc_o2s_ctrl_reg2 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2s_inter_frame_delay : 17; + uint32_t _reserved0 : 15; +#else + uint32_t _reserved0 : 15; + uint32_t o2s_inter_frame_delay : 17; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2s_ctrl_reg2_t; + + + +typedef union pmc_o2s_ctrl_reg4 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2s_crc_gen_en : 1; + uint32_t o2s_crc_check_en : 1; + uint32_t o2s_majority_vote_en : 1; + uint32_t o2s_max_retries : 5; + uint32_t pmcocr4_reserved8_15 : 8; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t pmcocr4_reserved8_15 : 8; + uint32_t o2s_max_retries : 5; + uint32_t o2s_majority_vote_en : 1; + uint32_t o2s_crc_check_en : 1; + uint32_t o2s_crc_gen_en : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2s_ctrl_reg4_t; + + + +typedef union pmc_o2s_status_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2s_ongoing : 1; + uint32_t o2s_crc_error0 : 1; + uint32_t o2s_crc_error1 : 1; + uint32_t o2s_crc_error2 : 1; + uint32_t o2s_retry_timeout : 1; + uint32_t o2s_write_while_bridge_busy_err : 1; + uint32_t pmcosr_reserved_6 : 1; + uint32_t o2s_fsm_err : 1; + uint32_t o2s_majority_detected_a_minority0 : 1; + uint32_t o2s_majority_detected_a_minority1 : 1; + uint32_t o2s_majority_detected_a_minority2 : 1; + uint32_t o2s_majority_nr_of_minorities0 : 4; + uint32_t o2s_majority_nr_of_minorities1 : 4; + uint32_t o2s_majority_nr_of_minorities2 : 4; + uint32_t _reserved0 : 9; +#else + uint32_t _reserved0 : 9; + uint32_t o2s_majority_nr_of_minorities2 : 4; + uint32_t o2s_majority_nr_of_minorities1 : 4; + uint32_t o2s_majority_nr_of_minorities0 : 4; + uint32_t o2s_majority_detected_a_minority2 : 1; + uint32_t o2s_majority_detected_a_minority1 : 1; + uint32_t o2s_majority_detected_a_minority0 : 1; + uint32_t o2s_fsm_err : 1; + uint32_t pmcosr_reserved_6 : 1; + uint32_t o2s_write_while_bridge_busy_err : 1; + uint32_t o2s_retry_timeout : 1; + uint32_t o2s_crc_error2 : 1; + uint32_t o2s_crc_error1 : 1; + uint32_t o2s_crc_error0 : 1; + uint32_t o2s_ongoing : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2s_status_reg_t; + + + +typedef union pmc_o2s_command_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2s_halt_retries : 1; + uint32_t o2s_clear_sticky_bits : 1; + uint32_t _reserved0 : 30; +#else + uint32_t _reserved0 : 30; + uint32_t o2s_clear_sticky_bits : 1; + uint32_t o2s_halt_retries : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2s_command_reg_t; + + + +typedef union pmc_o2s_wdata_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2s_wdata : 32; +#else + uint32_t o2s_wdata : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2s_wdata_reg_t; + + + +typedef union pmc_o2s_rdata_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2s_rdata : 32; +#else + uint32_t o2s_rdata : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2s_rdata_reg_t; + + + +typedef union pmc_o2p_addr_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2p_write_plus_read : 1; + uint32_t o2p_mc : 1; + uint32_t o2p_slave_addr : 6; + uint32_t o2p_read_not_write : 1; + uint32_t reserved_bit_pmco2par2 : 3; + uint32_t o2p_pcb_port : 4; + uint32_t o2p_pcb_reg_addr : 16; +#else + uint32_t o2p_pcb_reg_addr : 16; + uint32_t o2p_pcb_port : 4; + uint32_t reserved_bit_pmco2par2 : 3; + uint32_t o2p_read_not_write : 1; + uint32_t o2p_slave_addr : 6; + uint32_t o2p_mc : 1; + uint32_t o2p_write_plus_read : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2p_addr_reg_t; + + + +typedef union pmc_o2p_ctrl_status_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2p_ongoing : 1; + uint32_t o2p_scresp : 3; + uint32_t o2p_write_while_bridge_busy_err : 1; + uint32_t o2p_fsm_err : 1; + uint32_t o2p_abort : 1; + uint32_t o2p_parity_error : 1; + uint32_t o2p_clear_sticky_bits : 1; + uint32_t _reserved0 : 23; +#else + uint32_t _reserved0 : 23; + uint32_t o2p_clear_sticky_bits : 1; + uint32_t o2p_parity_error : 1; + uint32_t o2p_abort : 1; + uint32_t o2p_fsm_err : 1; + uint32_t o2p_write_while_bridge_busy_err : 1; + uint32_t o2p_scresp : 3; + uint32_t o2p_ongoing : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2p_ctrl_status_reg_t; + + + +typedef union pmc_o2p_send_data_hi_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2p_send_data_hi : 32; +#else + uint32_t o2p_send_data_hi : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2p_send_data_hi_reg_t; + + + +typedef union pmc_o2p_send_data_lo_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2p_send_data_lo : 32; +#else + uint32_t o2p_send_data_lo : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2p_send_data_lo_reg_t; + + + +typedef union pmc_o2p_recv_data_hi_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2p_receive_data_hi : 32; +#else + uint32_t o2p_receive_data_hi : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2p_recv_data_hi_reg_t; + + + +typedef union pmc_o2p_recv_data_lo_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t o2p_receive_data_lo : 32; +#else + uint32_t o2p_receive_data_lo : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_o2p_recv_data_lo_reg_t; + + + +typedef union pmc_occ_heartbeat_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t pmc_occ_heartbeat_time : 16; + uint32_t pmc_occ_heartbeat_en : 1; + uint32_t _reserved0 : 15; +#else + uint32_t _reserved0 : 15; + uint32_t pmc_occ_heartbeat_en : 1; + uint32_t pmc_occ_heartbeat_time : 16; +#endif // _BIG_ENDIAN + } fields; +} pmc_occ_heartbeat_reg_t; + + + +typedef union pmc_error_int_mask_hi_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t pmc_error_int_mask_hi : 32; +#else + uint32_t pmc_error_int_mask_hi : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_error_int_mask_hi_reg_t; + + + +typedef union pmc_error_int_mask_lo_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t pmc_error_int_mask_lo : 32; +#else + uint32_t pmc_error_int_mask_lo : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_error_int_mask_lo_reg_t; + + + +typedef union pmc_idle_suspend_mask_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t pmc_idle_suspend_mask : 16; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t pmc_idle_suspend_mask : 16; +#endif // _BIG_ENDIAN + } fields; +} pmc_idle_suspend_mask_reg_t; + + + +typedef union pmc_pend_idle_req_reg0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t idle_pending_0 : 1; + uint32_t idle_op_0 : 2; + uint32_t idle_type_0 : 1; + uint32_t idle_scope_0 : 1; + uint32_t assist_mode_0 : 1; + uint32_t reserved_pirr_0 : 2; + uint32_t idle_pending_1 : 1; + uint32_t idle_op_1 : 2; + uint32_t idle_type_1 : 1; + uint32_t idle_scope_1 : 1; + uint32_t assist_mode_1 : 1; + uint32_t reserved_pirr_1 : 2; + uint32_t idle_pending_2 : 1; + uint32_t idle_op_2 : 2; + uint32_t idle_type_2 : 1; + uint32_t idle_scope_2 : 1; + uint32_t assist_mode_2 : 1; + uint32_t reserved_pirr_2 : 2; + uint32_t idle_pending_3 : 1; + uint32_t idle_op_3 : 2; + uint32_t idle_type_3 : 1; + uint32_t idle_scope_3 : 1; + uint32_t assist_mode_3 : 1; + uint32_t reserved_pirr_3 : 2; +#else + uint32_t reserved_pirr_3 : 2; + uint32_t assist_mode_3 : 1; + uint32_t idle_scope_3 : 1; + uint32_t idle_type_3 : 1; + uint32_t idle_op_3 : 2; + uint32_t idle_pending_3 : 1; + uint32_t reserved_pirr_2 : 2; + uint32_t assist_mode_2 : 1; + uint32_t idle_scope_2 : 1; + uint32_t idle_type_2 : 1; + uint32_t idle_op_2 : 2; + uint32_t idle_pending_2 : 1; + uint32_t reserved_pirr_1 : 2; + uint32_t assist_mode_1 : 1; + uint32_t idle_scope_1 : 1; + uint32_t idle_type_1 : 1; + uint32_t idle_op_1 : 2; + uint32_t idle_pending_1 : 1; + uint32_t reserved_pirr_0 : 2; + uint32_t assist_mode_0 : 1; + uint32_t idle_scope_0 : 1; + uint32_t idle_type_0 : 1; + uint32_t idle_op_0 : 2; + uint32_t idle_pending_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_pend_idle_req_reg0_t; + + + +typedef union pmc_pend_idle_req_reg1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t idle_pending_4 : 1; + uint32_t idle_op_4 : 2; + uint32_t idle_type_4 : 1; + uint32_t idle_scope_4 : 1; + uint32_t assist_mode_4 : 1; + uint32_t reserved_pirr_4 : 2; + uint32_t idle_pending_5 : 1; + uint32_t idle_op_5 : 2; + uint32_t idle_type_5 : 1; + uint32_t idle_scope_5 : 1; + uint32_t assist_mode_5 : 1; + uint32_t reserved_pirr_5 : 2; + uint32_t idle_pending_6 : 1; + uint32_t idle_op_6 : 2; + uint32_t idle_type_6 : 1; + uint32_t idle_scope_6 : 1; + uint32_t assist_mode_6 : 1; + uint32_t reserved_pirr_6 : 2; + uint32_t idle_pending_7 : 1; + uint32_t idle_op_7 : 2; + uint32_t idle_type_7 : 1; + uint32_t idle_scope_7 : 1; + uint32_t assist_mode_7 : 1; + uint32_t reserved_pirr_7 : 2; +#else + uint32_t reserved_pirr_7 : 2; + uint32_t assist_mode_7 : 1; + uint32_t idle_scope_7 : 1; + uint32_t idle_type_7 : 1; + uint32_t idle_op_7 : 2; + uint32_t idle_pending_7 : 1; + uint32_t reserved_pirr_6 : 2; + uint32_t assist_mode_6 : 1; + uint32_t idle_scope_6 : 1; + uint32_t idle_type_6 : 1; + uint32_t idle_op_6 : 2; + uint32_t idle_pending_6 : 1; + uint32_t reserved_pirr_5 : 2; + uint32_t assist_mode_5 : 1; + uint32_t idle_scope_5 : 1; + uint32_t idle_type_5 : 1; + uint32_t idle_op_5 : 2; + uint32_t idle_pending_5 : 1; + uint32_t reserved_pirr_4 : 2; + uint32_t assist_mode_4 : 1; + uint32_t idle_scope_4 : 1; + uint32_t idle_type_4 : 1; + uint32_t idle_op_4 : 2; + uint32_t idle_pending_4 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_pend_idle_req_reg1_t; + + + +typedef union pmc_pend_idle_req_reg2 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t idle_pending_8 : 1; + uint32_t idle_op_8 : 2; + uint32_t idle_type_8 : 1; + uint32_t idle_scope_8 : 1; + uint32_t assist_mode_8 : 1; + uint32_t reserved_pirr_8 : 2; + uint32_t idle_pending_9 : 1; + uint32_t idle_op_9 : 2; + uint32_t idle_type_9 : 1; + uint32_t idle_scope_9 : 1; + uint32_t assist_mode_9 : 1; + uint32_t reserved_pirr_9 : 2; + uint32_t idle_pending_10 : 1; + uint32_t idle_op_10 : 2; + uint32_t idle_type_10 : 1; + uint32_t idle_scope_10 : 1; + uint32_t assist_mode_10 : 1; + uint32_t reserved_pirr_10 : 2; + uint32_t idle_pending_11 : 1; + uint32_t idle_op_11 : 2; + uint32_t idle_type_11 : 1; + uint32_t idle_scope_11 : 1; + uint32_t assist_mode_11 : 1; + uint32_t reserved_pirr_11 : 2; +#else + uint32_t reserved_pirr_11 : 2; + uint32_t assist_mode_11 : 1; + uint32_t idle_scope_11 : 1; + uint32_t idle_type_11 : 1; + uint32_t idle_op_11 : 2; + uint32_t idle_pending_11 : 1; + uint32_t reserved_pirr_10 : 2; + uint32_t assist_mode_10 : 1; + uint32_t idle_scope_10 : 1; + uint32_t idle_type_10 : 1; + uint32_t idle_op_10 : 2; + uint32_t idle_pending_10 : 1; + uint32_t reserved_pirr_9 : 2; + uint32_t assist_mode_9 : 1; + uint32_t idle_scope_9 : 1; + uint32_t idle_type_9 : 1; + uint32_t idle_op_9 : 2; + uint32_t idle_pending_9 : 1; + uint32_t reserved_pirr_8 : 2; + uint32_t assist_mode_8 : 1; + uint32_t idle_scope_8 : 1; + uint32_t idle_type_8 : 1; + uint32_t idle_op_8 : 2; + uint32_t idle_pending_8 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_pend_idle_req_reg2_t; + + + +typedef union pmc_pend_idle_req_reg3 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t idle_pending_12 : 1; + uint32_t idle_op_12 : 2; + uint32_t idle_type_12 : 1; + uint32_t idle_scope_12 : 1; + uint32_t assist_mode_12 : 1; + uint32_t reserved_pirr_12 : 2; + uint32_t idle_pending_13 : 1; + uint32_t idle_op_13 : 2; + uint32_t idle_type_13 : 1; + uint32_t idle_scope_13 : 1; + uint32_t assist_mode_13 : 1; + uint32_t reserved_pirr_13 : 2; + uint32_t idle_pending_14 : 1; + uint32_t idle_op_14 : 2; + uint32_t idle_type_14 : 1; + uint32_t idle_scope_14 : 1; + uint32_t assist_mode_14 : 1; + uint32_t reserved_pirr_14 : 2; + uint32_t idle_pending_15 : 1; + uint32_t idle_op_15 : 2; + uint32_t idle_type_15 : 1; + uint32_t idle_scope_15 : 1; + uint32_t assist_mode_15 : 1; + uint32_t reserved_pirr_15 : 2; +#else + uint32_t reserved_pirr_15 : 2; + uint32_t assist_mode_15 : 1; + uint32_t idle_scope_15 : 1; + uint32_t idle_type_15 : 1; + uint32_t idle_op_15 : 2; + uint32_t idle_pending_15 : 1; + uint32_t reserved_pirr_14 : 2; + uint32_t assist_mode_14 : 1; + uint32_t idle_scope_14 : 1; + uint32_t idle_type_14 : 1; + uint32_t idle_op_14 : 2; + uint32_t idle_pending_14 : 1; + uint32_t reserved_pirr_13 : 2; + uint32_t assist_mode_13 : 1; + uint32_t idle_scope_13 : 1; + uint32_t idle_type_13 : 1; + uint32_t idle_op_13 : 2; + uint32_t idle_pending_13 : 1; + uint32_t reserved_pirr_12 : 2; + uint32_t assist_mode_12 : 1; + uint32_t idle_scope_12 : 1; + uint32_t idle_type_12 : 1; + uint32_t idle_op_12 : 2; + uint32_t idle_pending_12 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_pend_idle_req_reg3_t; + + + +typedef union pmc_sleep_int_req_vec_reg0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t fastsleepentry_int_req_vec : 32; +#else + uint32_t fastsleepentry_int_req_vec : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_sleep_int_req_vec_reg0_t; + + + +typedef union pmc_sleep_int_req_vec_reg1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t deepsleepentry_int_req_vec : 32; +#else + uint32_t deepsleepentry_int_req_vec : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_sleep_int_req_vec_reg1_t; + + + +typedef union pmc_sleep_int_req_vec_reg2 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t fastsleepexit_int_req_vec : 32; +#else + uint32_t fastsleepexit_int_req_vec : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_sleep_int_req_vec_reg2_t; + + + +typedef union pmc_sleep_int_req_vec_reg3 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t deepsleepexit_int_req_vec : 32; +#else + uint32_t deepsleepexit_int_req_vec : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_sleep_int_req_vec_reg3_t; + + + +typedef union pmc_winkle_int_req_vec_reg0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t fastwinkleentry_int_req_vec : 32; +#else + uint32_t fastwinkleentry_int_req_vec : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_winkle_int_req_vec_reg0_t; + + + +typedef union pmc_winkle_int_req_vec_reg1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t deepwinkleentry_int_req_vec : 32; +#else + uint32_t deepwinkleentry_int_req_vec : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_winkle_int_req_vec_reg1_t; + + + +typedef union pmc_winkle_int_req_vec_reg2 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t fastwinkleexit_int_req_vec : 32; +#else + uint32_t fastwinkleexit_int_req_vec : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_winkle_int_req_vec_reg2_t; + + + +typedef union pmc_winkle_int_req_vec_reg3 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t deepwinkleexit_int_req_vec : 32; +#else + uint32_t deepwinkleexit_int_req_vec : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_winkle_int_req_vec_reg3_t; + + + +typedef union pmc_nap_int_req_vec_reg0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t napentry_int_req_vec : 16; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t napentry_int_req_vec : 16; +#endif // _BIG_ENDIAN + } fields; +} pmc_nap_int_req_vec_reg0_t; + + + +typedef union pmc_nap_int_req_vec_reg1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t napexit_int_req_vec : 25; + uint32_t _reserved0 : 7; +#else + uint32_t _reserved0 : 7; + uint32_t napexit_int_req_vec : 25; +#endif // _BIG_ENDIAN + } fields; +} pmc_nap_int_req_vec_reg1_t; + + + +typedef union pmc_pore_req_reg0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t porrr_reserved0 : 8; + uint32_t porrr_start_vector : 4; + uint32_t porrr_reserved1 : 8; + uint32_t porrr_pore_busy : 1; + uint32_t porrr_pore_suspended : 1; + uint32_t porrr_porrtc_busy : 1; + uint32_t _reserved0 : 9; +#else + uint32_t _reserved0 : 9; + uint32_t porrr_porrtc_busy : 1; + uint32_t porrr_pore_suspended : 1; + uint32_t porrr_pore_busy : 1; + uint32_t porrr_reserved1 : 8; + uint32_t porrr_start_vector : 4; + uint32_t porrr_reserved0 : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_pore_req_reg0_t; + + + +typedef union pmc_pore_req_reg1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t porrr_chiplet_enable_0 : 1; + uint32_t porrr_chiplet_enable_1 : 1; + uint32_t porrr_chiplet_enable_2 : 1; + uint32_t porrr_chiplet_enable_3 : 1; + uint32_t porrr_chiplet_enable_4 : 1; + uint32_t porrr_chiplet_enable_5 : 1; + uint32_t porrr_chiplet_enable_6 : 1; + uint32_t porrr_chiplet_enable_7 : 1; + uint32_t porrr_chiplet_enable_8 : 1; + uint32_t porrr_chiplet_enable_9 : 1; + uint32_t porrr_chiplet_enable_10 : 1; + uint32_t porrr_chiplet_enable_11 : 1; + uint32_t porrr_chiplet_enable_12 : 1; + uint32_t porrr_chiplet_enable_13 : 1; + uint32_t porrr_chiplet_enable_14 : 1; + uint32_t porrr_chiplet_enable_15 : 1; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t porrr_chiplet_enable_15 : 1; + uint32_t porrr_chiplet_enable_14 : 1; + uint32_t porrr_chiplet_enable_13 : 1; + uint32_t porrr_chiplet_enable_12 : 1; + uint32_t porrr_chiplet_enable_11 : 1; + uint32_t porrr_chiplet_enable_10 : 1; + uint32_t porrr_chiplet_enable_9 : 1; + uint32_t porrr_chiplet_enable_8 : 1; + uint32_t porrr_chiplet_enable_7 : 1; + uint32_t porrr_chiplet_enable_6 : 1; + uint32_t porrr_chiplet_enable_5 : 1; + uint32_t porrr_chiplet_enable_4 : 1; + uint32_t porrr_chiplet_enable_3 : 1; + uint32_t porrr_chiplet_enable_2 : 1; + uint32_t porrr_chiplet_enable_1 : 1; + uint32_t porrr_chiplet_enable_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_pore_req_reg1_t; + + + +typedef union pmc_pore_req_stat_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t porrs_reserved0 : 8; + uint32_t porrs_start_vector : 4; + uint32_t pore_rc : 8; + uint32_t porrs_reserved1 : 1; + uint32_t porrs_recovery_write : 1; + uint32_t _reserved0 : 10; +#else + uint32_t _reserved0 : 10; + uint32_t porrs_recovery_write : 1; + uint32_t porrs_reserved1 : 1; + uint32_t pore_rc : 8; + uint32_t porrs_start_vector : 4; + uint32_t porrs_reserved0 : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_pore_req_stat_reg_t; + + + +typedef union pmc_pore_req_tout_th_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t porrtt_timeout_threshold : 8; + uint32_t porrtc_no_predivide : 1; + uint32_t _reserved0 : 23; +#else + uint32_t _reserved0 : 23; + uint32_t porrtc_no_predivide : 1; + uint32_t porrtt_timeout_threshold : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_pore_req_tout_th_reg_t; + + + +typedef union pmc_deep_exit_mask_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t chiplet_deep_exit_mask0 : 1; + uint32_t chiplet_deep_exit_mask1 : 1; + uint32_t chiplet_deep_exit_mask2 : 1; + uint32_t chiplet_deep_exit_mask3 : 1; + uint32_t chiplet_deep_exit_mask4 : 1; + uint32_t chiplet_deep_exit_mask5 : 1; + uint32_t chiplet_deep_exit_mask6 : 1; + uint32_t chiplet_deep_exit_mask7 : 1; + uint32_t chiplet_deep_exit_mask8 : 1; + uint32_t chiplet_deep_exit_mask9 : 1; + uint32_t chiplet_deep_exit_mask10 : 1; + uint32_t chiplet_deep_exit_mask11 : 1; + uint32_t chiplet_deep_exit_mask12 : 1; + uint32_t chiplet_deep_exit_mask13 : 1; + uint32_t chiplet_deep_exit_mask14 : 1; + uint32_t chiplet_deep_exit_mask15 : 1; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t chiplet_deep_exit_mask15 : 1; + uint32_t chiplet_deep_exit_mask14 : 1; + uint32_t chiplet_deep_exit_mask13 : 1; + uint32_t chiplet_deep_exit_mask12 : 1; + uint32_t chiplet_deep_exit_mask11 : 1; + uint32_t chiplet_deep_exit_mask10 : 1; + uint32_t chiplet_deep_exit_mask9 : 1; + uint32_t chiplet_deep_exit_mask8 : 1; + uint32_t chiplet_deep_exit_mask7 : 1; + uint32_t chiplet_deep_exit_mask6 : 1; + uint32_t chiplet_deep_exit_mask5 : 1; + uint32_t chiplet_deep_exit_mask4 : 1; + uint32_t chiplet_deep_exit_mask3 : 1; + uint32_t chiplet_deep_exit_mask2 : 1; + uint32_t chiplet_deep_exit_mask1 : 1; + uint32_t chiplet_deep_exit_mask0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_deep_exit_mask_reg_t; + + + +typedef union pmc_deep_exit_mask_reg_and { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t chiplet_deep_exit_mask0 : 1; + uint32_t chiplet_deep_exit_mask1 : 1; + uint32_t chiplet_deep_exit_mask2 : 1; + uint32_t chiplet_deep_exit_mask3 : 1; + uint32_t chiplet_deep_exit_mask4 : 1; + uint32_t chiplet_deep_exit_mask5 : 1; + uint32_t chiplet_deep_exit_mask6 : 1; + uint32_t chiplet_deep_exit_mask7 : 1; + uint32_t chiplet_deep_exit_mask8 : 1; + uint32_t chiplet_deep_exit_mask9 : 1; + uint32_t chiplet_deep_exit_mask10 : 1; + uint32_t chiplet_deep_exit_mask11 : 1; + uint32_t chiplet_deep_exit_mask12 : 1; + uint32_t chiplet_deep_exit_mask13 : 1; + uint32_t chiplet_deep_exit_mask14 : 1; + uint32_t chiplet_deep_exit_mask15 : 1; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t chiplet_deep_exit_mask15 : 1; + uint32_t chiplet_deep_exit_mask14 : 1; + uint32_t chiplet_deep_exit_mask13 : 1; + uint32_t chiplet_deep_exit_mask12 : 1; + uint32_t chiplet_deep_exit_mask11 : 1; + uint32_t chiplet_deep_exit_mask10 : 1; + uint32_t chiplet_deep_exit_mask9 : 1; + uint32_t chiplet_deep_exit_mask8 : 1; + uint32_t chiplet_deep_exit_mask7 : 1; + uint32_t chiplet_deep_exit_mask6 : 1; + uint32_t chiplet_deep_exit_mask5 : 1; + uint32_t chiplet_deep_exit_mask4 : 1; + uint32_t chiplet_deep_exit_mask3 : 1; + uint32_t chiplet_deep_exit_mask2 : 1; + uint32_t chiplet_deep_exit_mask1 : 1; + uint32_t chiplet_deep_exit_mask0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_deep_exit_mask_reg_and_t; + + + +typedef union pmc_deep_exit_mask_reg_or { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t chiplet_deep_exit_mask0 : 1; + uint32_t chiplet_deep_exit_mask1 : 1; + uint32_t chiplet_deep_exit_mask2 : 1; + uint32_t chiplet_deep_exit_mask3 : 1; + uint32_t chiplet_deep_exit_mask4 : 1; + uint32_t chiplet_deep_exit_mask5 : 1; + uint32_t chiplet_deep_exit_mask6 : 1; + uint32_t chiplet_deep_exit_mask7 : 1; + uint32_t chiplet_deep_exit_mask8 : 1; + uint32_t chiplet_deep_exit_mask9 : 1; + uint32_t chiplet_deep_exit_mask10 : 1; + uint32_t chiplet_deep_exit_mask11 : 1; + uint32_t chiplet_deep_exit_mask12 : 1; + uint32_t chiplet_deep_exit_mask13 : 1; + uint32_t chiplet_deep_exit_mask14 : 1; + uint32_t chiplet_deep_exit_mask15 : 1; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t chiplet_deep_exit_mask15 : 1; + uint32_t chiplet_deep_exit_mask14 : 1; + uint32_t chiplet_deep_exit_mask13 : 1; + uint32_t chiplet_deep_exit_mask12 : 1; + uint32_t chiplet_deep_exit_mask11 : 1; + uint32_t chiplet_deep_exit_mask10 : 1; + uint32_t chiplet_deep_exit_mask9 : 1; + uint32_t chiplet_deep_exit_mask8 : 1; + uint32_t chiplet_deep_exit_mask7 : 1; + uint32_t chiplet_deep_exit_mask6 : 1; + uint32_t chiplet_deep_exit_mask5 : 1; + uint32_t chiplet_deep_exit_mask4 : 1; + uint32_t chiplet_deep_exit_mask3 : 1; + uint32_t chiplet_deep_exit_mask2 : 1; + uint32_t chiplet_deep_exit_mask1 : 1; + uint32_t chiplet_deep_exit_mask0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_deep_exit_mask_reg_or_t; + + + +typedef union pmc_core_pstate_reg0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + int32_t pstate_core0 : 8; + int32_t pstate_core1 : 8; + int32_t pstate_core2 : 8; + int32_t pstate_core3 : 8; +#else + int32_t pstate_core3 : 8; + int32_t pstate_core2 : 8; + int32_t pstate_core1 : 8; + int32_t pstate_core0 : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_core_pstate_reg0_t; + + + +typedef union pmc_core_pstate_reg1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + int32_t pstate_core4 : 8; + int32_t pstate_core5 : 8; + int32_t pstate_core6 : 8; + int32_t pstate_core7 : 8; +#else + int32_t pstate_core7 : 8; + int32_t pstate_core6 : 8; + int32_t pstate_core5 : 8; + int32_t pstate_core4 : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_core_pstate_reg1_t; + + + +typedef union pmc_core_pstate_reg2 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + int32_t pstate_core8 : 8; + int32_t pstate_core9 : 8; + int32_t pstate_core10 : 8; + int32_t pstate_core11 : 8; +#else + int32_t pstate_core11 : 8; + int32_t pstate_core10 : 8; + int32_t pstate_core9 : 8; + int32_t pstate_core8 : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_core_pstate_reg2_t; + + + +typedef union pmc_core_pstate_reg3 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + int32_t pstate_core12 : 8; + int32_t pstate_core13 : 8; + int32_t pstate_core14 : 8; + int32_t pstate_core15 : 8; +#else + int32_t pstate_core15 : 8; + int32_t pstate_core14 : 8; + int32_t pstate_core13 : 8; + int32_t pstate_core12 : 8; +#endif // _BIG_ENDIAN + } fields; +} pmc_core_pstate_reg3_t; + + + +typedef union pmc_core_power_donation_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t power_donation_core0 : 1; + uint32_t power_donation_core1 : 1; + uint32_t power_donation_core2 : 1; + uint32_t power_donation_core3 : 1; + uint32_t power_donation_core4 : 1; + uint32_t power_donation_core5 : 1; + uint32_t power_donation_core6 : 1; + uint32_t power_donation_core7 : 1; + uint32_t power_donation_core8 : 1; + uint32_t power_donation_core9 : 1; + uint32_t power_donation_core10 : 1; + uint32_t power_donation_core11 : 1; + uint32_t power_donation_core12 : 1; + uint32_t power_donation_core13 : 1; + uint32_t power_donation_core14 : 1; + uint32_t power_donation_core15 : 1; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t power_donation_core15 : 1; + uint32_t power_donation_core14 : 1; + uint32_t power_donation_core13 : 1; + uint32_t power_donation_core12 : 1; + uint32_t power_donation_core11 : 1; + uint32_t power_donation_core10 : 1; + uint32_t power_donation_core9 : 1; + uint32_t power_donation_core8 : 1; + uint32_t power_donation_core7 : 1; + uint32_t power_donation_core6 : 1; + uint32_t power_donation_core5 : 1; + uint32_t power_donation_core4 : 1; + uint32_t power_donation_core3 : 1; + uint32_t power_donation_core2 : 1; + uint32_t power_donation_core1 : 1; + uint32_t power_donation_core0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_core_power_donation_reg_t; + + + +typedef union pmc_pmax_sync_collection_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t pmax_sync0 : 1; + uint32_t pmax_sync1 : 1; + uint32_t pmax_sync2 : 1; + uint32_t pmax_sync3 : 1; + uint32_t pmax_sync4 : 1; + uint32_t pmax_sync5 : 1; + uint32_t pmax_sync6 : 1; + uint32_t pmax_sync7 : 1; + uint32_t pmax_sync8 : 1; + uint32_t pmax_sync9 : 1; + uint32_t pmax_sync10 : 1; + uint32_t pmax_sync11 : 1; + uint32_t pmax_sync12 : 1; + uint32_t pmax_sync13 : 1; + uint32_t pmax_sync14 : 1; + uint32_t pmax_sync15 : 1; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t pmax_sync15 : 1; + uint32_t pmax_sync14 : 1; + uint32_t pmax_sync13 : 1; + uint32_t pmax_sync12 : 1; + uint32_t pmax_sync11 : 1; + uint32_t pmax_sync10 : 1; + uint32_t pmax_sync9 : 1; + uint32_t pmax_sync8 : 1; + uint32_t pmax_sync7 : 1; + uint32_t pmax_sync6 : 1; + uint32_t pmax_sync5 : 1; + uint32_t pmax_sync4 : 1; + uint32_t pmax_sync3 : 1; + uint32_t pmax_sync2 : 1; + uint32_t pmax_sync1 : 1; + uint32_t pmax_sync0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_pmax_sync_collection_reg_t; + + + +typedef union pmc_pmax_sync_collection_mask_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t pmax_sync_mask0 : 1; + uint32_t pmax_sync_mask1 : 1; + uint32_t pmax_sync_mask2 : 1; + uint32_t pmax_sync_mask3 : 1; + uint32_t pmax_sync_mask4 : 1; + uint32_t pmax_sync_mask5 : 1; + uint32_t pmax_sync_mask6 : 1; + uint32_t pmax_sync_mask7 : 1; + uint32_t pmax_sync_mask8 : 1; + uint32_t pmax_sync_mask9 : 1; + uint32_t pmax_sync_mask10 : 1; + uint32_t pmax_sync_mask11 : 1; + uint32_t pmax_sync_mask12 : 1; + uint32_t pmax_sync_mask13 : 1; + uint32_t pmax_sync_mask14 : 1; + uint32_t pmax_sync_mask15 : 1; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t pmax_sync_mask15 : 1; + uint32_t pmax_sync_mask14 : 1; + uint32_t pmax_sync_mask13 : 1; + uint32_t pmax_sync_mask12 : 1; + uint32_t pmax_sync_mask11 : 1; + uint32_t pmax_sync_mask10 : 1; + uint32_t pmax_sync_mask9 : 1; + uint32_t pmax_sync_mask8 : 1; + uint32_t pmax_sync_mask7 : 1; + uint32_t pmax_sync_mask6 : 1; + uint32_t pmax_sync_mask5 : 1; + uint32_t pmax_sync_mask4 : 1; + uint32_t pmax_sync_mask3 : 1; + uint32_t pmax_sync_mask2 : 1; + uint32_t pmax_sync_mask1 : 1; + uint32_t pmax_sync_mask0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_pmax_sync_collection_mask_reg_t; + + + +typedef union pmc_gpsa_ack_collection_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t gpsa_ack0 : 1; + uint32_t gpsa_ack1 : 1; + uint32_t gpsa_ack2 : 1; + uint32_t gpsa_ack3 : 1; + uint32_t gpsa_ack4 : 1; + uint32_t gpsa_ack5 : 1; + uint32_t gpsa_ack6 : 1; + uint32_t gpsa_ack7 : 1; + uint32_t gpsa_ack8 : 1; + uint32_t gpsa_ack9 : 1; + uint32_t gpsa_ack10 : 1; + uint32_t gpsa_ack11 : 1; + uint32_t gpsa_ack12 : 1; + uint32_t gpsa_ack13 : 1; + uint32_t gpsa_ack14 : 1; + uint32_t gpsa_ack15 : 1; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t gpsa_ack15 : 1; + uint32_t gpsa_ack14 : 1; + uint32_t gpsa_ack13 : 1; + uint32_t gpsa_ack12 : 1; + uint32_t gpsa_ack11 : 1; + uint32_t gpsa_ack10 : 1; + uint32_t gpsa_ack9 : 1; + uint32_t gpsa_ack8 : 1; + uint32_t gpsa_ack7 : 1; + uint32_t gpsa_ack6 : 1; + uint32_t gpsa_ack5 : 1; + uint32_t gpsa_ack4 : 1; + uint32_t gpsa_ack3 : 1; + uint32_t gpsa_ack2 : 1; + uint32_t gpsa_ack1 : 1; + uint32_t gpsa_ack0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_gpsa_ack_collection_reg_t; + + + +typedef union pmc_gpsa_ack_collection_mask_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t gpsa_ack_mask0 : 1; + uint32_t gpsa_ack_mask1 : 1; + uint32_t gpsa_ack_mask2 : 1; + uint32_t gpsa_ack_mask3 : 1; + uint32_t gpsa_ack_mask4 : 1; + uint32_t gpsa_ack_mask5 : 1; + uint32_t gpsa_ack_mask6 : 1; + uint32_t gpsa_ack_mask7 : 1; + uint32_t gpsa_ack_mask8 : 1; + uint32_t gpsa_ack_mask9 : 1; + uint32_t gpsa_ack_mask10 : 1; + uint32_t gpsa_ack_mask11 : 1; + uint32_t gpsa_ack_mask12 : 1; + uint32_t gpsa_ack_mask13 : 1; + uint32_t gpsa_ack_mask14 : 1; + uint32_t gpsa_ack_mask15 : 1; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t gpsa_ack_mask15 : 1; + uint32_t gpsa_ack_mask14 : 1; + uint32_t gpsa_ack_mask13 : 1; + uint32_t gpsa_ack_mask12 : 1; + uint32_t gpsa_ack_mask11 : 1; + uint32_t gpsa_ack_mask10 : 1; + uint32_t gpsa_ack_mask9 : 1; + uint32_t gpsa_ack_mask8 : 1; + uint32_t gpsa_ack_mask7 : 1; + uint32_t gpsa_ack_mask6 : 1; + uint32_t gpsa_ack_mask5 : 1; + uint32_t gpsa_ack_mask4 : 1; + uint32_t gpsa_ack_mask3 : 1; + uint32_t gpsa_ack_mask2 : 1; + uint32_t gpsa_ack_mask1 : 1; + uint32_t gpsa_ack_mask0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_gpsa_ack_collection_mask_reg_t; + + + +typedef union pmc_pore_scratch_reg0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t porscr_scratch0 : 32; +#else + uint32_t porscr_scratch0 : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_pore_scratch_reg0_t; + + + +typedef union pmc_pore_scratch_reg1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t porscr_scratch1 : 32; +#else + uint32_t porscr_scratch1 : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_pore_scratch_reg1_t; + + + +typedef union pmc_deep_idle_exit_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t deep_exit_pending_and_masked_0 : 1; + uint32_t deep_exit_pending_and_masked_1 : 1; + uint32_t deep_exit_pending_and_masked_2 : 1; + uint32_t deep_exit_pending_and_masked_3 : 1; + uint32_t deep_exit_pending_and_masked_4 : 1; + uint32_t deep_exit_pending_and_masked_5 : 1; + uint32_t deep_exit_pending_and_masked_6 : 1; + uint32_t deep_exit_pending_and_masked_7 : 1; + uint32_t deep_exit_pending_and_masked_8 : 1; + uint32_t deep_exit_pending_and_masked_9 : 1; + uint32_t deep_exit_pending_and_masked_10 : 1; + uint32_t deep_exit_pending_and_masked_11 : 1; + uint32_t deep_exit_pending_and_masked_12 : 1; + uint32_t deep_exit_pending_and_masked_13 : 1; + uint32_t deep_exit_pending_and_masked_14 : 1; + uint32_t deep_exit_pending_and_masked_15 : 1; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t deep_exit_pending_and_masked_15 : 1; + uint32_t deep_exit_pending_and_masked_14 : 1; + uint32_t deep_exit_pending_and_masked_13 : 1; + uint32_t deep_exit_pending_and_masked_12 : 1; + uint32_t deep_exit_pending_and_masked_11 : 1; + uint32_t deep_exit_pending_and_masked_10 : 1; + uint32_t deep_exit_pending_and_masked_9 : 1; + uint32_t deep_exit_pending_and_masked_8 : 1; + uint32_t deep_exit_pending_and_masked_7 : 1; + uint32_t deep_exit_pending_and_masked_6 : 1; + uint32_t deep_exit_pending_and_masked_5 : 1; + uint32_t deep_exit_pending_and_masked_4 : 1; + uint32_t deep_exit_pending_and_masked_3 : 1; + uint32_t deep_exit_pending_and_masked_2 : 1; + uint32_t deep_exit_pending_and_masked_1 : 1; + uint32_t deep_exit_pending_and_masked_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_deep_idle_exit_reg_t; + + + +typedef union pmc_deep_status_reg { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t deep_idle_state_core0 : 1; + uint32_t deep_idle_state_core1 : 1; + uint32_t deep_idle_state_core2 : 1; + uint32_t deep_idle_state_core3 : 1; + uint32_t deep_idle_state_core4 : 1; + uint32_t deep_idle_state_core5 : 1; + uint32_t deep_idle_state_core6 : 1; + uint32_t deep_idle_state_core7 : 1; + uint32_t deep_idle_state_core8 : 1; + uint32_t deep_idle_state_core9 : 1; + uint32_t deep_idle_state_core10 : 1; + uint32_t deep_idle_state_core11 : 1; + uint32_t deep_idle_state_core12 : 1; + uint32_t deep_idle_state_core13 : 1; + uint32_t deep_idle_state_core14 : 1; + uint32_t deep_idle_state_core15 : 1; + uint32_t winkle_state_core0 : 1; + uint32_t winkle_state_core1 : 1; + uint32_t winkle_state_core2 : 1; + uint32_t winkle_state_core3 : 1; + uint32_t winkle_state_core4 : 1; + uint32_t winkle_state_core5 : 1; + uint32_t winkle_state_core6 : 1; + uint32_t winkle_state_core7 : 1; + uint32_t winkle_state_core8 : 1; + uint32_t winkle_state_core9 : 1; + uint32_t winkle_state_core10 : 1; + uint32_t winkle_state_core11 : 1; + uint32_t winkle_state_core12 : 1; + uint32_t winkle_state_core13 : 1; + uint32_t winkle_state_core14 : 1; + uint32_t winkle_state_core15 : 1; +#else + uint32_t winkle_state_core15 : 1; + uint32_t winkle_state_core14 : 1; + uint32_t winkle_state_core13 : 1; + uint32_t winkle_state_core12 : 1; + uint32_t winkle_state_core11 : 1; + uint32_t winkle_state_core10 : 1; + uint32_t winkle_state_core9 : 1; + uint32_t winkle_state_core8 : 1; + uint32_t winkle_state_core7 : 1; + uint32_t winkle_state_core6 : 1; + uint32_t winkle_state_core5 : 1; + uint32_t winkle_state_core4 : 1; + uint32_t winkle_state_core3 : 1; + uint32_t winkle_state_core2 : 1; + uint32_t winkle_state_core1 : 1; + uint32_t winkle_state_core0 : 1; + uint32_t deep_idle_state_core15 : 1; + uint32_t deep_idle_state_core14 : 1; + uint32_t deep_idle_state_core13 : 1; + uint32_t deep_idle_state_core12 : 1; + uint32_t deep_idle_state_core11 : 1; + uint32_t deep_idle_state_core10 : 1; + uint32_t deep_idle_state_core9 : 1; + uint32_t deep_idle_state_core8 : 1; + uint32_t deep_idle_state_core7 : 1; + uint32_t deep_idle_state_core6 : 1; + uint32_t deep_idle_state_core5 : 1; + uint32_t deep_idle_state_core4 : 1; + uint32_t deep_idle_state_core3 : 1; + uint32_t deep_idle_state_core2 : 1; + uint32_t deep_idle_state_core1 : 1; + uint32_t deep_idle_state_core0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_deep_status_reg_t; + + + +typedef union pmc_ba_pore_exe_trigger_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 32; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_ba_pore_exe_trigger_reg_t; + + + +typedef union pmc_pcbs_gaps_brdcast_addr { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t value : 32; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t value : 32; +#endif // _BIG_ENDIAN + } fields; +} pmc_pcbs_gaps_brdcast_addr_t; + + + +typedef union pmc_lfir_err_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t lfir_pstate_oci_master_rderr : 1; + uint64_t lfir_pstate_oci_master_rddata_parity_err : 1; + uint64_t lfir_pstate_gpst_checkbyte_err : 1; + uint64_t lfir_pstate_gack_to_err : 1; + uint64_t lfir_pstate_pib_master_nonoffline_err : 1; + uint64_t lfir_pstate_pib_master_offline_err : 1; + uint64_t lfir_pstate_oci_master_to_err : 1; + uint64_t lfir_pstate_interchip_ue_err : 1; + uint64_t lfir_pstate_interchip_errorframe_err : 1; + uint64_t lfir_pstate_ms_fsm_err : 1; + uint64_t lfir_ms_comp_parity_err : 1; + uint64_t lfir_idle_poresw_fatal_err : 1; + uint64_t lfir_idle_poresw_status_rc_err : 1; + uint64_t lfir_idle_poresw_status_value_err : 1; + uint64_t lfir_idle_poresw_write_while_inactive_err : 1; + uint64_t lfir_idle_poresw_timeout_err : 1; + uint64_t lfir_idle_oci_master_write_timeout_err : 1; + uint64_t lfir_idle_internal_err : 1; + uint64_t lfir_int_comp_parity_err : 1; + uint64_t lfir_pmc_occ_heartbeat_timeout : 1; + uint64_t lfir_spivid_crc_error0 : 1; + uint64_t lfir_spivid_crc_error1 : 1; + uint64_t lfir_spivid_crc_error2 : 1; + uint64_t lfir_spivid_retry_timeout : 1; + uint64_t lfir_spivid_fsm_err : 1; + uint64_t lfir_spivid_majority_detected_a_minority : 1; + uint64_t lfir_o2s_crc_error0 : 1; + uint64_t lfir_o2s_crc_error1 : 1; + uint64_t lfir_o2s_crc_error2 : 1; + uint64_t lfir_o2s_retry_timeout : 1; + uint64_t lfir_o2s_write_while_bridge_busy_err : 1; + uint64_t lfir_o2s_fsm_err : 1; + uint64_t lfir_o2s_majority_detected_a_minority : 1; + uint64_t lfir_o2p_write_while_bridge_busy_err : 1; + uint64_t lfir_o2p_fsm_err : 1; + uint64_t lfir_oci_slave_err : 1; + uint64_t lfir_if_comp_parity_error : 1; + uint64_t spare_fir : 10; + uint64_t fir_parity_err_dup : 1; + uint64_t fir_parity_err : 1; + uint64_t _reserved0 : 15; +#else + uint64_t _reserved0 : 15; + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err_dup : 1; + uint64_t spare_fir : 10; + uint64_t lfir_if_comp_parity_error : 1; + uint64_t lfir_oci_slave_err : 1; + uint64_t lfir_o2p_fsm_err : 1; + uint64_t lfir_o2p_write_while_bridge_busy_err : 1; + uint64_t lfir_o2s_majority_detected_a_minority : 1; + uint64_t lfir_o2s_fsm_err : 1; + uint64_t lfir_o2s_write_while_bridge_busy_err : 1; + uint64_t lfir_o2s_retry_timeout : 1; + uint64_t lfir_o2s_crc_error2 : 1; + uint64_t lfir_o2s_crc_error1 : 1; + uint64_t lfir_o2s_crc_error0 : 1; + uint64_t lfir_spivid_majority_detected_a_minority : 1; + uint64_t lfir_spivid_fsm_err : 1; + uint64_t lfir_spivid_retry_timeout : 1; + uint64_t lfir_spivid_crc_error2 : 1; + uint64_t lfir_spivid_crc_error1 : 1; + uint64_t lfir_spivid_crc_error0 : 1; + uint64_t lfir_pmc_occ_heartbeat_timeout : 1; + uint64_t lfir_int_comp_parity_err : 1; + uint64_t lfir_idle_internal_err : 1; + uint64_t lfir_idle_oci_master_write_timeout_err : 1; + uint64_t lfir_idle_poresw_timeout_err : 1; + uint64_t lfir_idle_poresw_write_while_inactive_err : 1; + uint64_t lfir_idle_poresw_status_value_err : 1; + uint64_t lfir_idle_poresw_status_rc_err : 1; + uint64_t lfir_idle_poresw_fatal_err : 1; + uint64_t lfir_ms_comp_parity_err : 1; + uint64_t lfir_pstate_ms_fsm_err : 1; + uint64_t lfir_pstate_interchip_errorframe_err : 1; + uint64_t lfir_pstate_interchip_ue_err : 1; + uint64_t lfir_pstate_oci_master_to_err : 1; + uint64_t lfir_pstate_pib_master_offline_err : 1; + uint64_t lfir_pstate_pib_master_nonoffline_err : 1; + uint64_t lfir_pstate_gack_to_err : 1; + uint64_t lfir_pstate_gpst_checkbyte_err : 1; + uint64_t lfir_pstate_oci_master_rddata_parity_err : 1; + uint64_t lfir_pstate_oci_master_rderr : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_lfir_err_reg_t; + + + +typedef union pmc_lfir_err_reg_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t lfir_pstate_oci_master_rderr : 1; + uint64_t lfir_pstate_oci_master_rddata_parity_err : 1; + uint64_t lfir_pstate_gpst_checkbyte_err : 1; + uint64_t lfir_pstate_gack_to_err : 1; + uint64_t lfir_pstate_pib_master_nonoffline_err : 1; + uint64_t lfir_pstate_pib_master_offline_err : 1; + uint64_t lfir_pstate_oci_master_to_err : 1; + uint64_t lfir_pstate_interchip_ue_err : 1; + uint64_t lfir_pstate_interchip_errorframe_err : 1; + uint64_t lfir_pstate_ms_fsm_err : 1; + uint64_t lfir_ms_comp_parity_err : 1; + uint64_t lfir_idle_poresw_fatal_err : 1; + uint64_t lfir_idle_poresw_status_rc_err : 1; + uint64_t lfir_idle_poresw_status_value_err : 1; + uint64_t lfir_idle_poresw_write_while_inactive_err : 1; + uint64_t lfir_idle_poresw_timeout_err : 1; + uint64_t lfir_idle_oci_master_write_timeout_err : 1; + uint64_t lfir_idle_internal_err : 1; + uint64_t lfir_int_comp_parity_err : 1; + uint64_t lfir_pmc_occ_heartbeat_timeout : 1; + uint64_t lfir_spivid_crc_error0 : 1; + uint64_t lfir_spivid_crc_error1 : 1; + uint64_t lfir_spivid_crc_error2 : 1; + uint64_t lfir_spivid_retry_timeout : 1; + uint64_t lfir_spivid_fsm_err : 1; + uint64_t lfir_spivid_majority_detected_a_minority : 1; + uint64_t lfir_o2s_crc_error0 : 1; + uint64_t lfir_o2s_crc_error1 : 1; + uint64_t lfir_o2s_crc_error2 : 1; + uint64_t lfir_o2s_retry_timeout : 1; + uint64_t lfir_o2s_write_while_bridge_busy_err : 1; + uint64_t lfir_o2s_fsm_err : 1; + uint64_t lfir_o2s_majority_detected_a_minority : 1; + uint64_t lfir_o2p_write_while_bridge_busy_err : 1; + uint64_t lfir_o2p_fsm_err : 1; + uint64_t lfir_oci_slave_err : 1; + uint64_t lfir_if_comp_parity_error : 1; + uint64_t spare_fir : 10; + uint64_t fir_parity_err_dup : 1; + uint64_t fir_parity_err : 1; + uint64_t _reserved0 : 15; +#else + uint64_t _reserved0 : 15; + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err_dup : 1; + uint64_t spare_fir : 10; + uint64_t lfir_if_comp_parity_error : 1; + uint64_t lfir_oci_slave_err : 1; + uint64_t lfir_o2p_fsm_err : 1; + uint64_t lfir_o2p_write_while_bridge_busy_err : 1; + uint64_t lfir_o2s_majority_detected_a_minority : 1; + uint64_t lfir_o2s_fsm_err : 1; + uint64_t lfir_o2s_write_while_bridge_busy_err : 1; + uint64_t lfir_o2s_retry_timeout : 1; + uint64_t lfir_o2s_crc_error2 : 1; + uint64_t lfir_o2s_crc_error1 : 1; + uint64_t lfir_o2s_crc_error0 : 1; + uint64_t lfir_spivid_majority_detected_a_minority : 1; + uint64_t lfir_spivid_fsm_err : 1; + uint64_t lfir_spivid_retry_timeout : 1; + uint64_t lfir_spivid_crc_error2 : 1; + uint64_t lfir_spivid_crc_error1 : 1; + uint64_t lfir_spivid_crc_error0 : 1; + uint64_t lfir_pmc_occ_heartbeat_timeout : 1; + uint64_t lfir_int_comp_parity_err : 1; + uint64_t lfir_idle_internal_err : 1; + uint64_t lfir_idle_oci_master_write_timeout_err : 1; + uint64_t lfir_idle_poresw_timeout_err : 1; + uint64_t lfir_idle_poresw_write_while_inactive_err : 1; + uint64_t lfir_idle_poresw_status_value_err : 1; + uint64_t lfir_idle_poresw_status_rc_err : 1; + uint64_t lfir_idle_poresw_fatal_err : 1; + uint64_t lfir_ms_comp_parity_err : 1; + uint64_t lfir_pstate_ms_fsm_err : 1; + uint64_t lfir_pstate_interchip_errorframe_err : 1; + uint64_t lfir_pstate_interchip_ue_err : 1; + uint64_t lfir_pstate_oci_master_to_err : 1; + uint64_t lfir_pstate_pib_master_offline_err : 1; + uint64_t lfir_pstate_pib_master_nonoffline_err : 1; + uint64_t lfir_pstate_gack_to_err : 1; + uint64_t lfir_pstate_gpst_checkbyte_err : 1; + uint64_t lfir_pstate_oci_master_rddata_parity_err : 1; + uint64_t lfir_pstate_oci_master_rderr : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_lfir_err_reg_and_t; + + + +typedef union pmc_lfir_err_reg_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t lfir_pstate_oci_master_rderr : 1; + uint64_t lfir_pstate_oci_master_rddata_parity_err : 1; + uint64_t lfir_pstate_gpst_checkbyte_err : 1; + uint64_t lfir_pstate_gack_to_err : 1; + uint64_t lfir_pstate_pib_master_nonoffline_err : 1; + uint64_t lfir_pstate_pib_master_offline_err : 1; + uint64_t lfir_pstate_oci_master_to_err : 1; + uint64_t lfir_pstate_interchip_ue_err : 1; + uint64_t lfir_pstate_interchip_errorframe_err : 1; + uint64_t lfir_pstate_ms_fsm_err : 1; + uint64_t lfir_ms_comp_parity_err : 1; + uint64_t lfir_idle_poresw_fatal_err : 1; + uint64_t lfir_idle_poresw_status_rc_err : 1; + uint64_t lfir_idle_poresw_status_value_err : 1; + uint64_t lfir_idle_poresw_write_while_inactive_err : 1; + uint64_t lfir_idle_poresw_timeout_err : 1; + uint64_t lfir_idle_oci_master_write_timeout_err : 1; + uint64_t lfir_idle_internal_err : 1; + uint64_t lfir_int_comp_parity_err : 1; + uint64_t lfir_pmc_occ_heartbeat_timeout : 1; + uint64_t lfir_spivid_crc_error0 : 1; + uint64_t lfir_spivid_crc_error1 : 1; + uint64_t lfir_spivid_crc_error2 : 1; + uint64_t lfir_spivid_retry_timeout : 1; + uint64_t lfir_spivid_fsm_err : 1; + uint64_t lfir_spivid_majority_detected_a_minority : 1; + uint64_t lfir_o2s_crc_error0 : 1; + uint64_t lfir_o2s_crc_error1 : 1; + uint64_t lfir_o2s_crc_error2 : 1; + uint64_t lfir_o2s_retry_timeout : 1; + uint64_t lfir_o2s_write_while_bridge_busy_err : 1; + uint64_t lfir_o2s_fsm_err : 1; + uint64_t lfir_o2s_majority_detected_a_minority : 1; + uint64_t lfir_o2p_write_while_bridge_busy_err : 1; + uint64_t lfir_o2p_fsm_err : 1; + uint64_t lfir_oci_slave_err : 1; + uint64_t lfir_if_comp_parity_error : 1; + uint64_t spare_fir : 10; + uint64_t fir_parity_err_dup : 1; + uint64_t fir_parity_err : 1; + uint64_t _reserved0 : 15; +#else + uint64_t _reserved0 : 15; + uint64_t fir_parity_err : 1; + uint64_t fir_parity_err_dup : 1; + uint64_t spare_fir : 10; + uint64_t lfir_if_comp_parity_error : 1; + uint64_t lfir_oci_slave_err : 1; + uint64_t lfir_o2p_fsm_err : 1; + uint64_t lfir_o2p_write_while_bridge_busy_err : 1; + uint64_t lfir_o2s_majority_detected_a_minority : 1; + uint64_t lfir_o2s_fsm_err : 1; + uint64_t lfir_o2s_write_while_bridge_busy_err : 1; + uint64_t lfir_o2s_retry_timeout : 1; + uint64_t lfir_o2s_crc_error2 : 1; + uint64_t lfir_o2s_crc_error1 : 1; + uint64_t lfir_o2s_crc_error0 : 1; + uint64_t lfir_spivid_majority_detected_a_minority : 1; + uint64_t lfir_spivid_fsm_err : 1; + uint64_t lfir_spivid_retry_timeout : 1; + uint64_t lfir_spivid_crc_error2 : 1; + uint64_t lfir_spivid_crc_error1 : 1; + uint64_t lfir_spivid_crc_error0 : 1; + uint64_t lfir_pmc_occ_heartbeat_timeout : 1; + uint64_t lfir_int_comp_parity_err : 1; + uint64_t lfir_idle_internal_err : 1; + uint64_t lfir_idle_oci_master_write_timeout_err : 1; + uint64_t lfir_idle_poresw_timeout_err : 1; + uint64_t lfir_idle_poresw_write_while_inactive_err : 1; + uint64_t lfir_idle_poresw_status_value_err : 1; + uint64_t lfir_idle_poresw_status_rc_err : 1; + uint64_t lfir_idle_poresw_fatal_err : 1; + uint64_t lfir_ms_comp_parity_err : 1; + uint64_t lfir_pstate_ms_fsm_err : 1; + uint64_t lfir_pstate_interchip_errorframe_err : 1; + uint64_t lfir_pstate_interchip_ue_err : 1; + uint64_t lfir_pstate_oci_master_to_err : 1; + uint64_t lfir_pstate_pib_master_offline_err : 1; + uint64_t lfir_pstate_pib_master_nonoffline_err : 1; + uint64_t lfir_pstate_gack_to_err : 1; + uint64_t lfir_pstate_gpst_checkbyte_err : 1; + uint64_t lfir_pstate_oci_master_rddata_parity_err : 1; + uint64_t lfir_pstate_oci_master_rderr : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_lfir_err_reg_or_t; + + + +typedef union pmc_lfir_err_mask_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pmc_lfir_mask_0 : 1; + uint64_t pmc_lfir_mask_1 : 1; + uint64_t pmc_lfir_mask_2 : 1; + uint64_t pmc_lfir_mask_3 : 1; + uint64_t pmc_lfir_mask_4 : 1; + uint64_t pmc_lfir_mask_5 : 1; + uint64_t pmc_lfir_mask_6 : 1; + uint64_t pmc_lfir_mask_7 : 1; + uint64_t pmc_lfir_mask_8 : 1; + uint64_t pmc_lfir_mask_9 : 1; + uint64_t pmc_lfir_mask_10 : 1; + uint64_t pmc_lfir_mask_11 : 1; + uint64_t pmc_lfir_mask_12 : 1; + uint64_t pmc_lfir_mask_13 : 1; + uint64_t pmc_lfir_mask_14 : 1; + uint64_t pmc_lfir_mask_15 : 1; + uint64_t pmc_lfir_mask_16 : 1; + uint64_t pmc_lfir_mask_17 : 1; + uint64_t pmc_lfir_mask_18 : 1; + uint64_t pmc_lfir_mask_19 : 1; + uint64_t pmc_lfir_mask_20 : 1; + uint64_t pmc_lfir_mask_21 : 1; + uint64_t pmc_lfir_mask_22 : 1; + uint64_t pmc_lfir_mask_23 : 1; + uint64_t pmc_lfir_mask_24 : 1; + uint64_t pmc_lfir_mask_25 : 1; + uint64_t pmc_lfir_mask_26 : 1; + uint64_t pmc_lfir_mask_27 : 1; + uint64_t pmc_lfir_mask_28 : 1; + uint64_t pmc_lfir_mask_29 : 1; + uint64_t pmc_lfir_mask_30 : 1; + uint64_t pmc_lfir_mask_31 : 1; + uint64_t pmc_lfir_mask_32 : 1; + uint64_t pmc_lfir_mask_33 : 1; + uint64_t pmc_lfir_mask_34 : 1; + uint64_t pmc_lfir_mask_35 : 1; + uint64_t pmc_lfir_mask_36 : 1; + uint64_t pmc_lfir_mask1_37_46 : 10; + uint64_t pmc_lfir_mask1_47 : 1; + uint64_t pmc_lfir_mask1_48 : 1; + uint64_t _reserved0 : 15; +#else + uint64_t _reserved0 : 15; + uint64_t pmc_lfir_mask1_48 : 1; + uint64_t pmc_lfir_mask1_47 : 1; + uint64_t pmc_lfir_mask1_37_46 : 10; + uint64_t pmc_lfir_mask_36 : 1; + uint64_t pmc_lfir_mask_35 : 1; + uint64_t pmc_lfir_mask_34 : 1; + uint64_t pmc_lfir_mask_33 : 1; + uint64_t pmc_lfir_mask_32 : 1; + uint64_t pmc_lfir_mask_31 : 1; + uint64_t pmc_lfir_mask_30 : 1; + uint64_t pmc_lfir_mask_29 : 1; + uint64_t pmc_lfir_mask_28 : 1; + uint64_t pmc_lfir_mask_27 : 1; + uint64_t pmc_lfir_mask_26 : 1; + uint64_t pmc_lfir_mask_25 : 1; + uint64_t pmc_lfir_mask_24 : 1; + uint64_t pmc_lfir_mask_23 : 1; + uint64_t pmc_lfir_mask_22 : 1; + uint64_t pmc_lfir_mask_21 : 1; + uint64_t pmc_lfir_mask_20 : 1; + uint64_t pmc_lfir_mask_19 : 1; + uint64_t pmc_lfir_mask_18 : 1; + uint64_t pmc_lfir_mask_17 : 1; + uint64_t pmc_lfir_mask_16 : 1; + uint64_t pmc_lfir_mask_15 : 1; + uint64_t pmc_lfir_mask_14 : 1; + uint64_t pmc_lfir_mask_13 : 1; + uint64_t pmc_lfir_mask_12 : 1; + uint64_t pmc_lfir_mask_11 : 1; + uint64_t pmc_lfir_mask_10 : 1; + uint64_t pmc_lfir_mask_9 : 1; + uint64_t pmc_lfir_mask_8 : 1; + uint64_t pmc_lfir_mask_7 : 1; + uint64_t pmc_lfir_mask_6 : 1; + uint64_t pmc_lfir_mask_5 : 1; + uint64_t pmc_lfir_mask_4 : 1; + uint64_t pmc_lfir_mask_3 : 1; + uint64_t pmc_lfir_mask_2 : 1; + uint64_t pmc_lfir_mask_1 : 1; + uint64_t pmc_lfir_mask_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_lfir_err_mask_reg_t; + + + +typedef union pmc_lfir_err_mask_reg_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pmc_lfir_mask_0 : 1; + uint64_t pmc_lfir_mask_1 : 1; + uint64_t pmc_lfir_mask_2 : 1; + uint64_t pmc_lfir_mask_3 : 1; + uint64_t pmc_lfir_mask_4 : 1; + uint64_t pmc_lfir_mask_5 : 1; + uint64_t pmc_lfir_mask_6 : 1; + uint64_t pmc_lfir_mask_7 : 1; + uint64_t pmc_lfir_mask_8 : 1; + uint64_t pmc_lfir_mask_9 : 1; + uint64_t pmc_lfir_mask_10 : 1; + uint64_t pmc_lfir_mask_11 : 1; + uint64_t pmc_lfir_mask_12 : 1; + uint64_t pmc_lfir_mask_13 : 1; + uint64_t pmc_lfir_mask_14 : 1; + uint64_t pmc_lfir_mask_15 : 1; + uint64_t pmc_lfir_mask_16 : 1; + uint64_t pmc_lfir_mask_17 : 1; + uint64_t pmc_lfir_mask_18 : 1; + uint64_t pmc_lfir_mask_19 : 1; + uint64_t pmc_lfir_mask_20 : 1; + uint64_t pmc_lfir_mask_21 : 1; + uint64_t pmc_lfir_mask_22 : 1; + uint64_t pmc_lfir_mask_23 : 1; + uint64_t pmc_lfir_mask_24 : 1; + uint64_t pmc_lfir_mask_25 : 1; + uint64_t pmc_lfir_mask_26 : 1; + uint64_t pmc_lfir_mask_27 : 1; + uint64_t pmc_lfir_mask_28 : 1; + uint64_t pmc_lfir_mask_29 : 1; + uint64_t pmc_lfir_mask_30 : 1; + uint64_t pmc_lfir_mask_31 : 1; + uint64_t pmc_lfir_mask_32 : 1; + uint64_t pmc_lfir_mask_33 : 1; + uint64_t pmc_lfir_mask_34 : 1; + uint64_t pmc_lfir_mask_35 : 1; + uint64_t pmc_lfir_mask_36 : 1; + uint64_t pmc_lfir_mask1_37_46 : 10; + uint64_t pmc_lfir_mask1_47 : 1; + uint64_t pmc_lfir_mask1_48 : 1; + uint64_t _reserved0 : 15; +#else + uint64_t _reserved0 : 15; + uint64_t pmc_lfir_mask1_48 : 1; + uint64_t pmc_lfir_mask1_47 : 1; + uint64_t pmc_lfir_mask1_37_46 : 10; + uint64_t pmc_lfir_mask_36 : 1; + uint64_t pmc_lfir_mask_35 : 1; + uint64_t pmc_lfir_mask_34 : 1; + uint64_t pmc_lfir_mask_33 : 1; + uint64_t pmc_lfir_mask_32 : 1; + uint64_t pmc_lfir_mask_31 : 1; + uint64_t pmc_lfir_mask_30 : 1; + uint64_t pmc_lfir_mask_29 : 1; + uint64_t pmc_lfir_mask_28 : 1; + uint64_t pmc_lfir_mask_27 : 1; + uint64_t pmc_lfir_mask_26 : 1; + uint64_t pmc_lfir_mask_25 : 1; + uint64_t pmc_lfir_mask_24 : 1; + uint64_t pmc_lfir_mask_23 : 1; + uint64_t pmc_lfir_mask_22 : 1; + uint64_t pmc_lfir_mask_21 : 1; + uint64_t pmc_lfir_mask_20 : 1; + uint64_t pmc_lfir_mask_19 : 1; + uint64_t pmc_lfir_mask_18 : 1; + uint64_t pmc_lfir_mask_17 : 1; + uint64_t pmc_lfir_mask_16 : 1; + uint64_t pmc_lfir_mask_15 : 1; + uint64_t pmc_lfir_mask_14 : 1; + uint64_t pmc_lfir_mask_13 : 1; + uint64_t pmc_lfir_mask_12 : 1; + uint64_t pmc_lfir_mask_11 : 1; + uint64_t pmc_lfir_mask_10 : 1; + uint64_t pmc_lfir_mask_9 : 1; + uint64_t pmc_lfir_mask_8 : 1; + uint64_t pmc_lfir_mask_7 : 1; + uint64_t pmc_lfir_mask_6 : 1; + uint64_t pmc_lfir_mask_5 : 1; + uint64_t pmc_lfir_mask_4 : 1; + uint64_t pmc_lfir_mask_3 : 1; + uint64_t pmc_lfir_mask_2 : 1; + uint64_t pmc_lfir_mask_1 : 1; + uint64_t pmc_lfir_mask_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_lfir_err_mask_reg_and_t; + + + +typedef union pmc_lfir_err_mask_reg_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pmc_lfir_mask_0 : 1; + uint64_t pmc_lfir_mask_1 : 1; + uint64_t pmc_lfir_mask_2 : 1; + uint64_t pmc_lfir_mask_3 : 1; + uint64_t pmc_lfir_mask_4 : 1; + uint64_t pmc_lfir_mask_5 : 1; + uint64_t pmc_lfir_mask_6 : 1; + uint64_t pmc_lfir_mask_7 : 1; + uint64_t pmc_lfir_mask_8 : 1; + uint64_t pmc_lfir_mask_9 : 1; + uint64_t pmc_lfir_mask_10 : 1; + uint64_t pmc_lfir_mask_11 : 1; + uint64_t pmc_lfir_mask_12 : 1; + uint64_t pmc_lfir_mask_13 : 1; + uint64_t pmc_lfir_mask_14 : 1; + uint64_t pmc_lfir_mask_15 : 1; + uint64_t pmc_lfir_mask_16 : 1; + uint64_t pmc_lfir_mask_17 : 1; + uint64_t pmc_lfir_mask_18 : 1; + uint64_t pmc_lfir_mask_19 : 1; + uint64_t pmc_lfir_mask_20 : 1; + uint64_t pmc_lfir_mask_21 : 1; + uint64_t pmc_lfir_mask_22 : 1; + uint64_t pmc_lfir_mask_23 : 1; + uint64_t pmc_lfir_mask_24 : 1; + uint64_t pmc_lfir_mask_25 : 1; + uint64_t pmc_lfir_mask_26 : 1; + uint64_t pmc_lfir_mask_27 : 1; + uint64_t pmc_lfir_mask_28 : 1; + uint64_t pmc_lfir_mask_29 : 1; + uint64_t pmc_lfir_mask_30 : 1; + uint64_t pmc_lfir_mask_31 : 1; + uint64_t pmc_lfir_mask_32 : 1; + uint64_t pmc_lfir_mask_33 : 1; + uint64_t pmc_lfir_mask_34 : 1; + uint64_t pmc_lfir_mask_35 : 1; + uint64_t pmc_lfir_mask_36 : 1; + uint64_t pmc_lfir_mask1_37_46 : 10; + uint64_t pmc_lfir_mask1_47 : 1; + uint64_t pmc_lfir_mask1_48 : 1; + uint64_t _reserved0 : 15; +#else + uint64_t _reserved0 : 15; + uint64_t pmc_lfir_mask1_48 : 1; + uint64_t pmc_lfir_mask1_47 : 1; + uint64_t pmc_lfir_mask1_37_46 : 10; + uint64_t pmc_lfir_mask_36 : 1; + uint64_t pmc_lfir_mask_35 : 1; + uint64_t pmc_lfir_mask_34 : 1; + uint64_t pmc_lfir_mask_33 : 1; + uint64_t pmc_lfir_mask_32 : 1; + uint64_t pmc_lfir_mask_31 : 1; + uint64_t pmc_lfir_mask_30 : 1; + uint64_t pmc_lfir_mask_29 : 1; + uint64_t pmc_lfir_mask_28 : 1; + uint64_t pmc_lfir_mask_27 : 1; + uint64_t pmc_lfir_mask_26 : 1; + uint64_t pmc_lfir_mask_25 : 1; + uint64_t pmc_lfir_mask_24 : 1; + uint64_t pmc_lfir_mask_23 : 1; + uint64_t pmc_lfir_mask_22 : 1; + uint64_t pmc_lfir_mask_21 : 1; + uint64_t pmc_lfir_mask_20 : 1; + uint64_t pmc_lfir_mask_19 : 1; + uint64_t pmc_lfir_mask_18 : 1; + uint64_t pmc_lfir_mask_17 : 1; + uint64_t pmc_lfir_mask_16 : 1; + uint64_t pmc_lfir_mask_15 : 1; + uint64_t pmc_lfir_mask_14 : 1; + uint64_t pmc_lfir_mask_13 : 1; + uint64_t pmc_lfir_mask_12 : 1; + uint64_t pmc_lfir_mask_11 : 1; + uint64_t pmc_lfir_mask_10 : 1; + uint64_t pmc_lfir_mask_9 : 1; + uint64_t pmc_lfir_mask_8 : 1; + uint64_t pmc_lfir_mask_7 : 1; + uint64_t pmc_lfir_mask_6 : 1; + uint64_t pmc_lfir_mask_5 : 1; + uint64_t pmc_lfir_mask_4 : 1; + uint64_t pmc_lfir_mask_3 : 1; + uint64_t pmc_lfir_mask_2 : 1; + uint64_t pmc_lfir_mask_1 : 1; + uint64_t pmc_lfir_mask_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_lfir_err_mask_reg_or_t; + + + +typedef union pmc_lfir_action0_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pmc_lfir_action0_0 : 1; + uint64_t pmc_lfir_action0_1 : 1; + uint64_t pmc_lfir_action0_2 : 1; + uint64_t pmc_lfir_action0_3 : 1; + uint64_t pmc_lfir_action0_4 : 1; + uint64_t pmc_lfir_action0_5 : 1; + uint64_t pmc_lfir_action0_6 : 1; + uint64_t pmc_lfir_action0_7 : 1; + uint64_t pmc_lfir_action0_8 : 1; + uint64_t pmc_lfir_action0_9 : 1; + uint64_t pmc_lfir_action0_10 : 1; + uint64_t pmc_lfir_action0_11 : 1; + uint64_t pmc_lfir_action0_12 : 1; + uint64_t pmc_lfir_action0_13 : 1; + uint64_t pmc_lfir_action0_14 : 1; + uint64_t pmc_lfir_action0_15 : 1; + uint64_t pmc_lfir_action0_16 : 1; + uint64_t pmc_lfir_action0_17 : 1; + uint64_t pmc_lfir_action0_18 : 1; + uint64_t pmc_lfir_action0_19 : 1; + uint64_t pmc_lfir_action0_20 : 1; + uint64_t pmc_lfir_action0_21 : 1; + uint64_t pmc_lfir_action0_22 : 1; + uint64_t pmc_lfir_action0_23 : 1; + uint64_t pmc_lfir_action0_24 : 1; + uint64_t pmc_lfir_action0_25 : 1; + uint64_t pmc_lfir_action0_26 : 1; + uint64_t pmc_lfir_action0_27 : 1; + uint64_t pmc_lfir_action0_28 : 1; + uint64_t pmc_lfir_action0_29 : 1; + uint64_t pmc_lfir_action0_30 : 1; + uint64_t pmc_lfir_action0_31 : 1; + uint64_t pmc_lfir_action0_32 : 1; + uint64_t pmc_lfir_action0_33 : 1; + uint64_t pmc_lfir_action0_34 : 1; + uint64_t pmc_lfir_action0_35 : 1; + uint64_t pmc_lfir_action0_36 : 1; + uint64_t pmc_lfir_action0_37_46 : 10; + uint64_t pmc_lfir_action0_47 : 1; + uint64_t pmc_lfir_action0_48 : 1; + uint64_t _reserved0 : 15; +#else + uint64_t _reserved0 : 15; + uint64_t pmc_lfir_action0_48 : 1; + uint64_t pmc_lfir_action0_47 : 1; + uint64_t pmc_lfir_action0_37_46 : 10; + uint64_t pmc_lfir_action0_36 : 1; + uint64_t pmc_lfir_action0_35 : 1; + uint64_t pmc_lfir_action0_34 : 1; + uint64_t pmc_lfir_action0_33 : 1; + uint64_t pmc_lfir_action0_32 : 1; + uint64_t pmc_lfir_action0_31 : 1; + uint64_t pmc_lfir_action0_30 : 1; + uint64_t pmc_lfir_action0_29 : 1; + uint64_t pmc_lfir_action0_28 : 1; + uint64_t pmc_lfir_action0_27 : 1; + uint64_t pmc_lfir_action0_26 : 1; + uint64_t pmc_lfir_action0_25 : 1; + uint64_t pmc_lfir_action0_24 : 1; + uint64_t pmc_lfir_action0_23 : 1; + uint64_t pmc_lfir_action0_22 : 1; + uint64_t pmc_lfir_action0_21 : 1; + uint64_t pmc_lfir_action0_20 : 1; + uint64_t pmc_lfir_action0_19 : 1; + uint64_t pmc_lfir_action0_18 : 1; + uint64_t pmc_lfir_action0_17 : 1; + uint64_t pmc_lfir_action0_16 : 1; + uint64_t pmc_lfir_action0_15 : 1; + uint64_t pmc_lfir_action0_14 : 1; + uint64_t pmc_lfir_action0_13 : 1; + uint64_t pmc_lfir_action0_12 : 1; + uint64_t pmc_lfir_action0_11 : 1; + uint64_t pmc_lfir_action0_10 : 1; + uint64_t pmc_lfir_action0_9 : 1; + uint64_t pmc_lfir_action0_8 : 1; + uint64_t pmc_lfir_action0_7 : 1; + uint64_t pmc_lfir_action0_6 : 1; + uint64_t pmc_lfir_action0_5 : 1; + uint64_t pmc_lfir_action0_4 : 1; + uint64_t pmc_lfir_action0_3 : 1; + uint64_t pmc_lfir_action0_2 : 1; + uint64_t pmc_lfir_action0_1 : 1; + uint64_t pmc_lfir_action0_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_lfir_action0_reg_t; + + + +typedef union pmc_lfir_action1_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pmc_lfir_action1_0 : 1; + uint64_t pmc_lfir_action1_1 : 1; + uint64_t pmc_lfir_action1_2 : 1; + uint64_t pmc_lfir_action1_3 : 1; + uint64_t pmc_lfir_action1_4 : 1; + uint64_t pmc_lfir_action1_5 : 1; + uint64_t pmc_lfir_action1_6 : 1; + uint64_t pmc_lfir_action1_7 : 1; + uint64_t pmc_lfir_action1_8 : 1; + uint64_t pmc_lfir_action1_9 : 1; + uint64_t pmc_lfir_action1_10 : 1; + uint64_t pmc_lfir_action1_11 : 1; + uint64_t pmc_lfir_action1_12 : 1; + uint64_t pmc_lfir_action1_13 : 1; + uint64_t pmc_lfir_action1_14 : 1; + uint64_t pmc_lfir_action1_15 : 1; + uint64_t pmc_lfir_action1_16 : 1; + uint64_t pmc_lfir_action1_17 : 1; + uint64_t pmc_lfir_action1_18 : 1; + uint64_t pmc_lfir_action1_19 : 1; + uint64_t pmc_lfir_action1_20 : 1; + uint64_t pmc_lfir_action1_21 : 1; + uint64_t pmc_lfir_action1_22 : 1; + uint64_t pmc_lfir_action1_23 : 1; + uint64_t pmc_lfir_action1_24 : 1; + uint64_t pmc_lfir_action1_25 : 1; + uint64_t pmc_lfir_action1_26 : 1; + uint64_t pmc_lfir_action1_27 : 1; + uint64_t pmc_lfir_action1_28 : 1; + uint64_t pmc_lfir_action1_29 : 1; + uint64_t pmc_lfir_action1_30 : 1; + uint64_t pmc_lfir_action1_31 : 1; + uint64_t pmc_lfir_action1_32 : 1; + uint64_t pmc_lfir_action1_33 : 1; + uint64_t pmc_lfir_action1_34 : 1; + uint64_t pmc_lfir_action1_35 : 1; + uint64_t pmc_lfir_action1_36 : 1; + uint64_t pmc_lfir_action1_37_46 : 10; + uint64_t pmc_lfir_action1_47 : 1; + uint64_t pmc_lfir_action1_48 : 1; + uint64_t _reserved0 : 15; +#else + uint64_t _reserved0 : 15; + uint64_t pmc_lfir_action1_48 : 1; + uint64_t pmc_lfir_action1_47 : 1; + uint64_t pmc_lfir_action1_37_46 : 10; + uint64_t pmc_lfir_action1_36 : 1; + uint64_t pmc_lfir_action1_35 : 1; + uint64_t pmc_lfir_action1_34 : 1; + uint64_t pmc_lfir_action1_33 : 1; + uint64_t pmc_lfir_action1_32 : 1; + uint64_t pmc_lfir_action1_31 : 1; + uint64_t pmc_lfir_action1_30 : 1; + uint64_t pmc_lfir_action1_29 : 1; + uint64_t pmc_lfir_action1_28 : 1; + uint64_t pmc_lfir_action1_27 : 1; + uint64_t pmc_lfir_action1_26 : 1; + uint64_t pmc_lfir_action1_25 : 1; + uint64_t pmc_lfir_action1_24 : 1; + uint64_t pmc_lfir_action1_23 : 1; + uint64_t pmc_lfir_action1_22 : 1; + uint64_t pmc_lfir_action1_21 : 1; + uint64_t pmc_lfir_action1_20 : 1; + uint64_t pmc_lfir_action1_19 : 1; + uint64_t pmc_lfir_action1_18 : 1; + uint64_t pmc_lfir_action1_17 : 1; + uint64_t pmc_lfir_action1_16 : 1; + uint64_t pmc_lfir_action1_15 : 1; + uint64_t pmc_lfir_action1_14 : 1; + uint64_t pmc_lfir_action1_13 : 1; + uint64_t pmc_lfir_action1_12 : 1; + uint64_t pmc_lfir_action1_11 : 1; + uint64_t pmc_lfir_action1_10 : 1; + uint64_t pmc_lfir_action1_9 : 1; + uint64_t pmc_lfir_action1_8 : 1; + uint64_t pmc_lfir_action1_7 : 1; + uint64_t pmc_lfir_action1_6 : 1; + uint64_t pmc_lfir_action1_5 : 1; + uint64_t pmc_lfir_action1_4 : 1; + uint64_t pmc_lfir_action1_3 : 1; + uint64_t pmc_lfir_action1_2 : 1; + uint64_t pmc_lfir_action1_1 : 1; + uint64_t pmc_lfir_action1_0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pmc_lfir_action1_reg_t; + + + +typedef union pmc_lfir_wof_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pmc_lfir_wof : 49; + uint64_t _reserved0 : 15; +#else + uint64_t _reserved0 : 15; + uint64_t pmc_lfir_wof : 49; +#endif // _BIG_ENDIAN + } fields; +} pmc_lfir_wof_reg_t; + + +#endif // __ASSEMBLER__ +#endif // __PMC_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/pmc_register_addresses.h b/src/ssx/pgp/registers/pmc_register_addresses.h new file mode 100755 index 0000000..96f8dac --- /dev/null +++ b/src/ssx/pgp/registers/pmc_register_addresses.h @@ -0,0 +1,116 @@ +#ifndef __PMC_REGISTER_ADDRESSES_H__ +#define __PMC_REGISTER_ADDRESSES_H__ + +// $Id: pmc_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pmc_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file pmc_register_addresses.h +/// \brief Symbolic addresses for the PMC unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define PMC_OCI_BASE 0x40010000 +#define PMC_MODE_REG 0x40010000 +#define PMC_HARDWARE_AUCTION_PSTATE_REG 0x40010008 +#define PMC_PSTATE_MONITOR_AND_CTRL_REG 0x40010010 +#define PMC_RAIL_BOUNDS_REGISTER 0x40010018 +#define PMC_GLOBAL_PSTATE_BOUNDS_REG 0x40010020 +#define PMC_PARAMETER_REG0 0x40010028 +#define PMC_PARAMETER_REG1 0x40010030 +#define PMC_EFF_GLOBAL_ACTUAL_VOLTAGE_REG 0x40010038 +#define PMC_GLOBAL_ACTUAL_VOLTAGE_REG 0x40010040 +#define PMC_STATUS_REG 0x40010048 +#define PMC_PHASE_ENABLE_REG 0x40010050 +#define PMC_UNDERVOLTING_REG 0x40010060 +#define PMC_CORE_DECONFIGURATION_REG 0x40010068 +#define PMC_INTCHP_CTRL_REG1 0x40010080 +#define PMC_INTCHP_CTRL_REG2 0x40010088 +#define PMC_INTCHP_CTRL_REG4 0x40010090 +#define PMC_INTCHP_STATUS_REG 0x40010098 +#define PMC_INTCHP_COMMAND_REG 0x400100a0 +#define PMC_INTCHP_MSG_WDATA 0x400100a8 +#define PMC_INTCHP_MSG_RDATA 0x400100b0 +#define PMC_INTCHP_PSTATE_REG 0x400100b8 +#define PMC_INTCHP_GLOBACK_REG 0x400100c0 +#define PMC_FSMSTATE_STATUS_REG 0x40010100 +#define PMC_TRACE_MODE_REG 0x40010180 +#define PMC_SPIV_CTRL_REG0A 0x40010200 +#define PMC_SPIV_CTRL_REG0B 0x40010208 +#define PMC_SPIV_CTRL_REG1 0x40010210 +#define PMC_SPIV_CTRL_REG2 0x40010218 +#define PMC_SPIV_CTRL_REG3 0x40010220 +#define PMC_SPIV_CTRL_REG4 0x40010228 +#define PMC_SPIV_STATUS_REG 0x40010230 +#define PMC_SPIV_COMMAND_REG 0x40010238 +#define PMC_O2S_CTRL_REG0A 0x40010280 +#define PMC_O2S_CTRL_REG0B 0x40010288 +#define PMC_O2S_CTRL_REG1 0x40010290 +#define PMC_O2S_CTRL_REG2 0x40010298 +#define PMC_O2S_CTRL_REG4 0x400102a8 +#define PMC_O2S_STATUS_REG 0x400102b0 +#define PMC_O2S_COMMAND_REG 0x400102b8 +#define PMC_O2S_WDATA_REG 0x400102c0 +#define PMC_O2S_RDATA_REG 0x400102c8 +#define PMC_O2P_ADDR_REG 0x40010300 +#define PMC_O2P_CTRL_STATUS_REG 0x40010308 +#define PMC_O2P_SEND_DATA_HI_REG 0x40010310 +#define PMC_O2P_SEND_DATA_LO_REG 0x40010318 +#define PMC_O2P_RECV_DATA_HI_REG 0x40010320 +#define PMC_O2P_RECV_DATA_LO_REG 0x40010328 +#define PMC_OCC_HEARTBEAT_REG 0x40010330 +#define PMC_ERROR_INT_MASK_HI_REG 0x40010338 +#define PMC_ERROR_INT_MASK_LO_REG 0x40010340 +#define PMC_IDLE_SUSPEND_MASK_REG 0x40010348 +#define PMC_PEND_IDLE_REQ_REG0 0x40010400 +#define PMC_PEND_IDLE_REQ_REG1 0x40010408 +#define PMC_PEND_IDLE_REQ_REG2 0x40010410 +#define PMC_PEND_IDLE_REQ_REG3 0x40010418 +#define PMC_SLEEP_INT_REQ_VEC_REG0 0x40010420 +#define PMC_SLEEP_INT_REQ_VEC_REG1 0x40010428 +#define PMC_SLEEP_INT_REQ_VEC_REG2 0x40010430 +#define PMC_SLEEP_INT_REQ_VEC_REG3 0x40010438 +#define PMC_WINKLE_INT_REQ_VEC_REG0 0x40010440 +#define PMC_WINKLE_INT_REQ_VEC_REG1 0x40010448 +#define PMC_WINKLE_INT_REQ_VEC_REG2 0x40010450 +#define PMC_WINKLE_INT_REQ_VEC_REG3 0x40010458 +#define PMC_NAP_INT_REQ_VEC_REG0 0x40010460 +#define PMC_NAP_INT_REQ_VEC_REG1 0x40010468 +#define PMC_PORE_REQ_REG0 0x40010470 +#define PMC_PORE_REQ_REG1 0x40010478 +#define PMC_PORE_REQ_STAT_REG 0x40010480 +#define PMC_PORE_REQ_TOUT_TH_REG 0x40010488 +#define PMC_DEEP_EXIT_MASK_REG 0x40010490 +#define PMC_DEEP_EXIT_MASK_REG_AND 0x40010500 +#define PMC_DEEP_EXIT_MASK_REG_OR 0x40010508 +#define PMC_CORE_PSTATE_REG0 0x400104a0 +#define PMC_CORE_PSTATE_REG1 0x400104a8 +#define PMC_CORE_PSTATE_REG2 0x400104b0 +#define PMC_CORE_PSTATE_REG3 0x400104b8 +#define PMC_CORE_POWER_DONATION_REG 0x400104c0 +#define PMC_PMAX_SYNC_COLLECTION_REG 0x400104c8 +#define PMC_PMAX_SYNC_COLLECTION_MASK_REG 0x400104d0 +#define PMC_GPSA_ACK_COLLECTION_REG 0x400104d8 +#define PMC_GPSA_ACK_COLLECTION_MASK_REG 0x400104e0 +#define PMC_PORE_SCRATCH_REG0 0x400104e8 +#define PMC_PORE_SCRATCH_REG1 0x400104f0 +#define PMC_DEEP_IDLE_EXIT_REG 0x400104f8 +#define PMC_DEEP_STATUS_REG 0x40010510 +#define PMC_PIB_BASE 0x01010840 +#define PMC_LFIR_ERR_REG 0x01010840 +#define PMC_LFIR_ERR_REG_AND 0x01010841 +#define PMC_LFIR_ERR_REG_OR 0x01010842 +#define PMC_LFIR_ERR_MASK_REG 0x01010843 +#define PMC_LFIR_ERR_MASK_REG_AND 0x01010844 +#define PMC_LFIR_ERR_MASK_REG_OR 0x01010845 +#define PMC_LFIR_ACTION0_REG 0x01010846 +#define PMC_LFIR_ACTION1_REG 0x01010847 +#define PMC_LFIR_WOF_REG 0x01010848 + +#endif // __PMC_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/pore_firmware_registers.h b/src/ssx/pgp/registers/pore_firmware_registers.h new file mode 100755 index 0000000..76127d9 --- /dev/null +++ b/src/ssx/pgp/registers/pore_firmware_registers.h @@ -0,0 +1,906 @@ +#ifndef __PORE_FIRMWARE_REGISTERS_H__ +#define __PORE_FIRMWARE_REGISTERS_H__ + +// $Id: pore_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pore_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file pore_firmware_registers.h +/// \brief C register structs for the PORE unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union pore_status { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t cur_state : 8; + uint64_t freeze_action : 1; + uint64_t interrupt_pending : 1; + uint64_t spare : 2; + uint64_t stack_pointer : 4; + uint64_t pc : 48; +#else + uint64_t pc : 48; + uint64_t stack_pointer : 4; + uint64_t spare : 2; + uint64_t interrupt_pending : 1; + uint64_t freeze_action : 1; + uint64_t cur_state : 8; +#endif // _BIG_ENDIAN + } fields; +} pore_status_t; + +#endif // __ASSEMBLER__ +#define PORE_STATUS_CUR_STATE_MASK SIXTYFOUR_BIT_CONSTANT(0xff00000000000000) +#define PORE_STATUS_FREEZE_ACTION SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) +#define PORE_STATUS_INTERRUPT_PENDING SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) +#define PORE_STATUS_SPARE_MASK SIXTYFOUR_BIT_CONSTANT(0x0030000000000000) +#define PORE_STATUS_STACK_POINTER_MASK SIXTYFOUR_BIT_CONSTANT(0x000f000000000000) +#define PORE_STATUS_PC_MASK SIXTYFOUR_BIT_CONSTANT(0xffffffffffffffff) +#ifndef __ASSEMBLER__ + + +typedef union pore_control { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t start_stop : 1; + uint64_t continue_step : 1; + uint64_t skip : 1; + uint64_t set_pc : 1; + uint64_t set_tp_scan_clk : 3; + uint64_t lock_exe_trig : 1; + uint64_t freeze_mask : 1; + uint64_t check_parity : 1; + uint64_t prv_parity : 1; + uint64_t trap_enable : 1; + uint64_t narrow_mode_trace : 1; + uint64_t interruptible : 1; + uint64_t pore_done_override : 1; + uint64_t interruptible_en : 1; + uint64_t pc_brk_pt : 48; +#else + uint64_t pc_brk_pt : 48; + uint64_t interruptible_en : 1; + uint64_t pore_done_override : 1; + uint64_t interruptible : 1; + uint64_t narrow_mode_trace : 1; + uint64_t trap_enable : 1; + uint64_t prv_parity : 1; + uint64_t check_parity : 1; + uint64_t freeze_mask : 1; + uint64_t lock_exe_trig : 1; + uint64_t set_tp_scan_clk : 3; + uint64_t set_pc : 1; + uint64_t skip : 1; + uint64_t continue_step : 1; + uint64_t start_stop : 1; +#endif // _BIG_ENDIAN + } fields; +} pore_control_t; + +#endif // __ASSEMBLER__ +#define PORE_CONTROL_START_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define PORE_CONTROL_CONTINUE_STEP SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#define PORE_CONTROL_SKIP SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) +#define PORE_CONTROL_SET_PC SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) +#define PORE_CONTROL_SET_TP_SCAN_CLK_MASK SIXTYFOUR_BIT_CONSTANT(0x0e00000000000000) +#define PORE_CONTROL_LOCK_EXE_TRIG SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) +#define PORE_CONTROL_FREEZE_MASK SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) +#define PORE_CONTROL_CHECK_PARITY SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) +#define PORE_CONTROL_PRV_PARITY SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) +#define PORE_CONTROL_TRAP_ENABLE SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) +#define PORE_CONTROL_NARROW_MODE_TRACE SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) +#define PORE_CONTROL_INTERRUPTIBLE SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) +#define PORE_CONTROL_PORE_DONE_OVERRIDE SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) +#define PORE_CONTROL_INTERRUPTIBLE_EN SIXTYFOUR_BIT_CONSTANT(0x0001000000000000) +#define PORE_CONTROL_PC_BRK_PT_MASK SIXTYFOUR_BIT_CONSTANT(0xffffffffffffffff) +#ifndef __ASSEMBLER__ + + +typedef union pore_reset { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t fn_reset : 1; + uint64_t oci_reset : 1; + uint64_t _reserved0 : 62; +#else + uint64_t _reserved0 : 62; + uint64_t oci_reset : 1; + uint64_t fn_reset : 1; +#endif // _BIG_ENDIAN + } fields; +} pore_reset_t; + + + +typedef union pore_error_mask { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t enable_err_handler0 : 1; + uint64_t enable_err_handler1 : 1; + uint64_t enable_err_handler2 : 1; + uint64_t enable_err_handler3 : 1; + uint64_t enable_err_handler4 : 1; + uint64_t enable_err_output0 : 1; + uint64_t enable_err_output1 : 1; + uint64_t enable_err_output2 : 1; + uint64_t enable_err_output3 : 1; + uint64_t enable_err_output4 : 1; + uint64_t enable_fatal_err_output0 : 1; + uint64_t enable_fatal_err_output1 : 1; + uint64_t enable_fatal_err_output2 : 1; + uint64_t enable_fatal_err_output3 : 1; + uint64_t enable_fatal_err_output4 : 1; + uint64_t stop_exe_on_error0 : 1; + uint64_t stop_exe_on_error1 : 1; + uint64_t stop_exe_on_error2 : 1; + uint64_t stop_exe_on_error3 : 1; + uint64_t stop_exe_on_error4 : 1; + uint64_t gate_chiplet_offline_err : 1; + uint64_t i2c_bad_status_0 : 1; + uint64_t i2c_bad_status_1 : 1; + uint64_t i2c_bad_status_2 : 1; + uint64_t i2c_bad_status_3 : 1; + uint64_t group_parity_error_0 : 1; + uint64_t group_parity_error_1 : 1; + uint64_t group_parity_error_2 : 1; + uint64_t group_parity_error_3 : 1; + uint64_t group_parity_error_4 : 1; + uint64_t _reserved0 : 34; +#else + uint64_t _reserved0 : 34; + uint64_t group_parity_error_4 : 1; + uint64_t group_parity_error_3 : 1; + uint64_t group_parity_error_2 : 1; + uint64_t group_parity_error_1 : 1; + uint64_t group_parity_error_0 : 1; + uint64_t i2c_bad_status_3 : 1; + uint64_t i2c_bad_status_2 : 1; + uint64_t i2c_bad_status_1 : 1; + uint64_t i2c_bad_status_0 : 1; + uint64_t gate_chiplet_offline_err : 1; + uint64_t stop_exe_on_error4 : 1; + uint64_t stop_exe_on_error3 : 1; + uint64_t stop_exe_on_error2 : 1; + uint64_t stop_exe_on_error1 : 1; + uint64_t stop_exe_on_error0 : 1; + uint64_t enable_fatal_err_output4 : 1; + uint64_t enable_fatal_err_output3 : 1; + uint64_t enable_fatal_err_output2 : 1; + uint64_t enable_fatal_err_output1 : 1; + uint64_t enable_fatal_err_output0 : 1; + uint64_t enable_err_output4 : 1; + uint64_t enable_err_output3 : 1; + uint64_t enable_err_output2 : 1; + uint64_t enable_err_output1 : 1; + uint64_t enable_err_output0 : 1; + uint64_t enable_err_handler4 : 1; + uint64_t enable_err_handler3 : 1; + uint64_t enable_err_handler2 : 1; + uint64_t enable_err_handler1 : 1; + uint64_t enable_err_handler0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pore_error_mask_t; + +#endif // __ASSEMBLER__ +#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER0 SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER1 SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER2 SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) +#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER3 SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) +#define PORE_ERROR_MASK_ENABLE_ERR_HANDLER4 SIXTYFOUR_BIT_CONSTANT(0x0800000000000000) +#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT0 SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) +#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT1 SIXTYFOUR_BIT_CONSTANT(0x0200000000000000) +#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT2 SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) +#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT3 SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) +#define PORE_ERROR_MASK_ENABLE_ERR_OUTPUT4 SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) +#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT0 SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) +#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT1 SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) +#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT2 SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) +#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT3 SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) +#define PORE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT4 SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) +#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR0 SIXTYFOUR_BIT_CONSTANT(0x0001000000000000) +#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR1 SIXTYFOUR_BIT_CONSTANT(0x0000800000000000) +#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR2 SIXTYFOUR_BIT_CONSTANT(0x0000400000000000) +#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR3 SIXTYFOUR_BIT_CONSTANT(0x0000200000000000) +#define PORE_ERROR_MASK_STOP_EXE_ON_ERROR4 SIXTYFOUR_BIT_CONSTANT(0x0000100000000000) +#define PORE_ERROR_MASK_GATE_CHIPLET_OFFLINE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000) +#define PORE_ERROR_MASK_I2C_BAD_STATUS_0 SIXTYFOUR_BIT_CONSTANT(0x0000040000000000) +#define PORE_ERROR_MASK_I2C_BAD_STATUS_1 SIXTYFOUR_BIT_CONSTANT(0x0000020000000000) +#define PORE_ERROR_MASK_I2C_BAD_STATUS_2 SIXTYFOUR_BIT_CONSTANT(0x0000010000000000) +#define PORE_ERROR_MASK_I2C_BAD_STATUS_3 SIXTYFOUR_BIT_CONSTANT(0x0000008000000000) +#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_0 SIXTYFOUR_BIT_CONSTANT(0x0000004000000000) +#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_1 SIXTYFOUR_BIT_CONSTANT(0x0000002000000000) +#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_2 SIXTYFOUR_BIT_CONSTANT(0x0000001000000000) +#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_3 SIXTYFOUR_BIT_CONSTANT(0x0000000800000000) +#define PORE_ERROR_MASK_GROUP_PARITY_ERROR_4 SIXTYFOUR_BIT_CONSTANT(0x0000000400000000) +#ifndef __ASSEMBLER__ + + +typedef union pore_prv_base_address0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t spare : 25; + uint64_t mc : 1; + uint64_t chiplet_id : 6; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t chiplet_id : 6; + uint64_t mc : 1; + uint64_t spare : 25; +#endif // _BIG_ENDIAN + } fields; +} pore_prv_base_address0_t; + + + +typedef union pore_prv_base_address1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t spare : 25; + uint64_t mc : 1; + uint64_t chiplet_id : 6; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t chiplet_id : 6; + uint64_t mc : 1; + uint64_t spare : 25; +#endif // _BIG_ENDIAN + } fields; +} pore_prv_base_address1_t; + + + +typedef union pore_oci_base_address0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t spare : 18; + uint64_t oci_mem_route : 14; + uint64_t oci_base_address : 32; +#else + uint64_t oci_base_address : 32; + uint64_t oci_mem_route : 14; + uint64_t spare : 18; +#endif // _BIG_ENDIAN + } fields; +} pore_oci_base_address0_t; + + + +typedef union pore_oci_base_address1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t spare : 18; + uint64_t oci_mem_route : 14; + uint64_t oci_base_address : 32; +#else + uint64_t oci_base_address : 32; + uint64_t oci_mem_route : 14; + uint64_t spare : 18; +#endif // _BIG_ENDIAN + } fields; +} pore_oci_base_address1_t; + + + +typedef union pore_table_base_addr { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved : 16; + uint64_t memory_space : 16; + uint64_t table_base_address : 32; +#else + uint64_t table_base_address : 32; + uint64_t memory_space : 16; + uint64_t reserved : 16; +#endif // _BIG_ENDIAN + } fields; +} pore_table_base_addr_t; + + + +typedef union pore_exe_trigger { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved : 8; + uint64_t start_vector : 4; + uint64_t zeroes : 8; + uint64_t unused : 12; + uint64_t mc_chiplet_select_mask : 32; +#else + uint64_t mc_chiplet_select_mask : 32; + uint64_t unused : 12; + uint64_t zeroes : 8; + uint64_t start_vector : 4; + uint64_t reserved : 8; +#endif // _BIG_ENDIAN + } fields; +} pore_exe_trigger_t; + + + +typedef union pore_scratch0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t zeroes : 8; + uint64_t scratch0 : 24; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t scratch0 : 24; + uint64_t zeroes : 8; +#endif // _BIG_ENDIAN + } fields; +} pore_scratch0_t; + + + +typedef union pore_scratch1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t scratch1 : 64; +#else + uint64_t scratch1 : 64; +#endif // _BIG_ENDIAN + } fields; +} pore_scratch1_t; + + + +typedef union pore_scratch2 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t scratch2 : 64; +#else + uint64_t scratch2 : 64; +#endif // _BIG_ENDIAN + } fields; +} pore_scratch2_t; + + + +typedef union pore_ibuf_01 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t ibuf0 : 32; + uint64_t ibuf1 : 32; +#else + uint64_t ibuf1 : 32; + uint64_t ibuf0 : 32; +#endif // _BIG_ENDIAN + } fields; +} pore_ibuf_01_t; + + + +typedef union pore_ibuf_2 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t ibuf2 : 32; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t ibuf2 : 32; +#endif // _BIG_ENDIAN + } fields; +} pore_ibuf_2_t; + + + +typedef union pore_dbg0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t last_completed_address : 32; + uint64_t last_pib_parity_fail : 1; + uint64_t last_ret_code_prv : 3; + uint64_t i2c_bad_status0 : 1; + uint64_t i2c_bad_status1 : 1; + uint64_t i2c_bad_status2 : 1; + uint64_t i2c_bad_status3 : 1; + uint64_t group_parity_error0 : 1; + uint64_t group_parity_error1 : 1; + uint64_t group_parity_error2 : 1; + uint64_t group_parity_error3 : 1; + uint64_t group_parity_error4 : 1; + uint64_t interrupt_counter : 8; + uint64_t _reserved0 : 11; +#else + uint64_t _reserved0 : 11; + uint64_t interrupt_counter : 8; + uint64_t group_parity_error4 : 1; + uint64_t group_parity_error3 : 1; + uint64_t group_parity_error2 : 1; + uint64_t group_parity_error1 : 1; + uint64_t group_parity_error0 : 1; + uint64_t i2c_bad_status3 : 1; + uint64_t i2c_bad_status2 : 1; + uint64_t i2c_bad_status1 : 1; + uint64_t i2c_bad_status0 : 1; + uint64_t last_ret_code_prv : 3; + uint64_t last_pib_parity_fail : 1; + uint64_t last_completed_address : 32; +#endif // _BIG_ENDIAN + } fields; +} pore_dbg0_t; + + + +typedef union pore_dbg1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pc_last_access : 48; + uint64_t oci_master_rd_parity_err : 1; + uint64_t last_ret_code_oci : 3; + uint64_t bad_instr_parity : 1; + uint64_t invalid_instr_code : 1; + uint64_t pc_overflow_underrun : 1; + uint64_t bad_scan_crc : 1; + uint64_t pc_stack_ovflw_undrn_err : 1; + uint64_t instruction_fetch_error : 1; + uint64_t invalid_instruction_operand : 1; + uint64_t invalid_instruction_path : 1; + uint64_t invalid_start_vector : 1; + uint64_t fast_i2c_protocol_hang : 1; + uint64_t spare : 1; + uint64_t debug_regs_locked : 1; +#else + uint64_t debug_regs_locked : 1; + uint64_t spare : 1; + uint64_t fast_i2c_protocol_hang : 1; + uint64_t invalid_start_vector : 1; + uint64_t invalid_instruction_path : 1; + uint64_t invalid_instruction_operand : 1; + uint64_t instruction_fetch_error : 1; + uint64_t pc_stack_ovflw_undrn_err : 1; + uint64_t bad_scan_crc : 1; + uint64_t pc_overflow_underrun : 1; + uint64_t invalid_instr_code : 1; + uint64_t bad_instr_parity : 1; + uint64_t last_ret_code_oci : 3; + uint64_t oci_master_rd_parity_err : 1; + uint64_t pc_last_access : 48; +#endif // _BIG_ENDIAN + } fields; +} pore_dbg1_t; + + + +typedef union pore_pc_stack0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pc_stack0 : 48; + uint64_t _reserved0 : 11; + uint64_t set_new_stack_pointer : 1; + uint64_t new_stack_pointer : 4; +#else + uint64_t new_stack_pointer : 4; + uint64_t set_new_stack_pointer : 1; + uint64_t _reserved0 : 11; + uint64_t pc_stack0 : 48; +#endif // _BIG_ENDIAN + } fields; +} pore_pc_stack0_t; + + + +typedef union pore_pc_stack1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pc_stack1 : 48; + uint64_t _reserved0 : 16; +#else + uint64_t _reserved0 : 16; + uint64_t pc_stack1 : 48; +#endif // _BIG_ENDIAN + } fields; +} pore_pc_stack1_t; + + + +typedef union pore_pc_stack2 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pc_stack2 : 48; + uint64_t _reserved0 : 16; +#else + uint64_t _reserved0 : 16; + uint64_t pc_stack2 : 48; +#endif // _BIG_ENDIAN + } fields; +} pore_pc_stack2_t; + + + +typedef union pore_id_flags { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved0 : 32; + uint64_t pib_parity_fail : 1; + uint64_t pib_status : 3; + uint64_t oci_parity_fail : 1; + uint64_t oci_status : 3; + uint64_t reserved1 : 8; + uint64_t ugt : 1; + uint64_t ult : 1; + uint64_t sgt : 1; + uint64_t slt : 1; + uint64_t c : 1; + uint64_t o : 1; + uint64_t n : 1; + uint64_t z : 1; + uint64_t reserved2 : 4; + uint64_t ibuf_id : 4; +#else + uint64_t ibuf_id : 4; + uint64_t reserved2 : 4; + uint64_t z : 1; + uint64_t n : 1; + uint64_t o : 1; + uint64_t c : 1; + uint64_t slt : 1; + uint64_t sgt : 1; + uint64_t ult : 1; + uint64_t ugt : 1; + uint64_t reserved1 : 8; + uint64_t oci_status : 3; + uint64_t oci_parity_fail : 1; + uint64_t pib_status : 3; + uint64_t pib_parity_fail : 1; + uint64_t reserved0 : 32; +#endif // _BIG_ENDIAN + } fields; +} pore_id_flags_t; + + + +typedef union pore_data0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t data0 : 32; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t data0 : 32; +#endif // _BIG_ENDIAN + } fields; +} pore_data0_t; + + + +typedef union pore_memory_reloc { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 30; + uint64_t memory_reloc_region : 2; + uint64_t memory_reloc_base : 20; + uint64_t _reserved1 : 12; +#else + uint64_t _reserved1 : 12; + uint64_t memory_reloc_base : 20; + uint64_t memory_reloc_region : 2; + uint64_t _reserved0 : 30; +#endif // _BIG_ENDIAN + } fields; +} pore_memory_reloc_t; + + + +typedef union pore_i2c_en_param { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t i2c_engine_identifier : 4; + uint64_t reserved0 : 1; + uint64_t i2c_engine_address_range : 3; + uint64_t reserved1 : 3; + uint64_t i2c_engine_port : 5; + uint64_t reserved2 : 1; + uint64_t i2c_engine_device_id : 7; + uint64_t reserved3 : 2; + uint64_t i2c_engine_speed : 2; + uint64_t i2c_poll_threshold : 4; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t i2c_poll_threshold : 4; + uint64_t i2c_engine_speed : 2; + uint64_t reserved3 : 2; + uint64_t i2c_engine_device_id : 7; + uint64_t reserved2 : 1; + uint64_t i2c_engine_port : 5; + uint64_t reserved1 : 3; + uint64_t i2c_engine_address_range : 3; + uint64_t reserved0 : 1; + uint64_t i2c_engine_identifier : 4; +#endif // _BIG_ENDIAN + } fields; +} pore_i2c_en_param_t; + + +#endif // __ASSEMBLER__ +#endif // __PORE_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/pore_register_addresses.h b/src/ssx/pgp/registers/pore_register_addresses.h new file mode 100755 index 0000000..0fc769b --- /dev/null +++ b/src/ssx/pgp/registers/pore_register_addresses.h @@ -0,0 +1,130 @@ +#ifndef __PORE_REGISTER_ADDRESSES_H__ +#define __PORE_REGISTER_ADDRESSES_H__ + +// $Id: pore_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/pore_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file pore_register_addresses.h +/// \brief Symbolic addresses for the PORE unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define PORE_GPE0_OCI_BASE 0x40000000 +#define PORE_GPE1_OCI_BASE 0x40000100 +#define PORE_SLW_OCI_BASE 0x40040000 +#define PORE_STATUS_OFFSET 0x00000000 +#define PORE_GPE0_STATUS 0x40000000 +#define PORE_GPE1_STATUS 0x40000100 +#define PORE_SLW_STATUS 0x40040000 +#define PORE_CONTROL_OFFSET 0x00000008 +#define PORE_GPE0_CONTROL 0x40000008 +#define PORE_GPE1_CONTROL 0x40000108 +#define PORE_SLW_CONTROL 0x40040008 +#define PORE_RESET_OFFSET 0x00000010 +#define PORE_GPE0_RESET 0x40000010 +#define PORE_GPE1_RESET 0x40000110 +#define PORE_SLW_RESET 0x40040010 +#define PORE_ERROR_MASK_OFFSET 0x00000018 +#define PORE_GPE0_ERROR_MASK 0x40000018 +#define PORE_GPE1_ERROR_MASK 0x40000118 +#define PORE_SLW_ERROR_MASK 0x40040018 +#define PORE_PRV_BASE_ADDRESS0_OFFSET 0x00000020 +#define PORE_GPE0_PRV_BASE_ADDRESS0 0x40000020 +#define PORE_GPE1_PRV_BASE_ADDRESS0 0x40000120 +#define PORE_SLW_PRV_BASE_ADDRESS0 0x40040020 +#define PORE_PRV_BASE_ADDRESS1_OFFSET 0x00000028 +#define PORE_GPE0_PRV_BASE_ADDRESS1 0x40000028 +#define PORE_GPE1_PRV_BASE_ADDRESS1 0x40000128 +#define PORE_SLW_PRV_BASE_ADDRESS1 0x40040028 +#define PORE_OCI_BASE_ADDRESS0_OFFSET 0x00000030 +#define PORE_GPE0_OCI_BASE_ADDRESS0 0x40000030 +#define PORE_GPE1_OCI_BASE_ADDRESS0 0x40000130 +#define PORE_SLW_OCI_BASE_ADDRESS0 0x40040030 +#define PORE_OCI_BASE_ADDRESS1_OFFSET 0x00000038 +#define PORE_GPE0_OCI_BASE_ADDRESS1 0x40000038 +#define PORE_GPE1_OCI_BASE_ADDRESS1 0x40000138 +#define PORE_SLW_OCI_BASE_ADDRESS1 0x40040038 +#define PORE_TABLE_BASE_ADDR_OFFSET 0x00000040 +#define PORE_GPE0_TABLE_BASE_ADDR 0x40000040 +#define PORE_GPE1_TABLE_BASE_ADDR 0x40000140 +#define PORE_SLW_TABLE_BASE_ADDR 0x40040040 +#define PORE_EXE_TRIGGER_OFFSET 0x00000048 +#define PORE_GPE0_EXE_TRIGGER 0x40000048 +#define PORE_GPE1_EXE_TRIGGER 0x40000148 +#define PORE_SLW_EXE_TRIGGER 0x40040048 +#define PORE_SCRATCH0_OFFSET 0x00000050 +#define PORE_GPE0_SCRATCH0 0x40000050 +#define PORE_GPE1_SCRATCH0 0x40000150 +#define PORE_SLW_SCRATCH0 0x40040050 +#define PORE_SCRATCH1_OFFSET 0x00000058 +#define PORE_GPE0_SCRATCH1 0x40000058 +#define PORE_GPE1_SCRATCH1 0x40000158 +#define PORE_SLW_SCRATCH1 0x40040058 +#define PORE_SCRATCH2_OFFSET 0x00000060 +#define PORE_GPE0_SCRATCH2 0x40000060 +#define PORE_GPE1_SCRATCH2 0x40000160 +#define PORE_SLW_SCRATCH2 0x40040060 +#define PORE_IBUF_01_OFFSET 0x00000068 +#define PORE_GPE0_IBUF_01 0x40000068 +#define PORE_GPE1_IBUF_01 0x40000168 +#define PORE_SLW_IBUF_01 0x40040068 +#define PORE_IBUF_2_OFFSET 0x00000070 +#define PORE_GPE0_IBUF_2 0x40000070 +#define PORE_GPE1_IBUF_2 0x40000170 +#define PORE_SLW_IBUF_2 0x40040070 +#define PORE_DBG0_OFFSET 0x00000078 +#define PORE_GPE0_DBG0 0x40000078 +#define PORE_GPE1_DBG0 0x40000178 +#define PORE_SLW_DBG0 0x40040078 +#define PORE_DBG1_OFFSET 0x00000080 +#define PORE_GPE0_DBG1 0x40000080 +#define PORE_GPE1_DBG1 0x40000180 +#define PORE_SLW_DBG1 0x40040080 +#define PORE_PC_STACK0_OFFSET 0x00000088 +#define PORE_GPE0_PC_STACK0 0x40000088 +#define PORE_GPE1_PC_STACK0 0x40000188 +#define PORE_SLW_PC_STACK0 0x40040088 +#define PORE_PC_STACK1_OFFSET 0x00000090 +#define PORE_GPE0_PC_STACK1 0x40000090 +#define PORE_GPE1_PC_STACK1 0x40000190 +#define PORE_SLW_PC_STACK1 0x40040090 +#define PORE_PC_STACK2_OFFSET 0x00000098 +#define PORE_GPE0_PC_STACK2 0x40000098 +#define PORE_GPE1_PC_STACK2 0x40000198 +#define PORE_SLW_PC_STACK2 0x40040098 +#define PORE_ID_FLAGS_OFFSET 0x000000a0 +#define PORE_GPE0_ID_FLAGS 0x400000a0 +#define PORE_GPE1_ID_FLAGS 0x400001a0 +#define PORE_SLW_ID_FLAGS 0x400400a0 +#define PORE_DATA0_OFFSET 0x000000a8 +#define PORE_GPE0_DATA0 0x400000a8 +#define PORE_GPE1_DATA0 0x400001a8 +#define PORE_SLW_DATA0 0x400400a8 +#define PORE_MEMORY_RELOC_OFFSET 0x000000b0 +#define PORE_GPE0_MEMORY_RELOC 0x400000b0 +#define PORE_GPE1_MEMORY_RELOC 0x400001b0 +#define PORE_SLW_MEMORY_RELOC 0x400400b0 +#define PORE_I2C_E0_PARAM_OFFSET 0x000000b8 +#define PORE_I2C_E1_PARAM_OFFSET 0x000000c0 +#define PORE_I2C_E2_PARAM_OFFSET 0x000000c8 +#define PORE_GPE0_I2C_EN_PARAM(n) (PORE_GPE0_I2C_E0_PARAM + ((PORE_GPE0_I2C_E1_PARAM - PORE_GPE0_I2C_E0_PARAM) * (n))) +#define PORE_GPE1_I2C_EN_PARAM(n) (PORE_GPE1_I2C_E0_PARAM + ((PORE_GPE1_I2C_E1_PARAM - PORE_GPE1_I2C_E0_PARAM) * (n))) +#define PORE_SLW_I2C_EN_PARAM(n) (PORE_SLW_I2C_E0_PARAM + ((PORE_SLW_I2C_E1_PARAM - PORE_SLW_I2C_E0_PARAM) * (n))) +#define PORE_GPE0_I2C_E0_PARAM 0x400000b8 +#define PORE_GPE1_I2C_E0_PARAM 0x400001b8 +#define PORE_SLW_I2C_E0_PARAM 0x400400b8 +#define PORE_GPE0_I2C_E1_PARAM 0x400000c0 +#define PORE_GPE1_I2C_E1_PARAM 0x400001c0 +#define PORE_SLW_I2C_E1_PARAM 0x400400c0 +#define PORE_GPE0_I2C_E2_PARAM 0x400000c8 +#define PORE_GPE1_I2C_E2_PARAM 0x400001c8 +#define PORE_SLW_I2C_E2_PARAM 0x400400c8 + +#endif // __PORE_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/sbe_firmware_registers.h b/src/ssx/pgp/registers/sbe_firmware_registers.h new file mode 100644 index 0000000..8175c11 --- /dev/null +++ b/src/ssx/pgp/registers/sbe_firmware_registers.h @@ -0,0 +1,906 @@ +#ifndef __SBE_FIRMWARE_REGISTERS_H__ +#define __SBE_FIRMWARE_REGISTERS_H__ + +// $Id: sbe_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sbe_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file sbe_firmware_registers.h +/// \brief C register structs for the SBE unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union pore_sbe_status { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t cur_state : 8; + uint64_t freeze_action : 1; + uint64_t interrupt_pending : 1; + uint64_t spare : 2; + uint64_t stack_pointer : 4; + uint64_t pc : 48; +#else + uint64_t pc : 48; + uint64_t stack_pointer : 4; + uint64_t spare : 2; + uint64_t interrupt_pending : 1; + uint64_t freeze_action : 1; + uint64_t cur_state : 8; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_status_t; + +#endif // __ASSEMBLER__ +#define PORE_SBE_STATUS_CUR_STATE_MASK SIXTYFOUR_BIT_CONSTANT(0xff00000000000000) +#define PORE_SBE_STATUS_FREEZE_ACTION SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) +#define PORE_SBE_STATUS_INTERRUPT_PENDING SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) +#define PORE_SBE_STATUS_SPARE_MASK SIXTYFOUR_BIT_CONSTANT(0x0030000000000000) +#define PORE_SBE_STATUS_STACK_POINTER_MASK SIXTYFOUR_BIT_CONSTANT(0x000f000000000000) +#define PORE_SBE_STATUS_PC_MASK SIXTYFOUR_BIT_CONSTANT(0xffffffffffffffff) +#ifndef __ASSEMBLER__ + + +typedef union pore_sbe_control { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t start_stop : 1; + uint64_t continue_step : 1; + uint64_t skip : 1; + uint64_t set_pc : 1; + uint64_t set_tp_scan_clk : 3; + uint64_t lock_exe_trig : 1; + uint64_t freeze_mask : 1; + uint64_t check_parity : 1; + uint64_t prv_parity : 1; + uint64_t trap_enable : 1; + uint64_t narrow_mode_trace : 1; + uint64_t interruptible : 1; + uint64_t pore_done_override : 1; + uint64_t interruptible_en : 1; + uint64_t pc_brk_pt : 48; +#else + uint64_t pc_brk_pt : 48; + uint64_t interruptible_en : 1; + uint64_t pore_done_override : 1; + uint64_t interruptible : 1; + uint64_t narrow_mode_trace : 1; + uint64_t trap_enable : 1; + uint64_t prv_parity : 1; + uint64_t check_parity : 1; + uint64_t freeze_mask : 1; + uint64_t lock_exe_trig : 1; + uint64_t set_tp_scan_clk : 3; + uint64_t set_pc : 1; + uint64_t skip : 1; + uint64_t continue_step : 1; + uint64_t start_stop : 1; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_control_t; + +#endif // __ASSEMBLER__ +#define PORE_SBE_CONTROL_START_STOP SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define PORE_SBE_CONTROL_CONTINUE_STEP SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#define PORE_SBE_CONTROL_SKIP SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) +#define PORE_SBE_CONTROL_SET_PC SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) +#define PORE_SBE_CONTROL_SET_TP_SCAN_CLK_MASK SIXTYFOUR_BIT_CONSTANT(0x0e00000000000000) +#define PORE_SBE_CONTROL_LOCK_EXE_TRIG SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) +#define PORE_SBE_CONTROL_FREEZE_MASK SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) +#define PORE_SBE_CONTROL_CHECK_PARITY SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) +#define PORE_SBE_CONTROL_PRV_PARITY SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) +#define PORE_SBE_CONTROL_TRAP_ENABLE SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) +#define PORE_SBE_CONTROL_NARROW_MODE_TRACE SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) +#define PORE_SBE_CONTROL_INTERRUPTIBLE SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) +#define PORE_SBE_CONTROL_PORE_DONE_OVERRIDE SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) +#define PORE_SBE_CONTROL_INTERRUPTIBLE_EN SIXTYFOUR_BIT_CONSTANT(0x0001000000000000) +#define PORE_SBE_CONTROL_PC_BRK_PT_MASK SIXTYFOUR_BIT_CONSTANT(0xffffffffffffffff) +#ifndef __ASSEMBLER__ + + +typedef union pore_sbe_reset { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t fn_reset : 1; + uint64_t oci_reset : 1; + uint64_t _reserved0 : 62; +#else + uint64_t _reserved0 : 62; + uint64_t oci_reset : 1; + uint64_t fn_reset : 1; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_reset_t; + + + +typedef union pore_sbe_error_mask { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t enable_err_handler0 : 1; + uint64_t enable_err_handler1 : 1; + uint64_t enable_err_handler2 : 1; + uint64_t enable_err_handler3 : 1; + uint64_t enable_err_handler4 : 1; + uint64_t enable_err_output0 : 1; + uint64_t enable_err_output1 : 1; + uint64_t enable_err_output2 : 1; + uint64_t enable_err_output3 : 1; + uint64_t enable_err_output4 : 1; + uint64_t enable_fatal_err_output0 : 1; + uint64_t enable_fatal_err_output1 : 1; + uint64_t enable_fatal_err_output2 : 1; + uint64_t enable_fatal_err_output3 : 1; + uint64_t enable_fatal_err_output4 : 1; + uint64_t stop_exe_on_error0 : 1; + uint64_t stop_exe_on_error1 : 1; + uint64_t stop_exe_on_error2 : 1; + uint64_t stop_exe_on_error3 : 1; + uint64_t stop_exe_on_error4 : 1; + uint64_t gate_chiplet_offline_err : 1; + uint64_t i2c_bad_status_0 : 1; + uint64_t i2c_bad_status_1 : 1; + uint64_t i2c_bad_status_2 : 1; + uint64_t i2c_bad_status_3 : 1; + uint64_t group_parity_error_0 : 1; + uint64_t group_parity_error_1 : 1; + uint64_t group_parity_error_2 : 1; + uint64_t group_parity_error_3 : 1; + uint64_t group_parity_error_4 : 1; + uint64_t _reserved0 : 34; +#else + uint64_t _reserved0 : 34; + uint64_t group_parity_error_4 : 1; + uint64_t group_parity_error_3 : 1; + uint64_t group_parity_error_2 : 1; + uint64_t group_parity_error_1 : 1; + uint64_t group_parity_error_0 : 1; + uint64_t i2c_bad_status_3 : 1; + uint64_t i2c_bad_status_2 : 1; + uint64_t i2c_bad_status_1 : 1; + uint64_t i2c_bad_status_0 : 1; + uint64_t gate_chiplet_offline_err : 1; + uint64_t stop_exe_on_error4 : 1; + uint64_t stop_exe_on_error3 : 1; + uint64_t stop_exe_on_error2 : 1; + uint64_t stop_exe_on_error1 : 1; + uint64_t stop_exe_on_error0 : 1; + uint64_t enable_fatal_err_output4 : 1; + uint64_t enable_fatal_err_output3 : 1; + uint64_t enable_fatal_err_output2 : 1; + uint64_t enable_fatal_err_output1 : 1; + uint64_t enable_fatal_err_output0 : 1; + uint64_t enable_err_output4 : 1; + uint64_t enable_err_output3 : 1; + uint64_t enable_err_output2 : 1; + uint64_t enable_err_output1 : 1; + uint64_t enable_err_output0 : 1; + uint64_t enable_err_handler4 : 1; + uint64_t enable_err_handler3 : 1; + uint64_t enable_err_handler2 : 1; + uint64_t enable_err_handler1 : 1; + uint64_t enable_err_handler0 : 1; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_error_mask_t; + +#endif // __ASSEMBLER__ +#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER0 SIXTYFOUR_BIT_CONSTANT(0x8000000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER1 SIXTYFOUR_BIT_CONSTANT(0x4000000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER2 SIXTYFOUR_BIT_CONSTANT(0x2000000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER3 SIXTYFOUR_BIT_CONSTANT(0x1000000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_ERR_HANDLER4 SIXTYFOUR_BIT_CONSTANT(0x0800000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT0 SIXTYFOUR_BIT_CONSTANT(0x0400000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT1 SIXTYFOUR_BIT_CONSTANT(0x0200000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT2 SIXTYFOUR_BIT_CONSTANT(0x0100000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT3 SIXTYFOUR_BIT_CONSTANT(0x0080000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_ERR_OUTPUT4 SIXTYFOUR_BIT_CONSTANT(0x0040000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT0 SIXTYFOUR_BIT_CONSTANT(0x0020000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT1 SIXTYFOUR_BIT_CONSTANT(0x0010000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT2 SIXTYFOUR_BIT_CONSTANT(0x0008000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT3 SIXTYFOUR_BIT_CONSTANT(0x0004000000000000) +#define PORE_SBE_ERROR_MASK_ENABLE_FATAL_ERR_OUTPUT4 SIXTYFOUR_BIT_CONSTANT(0x0002000000000000) +#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR0 SIXTYFOUR_BIT_CONSTANT(0x0001000000000000) +#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR1 SIXTYFOUR_BIT_CONSTANT(0x0000800000000000) +#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR2 SIXTYFOUR_BIT_CONSTANT(0x0000400000000000) +#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR3 SIXTYFOUR_BIT_CONSTANT(0x0000200000000000) +#define PORE_SBE_ERROR_MASK_STOP_EXE_ON_ERROR4 SIXTYFOUR_BIT_CONSTANT(0x0000100000000000) +#define PORE_SBE_ERROR_MASK_GATE_CHIPLET_OFFLINE_ERR SIXTYFOUR_BIT_CONSTANT(0x0000080000000000) +#define PORE_SBE_ERROR_MASK_I2C_BAD_STATUS_0 SIXTYFOUR_BIT_CONSTANT(0x0000040000000000) +#define PORE_SBE_ERROR_MASK_I2C_BAD_STATUS_1 SIXTYFOUR_BIT_CONSTANT(0x0000020000000000) +#define PORE_SBE_ERROR_MASK_I2C_BAD_STATUS_2 SIXTYFOUR_BIT_CONSTANT(0x0000010000000000) +#define PORE_SBE_ERROR_MASK_I2C_BAD_STATUS_3 SIXTYFOUR_BIT_CONSTANT(0x0000008000000000) +#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_0 SIXTYFOUR_BIT_CONSTANT(0x0000004000000000) +#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_1 SIXTYFOUR_BIT_CONSTANT(0x0000002000000000) +#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_2 SIXTYFOUR_BIT_CONSTANT(0x0000001000000000) +#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_3 SIXTYFOUR_BIT_CONSTANT(0x0000000800000000) +#define PORE_SBE_ERROR_MASK_GROUP_PARITY_ERROR_4 SIXTYFOUR_BIT_CONSTANT(0x0000000400000000) +#ifndef __ASSEMBLER__ + + +typedef union pore_sbe_prv_base_address0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t spare : 25; + uint64_t mc : 1; + uint64_t chiplet_id : 6; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t chiplet_id : 6; + uint64_t mc : 1; + uint64_t spare : 25; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_prv_base_address0_t; + + + +typedef union pore_sbe_prv_base_address1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t spare : 25; + uint64_t mc : 1; + uint64_t chiplet_id : 6; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t chiplet_id : 6; + uint64_t mc : 1; + uint64_t spare : 25; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_prv_base_address1_t; + + + +typedef union pore_sbe_oci_base_address0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t spare : 18; + uint64_t oci_mem_route : 14; + uint64_t oci_base_address : 32; +#else + uint64_t oci_base_address : 32; + uint64_t oci_mem_route : 14; + uint64_t spare : 18; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_oci_base_address0_t; + + + +typedef union pore_sbe_oci_base_address1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t spare : 18; + uint64_t oci_mem_route : 14; + uint64_t oci_base_address : 32; +#else + uint64_t oci_base_address : 32; + uint64_t oci_mem_route : 14; + uint64_t spare : 18; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_oci_base_address1_t; + + + +typedef union pore_sbe_table_base_addr { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved : 16; + uint64_t memory_space : 16; + uint64_t table_base_address : 32; +#else + uint64_t table_base_address : 32; + uint64_t memory_space : 16; + uint64_t reserved : 16; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_table_base_addr_t; + + + +typedef union pore_sbe_exe_trigger { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved : 8; + uint64_t start_vector : 4; + uint64_t zeroes : 8; + uint64_t unused : 12; + uint64_t mc_chiplet_select_mask : 32; +#else + uint64_t mc_chiplet_select_mask : 32; + uint64_t unused : 12; + uint64_t zeroes : 8; + uint64_t start_vector : 4; + uint64_t reserved : 8; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_exe_trigger_t; + + + +typedef union pore_sbe_scratch0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t zeroes : 8; + uint64_t scratch0 : 24; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t scratch0 : 24; + uint64_t zeroes : 8; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_scratch0_t; + + + +typedef union pore_sbe_scratch1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t scratch1 : 64; +#else + uint64_t scratch1 : 64; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_scratch1_t; + + + +typedef union pore_sbe_scratch2 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t scratch2 : 64; +#else + uint64_t scratch2 : 64; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_scratch2_t; + + + +typedef union pore_sbe_ibuf_01 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t ibuf0 : 32; + uint64_t ibuf1 : 32; +#else + uint64_t ibuf1 : 32; + uint64_t ibuf0 : 32; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_ibuf_01_t; + + + +typedef union pore_sbe_ibuf_2 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t ibuf2 : 32; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t ibuf2 : 32; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_ibuf_2_t; + + + +typedef union pore_sbe_dbg0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t last_completed_address : 32; + uint64_t last_pib_parity_fail : 1; + uint64_t last_ret_code_prv : 3; + uint64_t i2c_bad_status0 : 1; + uint64_t i2c_bad_status1 : 1; + uint64_t i2c_bad_status2 : 1; + uint64_t i2c_bad_status3 : 1; + uint64_t group_parity_error0 : 1; + uint64_t group_parity_error1 : 1; + uint64_t group_parity_error2 : 1; + uint64_t group_parity_error3 : 1; + uint64_t group_parity_error4 : 1; + uint64_t interrupt_counter : 8; + uint64_t _reserved0 : 11; +#else + uint64_t _reserved0 : 11; + uint64_t interrupt_counter : 8; + uint64_t group_parity_error4 : 1; + uint64_t group_parity_error3 : 1; + uint64_t group_parity_error2 : 1; + uint64_t group_parity_error1 : 1; + uint64_t group_parity_error0 : 1; + uint64_t i2c_bad_status3 : 1; + uint64_t i2c_bad_status2 : 1; + uint64_t i2c_bad_status1 : 1; + uint64_t i2c_bad_status0 : 1; + uint64_t last_ret_code_prv : 3; + uint64_t last_pib_parity_fail : 1; + uint64_t last_completed_address : 32; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_dbg0_t; + + + +typedef union pore_sbe_dbg1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pc_last_access : 48; + uint64_t oci_master_rd_parity_err : 1; + uint64_t last_ret_code_oci : 3; + uint64_t bad_instr_parity : 1; + uint64_t invalid_instr_code : 1; + uint64_t pc_overflow_underrun : 1; + uint64_t bad_scan_crc : 1; + uint64_t pc_stack_ovflw_undrn_err : 1; + uint64_t instruction_fetch_error : 1; + uint64_t invalid_instruction_operand : 1; + uint64_t invalid_instruction_path : 1; + uint64_t invalid_start_vector : 1; + uint64_t fast_i2c_protocol_hang : 1; + uint64_t spare : 1; + uint64_t debug_regs_locked : 1; +#else + uint64_t debug_regs_locked : 1; + uint64_t spare : 1; + uint64_t fast_i2c_protocol_hang : 1; + uint64_t invalid_start_vector : 1; + uint64_t invalid_instruction_path : 1; + uint64_t invalid_instruction_operand : 1; + uint64_t instruction_fetch_error : 1; + uint64_t pc_stack_ovflw_undrn_err : 1; + uint64_t bad_scan_crc : 1; + uint64_t pc_overflow_underrun : 1; + uint64_t invalid_instr_code : 1; + uint64_t bad_instr_parity : 1; + uint64_t last_ret_code_oci : 3; + uint64_t oci_master_rd_parity_err : 1; + uint64_t pc_last_access : 48; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_dbg1_t; + + + +typedef union pore_sbe_pc_stack0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pc_stack0 : 48; + uint64_t _reserved0 : 11; + uint64_t set_new_stack_pointer : 1; + uint64_t new_stack_pointer : 4; +#else + uint64_t new_stack_pointer : 4; + uint64_t set_new_stack_pointer : 1; + uint64_t _reserved0 : 11; + uint64_t pc_stack0 : 48; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_pc_stack0_t; + + + +typedef union pore_sbe_pc_stack1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pc_stack1 : 48; + uint64_t _reserved0 : 16; +#else + uint64_t _reserved0 : 16; + uint64_t pc_stack1 : 48; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_pc_stack1_t; + + + +typedef union pore_sbe_pc_stack2 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t pc_stack2 : 48; + uint64_t _reserved0 : 16; +#else + uint64_t _reserved0 : 16; + uint64_t pc_stack2 : 48; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_pc_stack2_t; + + + +typedef union pore_sbe_id_flags { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t reserved0 : 32; + uint64_t pib_parity_fail : 1; + uint64_t pib_status : 3; + uint64_t oci_parity_fail : 1; + uint64_t oci_status : 3; + uint64_t reserved1 : 8; + uint64_t ugt : 1; + uint64_t ult : 1; + uint64_t sgt : 1; + uint64_t slt : 1; + uint64_t c : 1; + uint64_t o : 1; + uint64_t n : 1; + uint64_t z : 1; + uint64_t reserved2 : 4; + uint64_t ibuf_id : 4; +#else + uint64_t ibuf_id : 4; + uint64_t reserved2 : 4; + uint64_t z : 1; + uint64_t n : 1; + uint64_t o : 1; + uint64_t c : 1; + uint64_t slt : 1; + uint64_t sgt : 1; + uint64_t ult : 1; + uint64_t ugt : 1; + uint64_t reserved1 : 8; + uint64_t oci_status : 3; + uint64_t oci_parity_fail : 1; + uint64_t pib_status : 3; + uint64_t pib_parity_fail : 1; + uint64_t reserved0 : 32; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_id_flags_t; + + + +typedef union pore_sbe_data0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t data0 : 32; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t data0 : 32; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_data0_t; + + + +typedef union pore_sbe_memory_reloc { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t _reserved0 : 30; + uint64_t memory_reloc_region : 2; + uint64_t memory_reloc_base : 20; + uint64_t _reserved1 : 12; +#else + uint64_t _reserved1 : 12; + uint64_t memory_reloc_base : 20; + uint64_t memory_reloc_region : 2; + uint64_t _reserved0 : 30; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_memory_reloc_t; + + + +typedef union pore_sbe_i2c_en_param { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t i2c_engine_identifier : 4; + uint64_t reserved0 : 1; + uint64_t i2c_engine_address_range : 3; + uint64_t reserved1 : 3; + uint64_t i2c_engine_port : 5; + uint64_t reserved2 : 1; + uint64_t i2c_engine_device_id : 7; + uint64_t reserved3 : 2; + uint64_t i2c_engine_speed : 2; + uint64_t i2c_poll_threshold : 4; + uint64_t _reserved0 : 32; +#else + uint64_t _reserved0 : 32; + uint64_t i2c_poll_threshold : 4; + uint64_t i2c_engine_speed : 2; + uint64_t reserved3 : 2; + uint64_t i2c_engine_device_id : 7; + uint64_t reserved2 : 1; + uint64_t i2c_engine_port : 5; + uint64_t reserved1 : 3; + uint64_t i2c_engine_address_range : 3; + uint64_t reserved0 : 1; + uint64_t i2c_engine_identifier : 4; +#endif // _BIG_ENDIAN + } fields; +} pore_sbe_i2c_en_param_t; + + +#endif // __ASSEMBLER__ +#endif // __SBE_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/sbe_register_addresses.h b/src/ssx/pgp/registers/sbe_register_addresses.h new file mode 100644 index 0000000..794acea --- /dev/null +++ b/src/ssx/pgp/registers/sbe_register_addresses.h @@ -0,0 +1,48 @@ +#ifndef __SBE_REGISTER_ADDRESSES_H__ +#define __SBE_REGISTER_ADDRESSES_H__ + +// $Id: sbe_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sbe_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file sbe_register_addresses.h +/// \brief Symbolic addresses for the SBE unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define PORE_SBE_PIB_BASE 0x000e0000 +#define PORE_SBE_STATUS 0x000e0000 +#define PORE_SBE_CONTROL 0x000e0001 +#define PORE_SBE_RESET 0x000e0002 +#define PORE_SBE_ERROR_MASK 0x000e0003 +#define PORE_SBE_PRV_BASE_ADDRESS0 0x000e0004 +#define PORE_SBE_PRV_BASE_ADDRESS1 0x000e0005 +#define PORE_SBE_OCI_BASE_ADDRESS0 0x000e0006 +#define PORE_SBE_OCI_BASE_ADDRESS1 0x000e0007 +#define PORE_SBE_TABLE_BASE_ADDR 0x000e0008 +#define PORE_SBE_EXE_TRIGGER 0x000e0009 +#define PORE_SBE_SCRATCH0 0x000e000a +#define PORE_SBE_SCRATCH1 0x000e000b +#define PORE_SBE_SCRATCH2 0x000e000c +#define PORE_SBE_IBUF_01 0x000e000d +#define PORE_SBE_IBUF_2 0x000e000e +#define PORE_SBE_DBG0 0x000e000f +#define PORE_SBE_DBG1 0x000e0010 +#define PORE_SBE_PC_STACK0 0x000e0011 +#define PORE_SBE_PC_STACK1 0x000e0012 +#define PORE_SBE_PC_STACK2 0x000e0013 +#define PORE_SBE_ID_FLAGS 0x000e0014 +#define PORE_SBE_DATA0 0x000e0015 +#define PORE_SBE_MEMORY_RELOC 0x000e0016 +#define PORE_SBE_I2C_EN_PARAM(n) (PORE_SBE_I2C_E0_PARAM + ((PORE_SBE_I2C_E1_PARAM - PORE_SBE_I2C_E0_PARAM) * (n))) +#define PORE_SBE_I2C_E0_PARAM 0x000e0017 +#define PORE_SBE_I2C_E1_PARAM 0x000e0018 +#define PORE_SBE_I2C_E2_PARAM 0x000e0019 + +#endif // __SBE_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/sensors_firmware_registers.h b/src/ssx/pgp/registers/sensors_firmware_registers.h new file mode 100755 index 0000000..9cb252e --- /dev/null +++ b/src/ssx/pgp/registers/sensors_firmware_registers.h @@ -0,0 +1,668 @@ +#ifndef __SENSORS_FIRMWARE_REGISTERS_H__ +#define __SENSORS_FIRMWARE_REGISTERS_H__ + +// $Id: sensors_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sensors_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file sensors_firmware_registers.h +/// \brief C register structs for the SENSORS unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union sensors_v0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t dts0 : 12; + uint64_t thermal_trip0 : 2; + uint64_t spare0 : 1; + uint64_t valid0 : 1; + uint64_t dts1 : 12; + uint64_t thermal_trip1 : 2; + uint64_t spare1 : 1; + uint64_t valid1 : 1; + uint64_t dts2 : 12; + uint64_t thermal_trip2 : 2; + uint64_t spare2 : 1; + uint64_t valid2 : 1; + uint64_t dts3 : 12; + uint64_t thermal_trip3 : 2; + uint64_t spare3 : 1; + uint64_t valid3 : 1; +#else + uint64_t valid3 : 1; + uint64_t spare3 : 1; + uint64_t thermal_trip3 : 2; + uint64_t dts3 : 12; + uint64_t valid2 : 1; + uint64_t spare2 : 1; + uint64_t thermal_trip2 : 2; + uint64_t dts2 : 12; + uint64_t valid1 : 1; + uint64_t spare1 : 1; + uint64_t thermal_trip1 : 2; + uint64_t dts1 : 12; + uint64_t valid0 : 1; + uint64_t spare0 : 1; + uint64_t thermal_trip0 : 2; + uint64_t dts0 : 12; +#endif // _BIG_ENDIAN + } fields; +} sensors_v0_t; + + + +typedef union sensors_v1 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t dts4 : 12; + uint64_t thermal_trip4 : 2; + uint64_t spare4 : 1; + uint64_t valid4 : 1; + uint64_t dts5 : 12; + uint64_t thermal_trip5 : 2; + uint64_t spare5 : 1; + uint64_t valid5 : 1; + uint64_t dts6 : 12; + uint64_t thermal_trip6 : 2; + uint64_t spare6 : 1; + uint64_t valid6 : 1; + uint64_t dts7 : 12; + uint64_t thermal_trip7 : 2; + uint64_t spare7 : 1; + uint64_t valid7 : 1; +#else + uint64_t valid7 : 1; + uint64_t spare7 : 1; + uint64_t thermal_trip7 : 2; + uint64_t dts7 : 12; + uint64_t valid6 : 1; + uint64_t spare6 : 1; + uint64_t thermal_trip6 : 2; + uint64_t dts6 : 12; + uint64_t valid5 : 1; + uint64_t spare5 : 1; + uint64_t thermal_trip5 : 2; + uint64_t dts5 : 12; + uint64_t valid4 : 1; + uint64_t spare4 : 1; + uint64_t thermal_trip4 : 2; + uint64_t dts4 : 12; +#endif // _BIG_ENDIAN + } fields; +} sensors_v1_t; + + + +typedef union sensors_v2 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t dts8 : 12; + uint64_t thermal_trip8 : 2; + uint64_t spare8 : 1; + uint64_t valid8 : 1; + uint64_t dts9 : 12; + uint64_t thermal_trip9 : 2; + uint64_t spare9 : 1; + uint64_t valid9 : 1; + uint64_t dts10 : 12; + uint64_t thermal_trip10 : 2; + uint64_t spare10 : 1; + uint64_t valid10 : 1; + uint64_t dts12 : 12; + uint64_t thermal_trip12 : 2; + uint64_t spare12 : 1; + uint64_t valid12 : 1; +#else + uint64_t valid12 : 1; + uint64_t spare12 : 1; + uint64_t thermal_trip12 : 2; + uint64_t dts12 : 12; + uint64_t valid10 : 1; + uint64_t spare10 : 1; + uint64_t thermal_trip10 : 2; + uint64_t dts10 : 12; + uint64_t valid9 : 1; + uint64_t spare9 : 1; + uint64_t thermal_trip9 : 2; + uint64_t dts9 : 12; + uint64_t valid8 : 1; + uint64_t spare8 : 1; + uint64_t thermal_trip8 : 2; + uint64_t dts8 : 12; +#endif // _BIG_ENDIAN + } fields; +} sensors_v2_t; + + + +typedef union sensors_v3 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t unknown : 64; +#else + uint64_t unknown : 64; +#endif // _BIG_ENDIAN + } fields; +} sensors_v3_t; + + + +typedef union sensors_v5 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t raw_cpm0 : 12; + uint64_t spare0 : 4; + uint64_t raw_cpm1 : 12; + uint64_t spare1 : 4; + uint64_t raw_cpm2 : 12; + uint64_t spare2 : 4; + uint64_t raw_cpm3 : 12; + uint64_t spare3 : 4; +#else + uint64_t spare3 : 4; + uint64_t raw_cpm3 : 12; + uint64_t spare2 : 4; + uint64_t raw_cpm2 : 12; + uint64_t spare1 : 4; + uint64_t raw_cpm1 : 12; + uint64_t spare0 : 4; + uint64_t raw_cpm0 : 12; +#endif // _BIG_ENDIAN + } fields; +} sensors_v5_t; + + + +typedef union sensors_v6 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t raw_cpm4 : 12; + uint64_t spare4 : 4; + uint64_t raw_cpm5 : 12; + uint64_t spare5 : 4; + uint64_t raw_cpm6 : 12; + uint64_t spare6 : 4; + uint64_t raw_cpm7 : 12; + uint64_t spare7 : 4; +#else + uint64_t spare7 : 4; + uint64_t raw_cpm7 : 12; + uint64_t spare6 : 4; + uint64_t raw_cpm6 : 12; + uint64_t spare5 : 4; + uint64_t raw_cpm5 : 12; + uint64_t spare4 : 4; + uint64_t raw_cpm4 : 12; +#endif // _BIG_ENDIAN + } fields; +} sensors_v6_t; + + + +typedef union sensors_v7 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t raw_cpm8 : 12; + uint64_t spare8 : 4; + uint64_t raw_cpm9 : 12; + uint64_t spare9 : 4; + uint64_t raw_cpm10 : 12; + uint64_t spare10 : 4; + uint64_t raw_cpm11 : 12; + uint64_t spare11 : 4; +#else + uint64_t spare11 : 4; + uint64_t raw_cpm11 : 12; + uint64_t spare10 : 4; + uint64_t raw_cpm10 : 12; + uint64_t spare9 : 4; + uint64_t raw_cpm9 : 12; + uint64_t spare8 : 4; + uint64_t raw_cpm8 : 12; +#endif // _BIG_ENDIAN + } fields; +} sensors_v7_t; + + + +typedef union sensors_v8 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t dts0 : 12; + uint64_t thermal_trip0 : 2; + uint64_t spare0 : 1; + uint64_t valid0 : 1; + uint64_t dts1 : 12; + uint64_t thermal_trip1 : 2; + uint64_t spare1 : 1; + uint64_t valid1 : 1; + uint64_t dts2 : 12; + uint64_t thermal_trip2 : 2; + uint64_t spare2 : 1; + uint64_t valid2 : 1; + uint64_t encoded_cpm0 : 4; + uint64_t encoded_cpm1 : 4; + uint64_t encoded_cpm2 : 4; + uint64_t encoded_cpm3 : 4; +#else + uint64_t encoded_cpm3 : 4; + uint64_t encoded_cpm2 : 4; + uint64_t encoded_cpm1 : 4; + uint64_t encoded_cpm0 : 4; + uint64_t valid2 : 1; + uint64_t spare2 : 1; + uint64_t thermal_trip2 : 2; + uint64_t dts2 : 12; + uint64_t valid1 : 1; + uint64_t spare1 : 1; + uint64_t thermal_trip1 : 2; + uint64_t dts1 : 12; + uint64_t valid0 : 1; + uint64_t spare0 : 1; + uint64_t thermal_trip0 : 2; + uint64_t dts0 : 12; +#endif // _BIG_ENDIAN + } fields; +} sensors_v8_t; + + + +typedef union sensors_v9 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t dts4 : 12; + uint64_t thermal_trip4 : 2; + uint64_t spare4 : 1; + uint64_t valid4 : 1; + uint64_t dts5 : 12; + uint64_t thermal_trip5 : 2; + uint64_t spare5 : 1; + uint64_t valid5 : 1; + uint64_t dts6 : 12; + uint64_t thermal_trip6 : 2; + uint64_t spare6 : 1; + uint64_t valid6 : 1; + uint64_t encoded_cpm4 : 4; + uint64_t encoded_cpm5 : 4; + uint64_t encoded_cpm6 : 4; + uint64_t encoded_cpm7 : 4; +#else + uint64_t encoded_cpm7 : 4; + uint64_t encoded_cpm6 : 4; + uint64_t encoded_cpm5 : 4; + uint64_t encoded_cpm4 : 4; + uint64_t valid6 : 1; + uint64_t spare6 : 1; + uint64_t thermal_trip6 : 2; + uint64_t dts6 : 12; + uint64_t valid5 : 1; + uint64_t spare5 : 1; + uint64_t thermal_trip5 : 2; + uint64_t dts5 : 12; + uint64_t valid4 : 1; + uint64_t spare4 : 1; + uint64_t thermal_trip4 : 2; + uint64_t dts4 : 12; +#endif // _BIG_ENDIAN + } fields; +} sensors_v9_t; + + + +typedef union sensors_v10 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t dts8 : 12; + uint64_t thermal_trip8 : 2; + uint64_t spare8 : 1; + uint64_t valid8 : 1; + uint64_t dts9 : 12; + uint64_t thermal_trip9 : 2; + uint64_t spare9 : 1; + uint64_t valid9 : 1; + uint64_t dts10 : 12; + uint64_t thermal_trip10 : 2; + uint64_t spare10 : 1; + uint64_t valid10 : 1; + uint64_t encoded_cpm8 : 4; + uint64_t encoded_cpm9 : 4; + uint64_t encoded_cpm10 : 4; + uint64_t encoded_cpm11 : 4; +#else + uint64_t encoded_cpm11 : 4; + uint64_t encoded_cpm10 : 4; + uint64_t encoded_cpm9 : 4; + uint64_t encoded_cpm8 : 4; + uint64_t valid10 : 1; + uint64_t spare10 : 1; + uint64_t thermal_trip10 : 2; + uint64_t dts10 : 12; + uint64_t valid9 : 1; + uint64_t spare9 : 1; + uint64_t thermal_trip9 : 2; + uint64_t dts9 : 12; + uint64_t valid8 : 1; + uint64_t spare8 : 1; + uint64_t thermal_trip8 : 2; + uint64_t dts8 : 12; +#endif // _BIG_ENDIAN + } fields; +} sensors_v10_t; + + + +typedef union sensors_v11 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t dvs0 : 12; + uint64_t spare00 : 1; + uint64_t trip0 : 1; + uint64_t spare01 : 1; + uint64_t valid0 : 1; + uint64_t dvs1 : 12; + uint64_t spare10 : 1; + uint64_t trip1 : 1; + uint64_t spare11 : 1; + uint64_t valid1 : 1; + uint64_t dvs2 : 12; + uint64_t spare20 : 1; + uint64_t trip2 : 1; + uint64_t spare21 : 1; + uint64_t valid2 : 1; + uint64_t dvs3 : 12; + uint64_t spare30 : 1; + uint64_t trip3 : 1; + uint64_t spare31 : 1; + uint64_t valid3 : 1; +#else + uint64_t valid3 : 1; + uint64_t spare31 : 1; + uint64_t trip3 : 1; + uint64_t spare30 : 1; + uint64_t dvs3 : 12; + uint64_t valid2 : 1; + uint64_t spare21 : 1; + uint64_t trip2 : 1; + uint64_t spare20 : 1; + uint64_t dvs2 : 12; + uint64_t valid1 : 1; + uint64_t spare11 : 1; + uint64_t trip1 : 1; + uint64_t spare10 : 1; + uint64_t dvs1 : 12; + uint64_t valid0 : 1; + uint64_t spare01 : 1; + uint64_t trip0 : 1; + uint64_t spare00 : 1; + uint64_t dvs0 : 12; +#endif // _BIG_ENDIAN + } fields; +} sensors_v11_t; + + + +typedef union sensors_v12 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t dvs4 : 12; + uint64_t spare40 : 1; + uint64_t trip4 : 1; + uint64_t spare41 : 1; + uint64_t valid4 : 1; + uint64_t dvs5 : 12; + uint64_t spare50 : 1; + uint64_t trip5 : 1; + uint64_t spare51 : 1; + uint64_t valid5 : 1; + uint64_t dvs6 : 12; + uint64_t spare60 : 1; + uint64_t trip6 : 1; + uint64_t spare61 : 1; + uint64_t valid6 : 1; + uint64_t dvs7 : 12; + uint64_t spare70 : 1; + uint64_t trip7 : 1; + uint64_t spare71 : 1; + uint64_t valid7 : 1; +#else + uint64_t valid7 : 1; + uint64_t spare71 : 1; + uint64_t trip7 : 1; + uint64_t spare70 : 1; + uint64_t dvs7 : 12; + uint64_t valid6 : 1; + uint64_t spare61 : 1; + uint64_t trip6 : 1; + uint64_t spare60 : 1; + uint64_t dvs6 : 12; + uint64_t valid5 : 1; + uint64_t spare51 : 1; + uint64_t trip5 : 1; + uint64_t spare50 : 1; + uint64_t dvs5 : 12; + uint64_t valid4 : 1; + uint64_t spare41 : 1; + uint64_t trip4 : 1; + uint64_t spare40 : 1; + uint64_t dvs4 : 12; +#endif // _BIG_ENDIAN + } fields; +} sensors_v12_t; + + + +typedef union sensors_v13 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t dvs8 : 12; + uint64_t spare80 : 1; + uint64_t trip8 : 1; + uint64_t spare81 : 1; + uint64_t valid8 : 1; + uint64_t dvs9 : 12; + uint64_t spare90 : 1; + uint64_t trip9 : 1; + uint64_t spare91 : 1; + uint64_t valid9 : 1; + uint64_t dvs10 : 12; + uint64_t spare100 : 1; + uint64_t trip10 : 1; + uint64_t spare101 : 1; + uint64_t valid10 : 1; + uint64_t dvs11 : 12; + uint64_t spare110 : 1; + uint64_t trip11 : 1; + uint64_t spare111 : 1; + uint64_t valid11 : 1; +#else + uint64_t valid11 : 1; + uint64_t spare111 : 1; + uint64_t trip11 : 1; + uint64_t spare110 : 1; + uint64_t dvs11 : 12; + uint64_t valid10 : 1; + uint64_t spare101 : 1; + uint64_t trip10 : 1; + uint64_t spare100 : 1; + uint64_t dvs10 : 12; + uint64_t valid9 : 1; + uint64_t spare91 : 1; + uint64_t trip9 : 1; + uint64_t spare90 : 1; + uint64_t dvs9 : 12; + uint64_t valid8 : 1; + uint64_t spare81 : 1; + uint64_t trip8 : 1; + uint64_t spare80 : 1; + uint64_t dvs8 : 12; +#endif // _BIG_ENDIAN + } fields; +} sensors_v13_t; + + +#endif // __ASSEMBLER__ +#endif // __SENSORS_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/sensors_register_addresses.h b/src/ssx/pgp/registers/sensors_register_addresses.h new file mode 100755 index 0000000..c815ace --- /dev/null +++ b/src/ssx/pgp/registers/sensors_register_addresses.h @@ -0,0 +1,47 @@ +#ifndef __SENSORS_REGISTER_ADDRESSES_H__ +#define __SENSORS_REGISTER_ADDRESSES_H__ + +// $Id: sensors_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sensors_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file sensors_register_addresses.h +/// \brief Symbolic addresses for the SENSORS unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define SENSORS_CORE_PCB_BASE 0x10050000 +#define SENSORS_V0_OFFSET 0x00000000 +#define SENSORS_CORE_V0 0x10050000 +#define SENSORS_V1_OFFSET 0x00000001 +#define SENSORS_CORE_V1 0x10050001 +#define SENSORS_V2_OFFSET 0x00000002 +#define SENSORS_CORE_V2 0x10050002 +#define SENSORS_V3_OFFSET 0x00000003 +#define SENSORS_CORE_V3 0x10050003 +#define SENSORS_V5_OFFSET 0x00000005 +#define SENSORS_CORE_V5 0x10050005 +#define SENSORS_V6_OFFSET 0x00000006 +#define SENSORS_CORE_V6 0x10050006 +#define SENSORS_V7_OFFSET 0x00000007 +#define SENSORS_CORE_V7 0x10050007 +#define SENSORS_V8_OFFSET 0x00000008 +#define SENSORS_CORE_V8 0x10050008 +#define SENSORS_V9_OFFSET 0x00000009 +#define SENSORS_CORE_V9 0x10050009 +#define SENSORS_V10_OFFSET 0x0000000a +#define SENSORS_CORE_V10 0x1005000a +#define SENSORS_V11_OFFSET 0x0000000b +#define SENSORS_CORE_V11 0x1005000b +#define SENSORS_V12_OFFSET 0x0000000c +#define SENSORS_CORE_V12 0x1005000c +#define SENSORS_V13_OFFSET 0x0000000d +#define SENSORS_CORE_V13 0x1005000d + +#endif // __SENSORS_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/sramctl_firmware_registers.h b/src/ssx/pgp/registers/sramctl_firmware_registers.h new file mode 100755 index 0000000..c8a7c26 --- /dev/null +++ b/src/ssx/pgp/registers/sramctl_firmware_registers.h @@ -0,0 +1,211 @@ +#ifndef __SRAMCTL_FIRMWARE_REGISTERS_H__ +#define __SRAMCTL_FIRMWARE_REGISTERS_H__ + +// $Id: sramctl_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sramctl_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file sramctl_firmware_registers.h +/// \brief C register structs for the SRAMCTL unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union sramctl_srbar { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t sram_region_qualifier : 2; + uint32_t reserved : 3; + uint32_t sram_bar_region : 8; + uint32_t _reserved0 : 19; +#else + uint32_t _reserved0 : 19; + uint32_t sram_bar_region : 8; + uint32_t reserved : 3; + uint32_t sram_region_qualifier : 2; +#endif // _BIG_ENDIAN + } fields; +} sramctl_srbar_t; + + + +typedef union sramctl_srmr { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t sram_enable_remap : 1; + uint32_t sram_arb_en_send_all_writes : 1; + uint32_t sram_disable_lfsr : 1; + uint32_t sram_lfsr_fairness_mask : 5; + uint32_t sram_error_inject_enable : 1; + uint32_t sram_ctl_trace_en : 1; + uint32_t sram_ctl_trace_sel : 1; + uint32_t reserved : 5; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t reserved : 5; + uint32_t sram_ctl_trace_sel : 1; + uint32_t sram_ctl_trace_en : 1; + uint32_t sram_error_inject_enable : 1; + uint32_t sram_lfsr_fairness_mask : 5; + uint32_t sram_disable_lfsr : 1; + uint32_t sram_arb_en_send_all_writes : 1; + uint32_t sram_enable_remap : 1; +#endif // _BIG_ENDIAN + } fields; +} sramctl_srmr_t; + + + +typedef union sramctl_srmap { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t reserved : 1; + uint32_t sram_remap_source : 12; + uint32_t _reserved0 : 1; + uint32_t reserved1 : 3; + uint32_t sram_remap_dest : 13; + uint32_t reserved2 : 2; +#else + uint32_t reserved2 : 2; + uint32_t sram_remap_dest : 13; + uint32_t reserved1 : 3; + uint32_t _reserved0 : 1; + uint32_t sram_remap_source : 12; + uint32_t reserved : 1; +#endif // _BIG_ENDIAN + } fields; +} sramctl_srmap_t; + + + +typedef union sramctl_srear { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t sram_error_address : 16; + uint32_t _reserved0 : 16; +#else + uint32_t _reserved0 : 16; + uint32_t sram_error_address : 16; +#endif // _BIG_ENDIAN + } fields; +} sramctl_srear_t; + + + +typedef union sramctl_srbv0 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t boot_vector_word0 : 32; +#else + uint32_t boot_vector_word0 : 32; +#endif // _BIG_ENDIAN + } fields; +} sramctl_srbv0_t; + + + +typedef union sramctl_srbv1 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t boot_vector_word1 : 32; +#else + uint32_t boot_vector_word1 : 32; +#endif // _BIG_ENDIAN + } fields; +} sramctl_srbv1_t; + + + +typedef union sramctl_srbv2 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t boot_vector_word2 : 32; +#else + uint32_t boot_vector_word2 : 32; +#endif // _BIG_ENDIAN + } fields; +} sramctl_srbv2_t; + + + +typedef union sramctl_srbv3 { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t boot_vector_word3 : 32; +#else + uint32_t boot_vector_word3 : 32; +#endif // _BIG_ENDIAN + } fields; +} sramctl_srbv3_t; + + + +typedef union sramctl_srchsw { + + uint32_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t chksw_wrfsm_dly_dis : 1; + uint32_t chksw_allow1_rd : 1; + uint32_t chksw_allow1_wr : 1; + uint32_t chksw_allow1_rdwr : 1; + uint32_t chksw_oci_parchk_dis : 1; + uint32_t chksw_tank_rddata_parchk_dis : 1; + uint32_t chksw_tank_sr_rderr_dis : 1; + uint32_t chksw_val_be_addr_chk_dis : 1; + uint32_t chksw_so_spare : 2; + uint32_t _reserved0 : 22; +#else + uint32_t _reserved0 : 22; + uint32_t chksw_so_spare : 2; + uint32_t chksw_val_be_addr_chk_dis : 1; + uint32_t chksw_tank_sr_rderr_dis : 1; + uint32_t chksw_tank_rddata_parchk_dis : 1; + uint32_t chksw_oci_parchk_dis : 1; + uint32_t chksw_allow1_rdwr : 1; + uint32_t chksw_allow1_wr : 1; + uint32_t chksw_allow1_rd : 1; + uint32_t chksw_wrfsm_dly_dis : 1; +#endif // _BIG_ENDIAN + } fields; +} sramctl_srchsw_t; + + +#endif // __ASSEMBLER__ +#endif // __SRAMCTL_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/sramctl_register_addresses.h b/src/ssx/pgp/registers/sramctl_register_addresses.h new file mode 100755 index 0000000..baec5d5 --- /dev/null +++ b/src/ssx/pgp/registers/sramctl_register_addresses.h @@ -0,0 +1,30 @@ +#ifndef __SRAMCTL_REGISTER_ADDRESSES_H__ +#define __SRAMCTL_REGISTER_ADDRESSES_H__ + +// $Id: sramctl_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/sramctl_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file sramctl_register_addresses.h +/// \brief Symbolic addresses for the SRAMCTL unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define SRAMCTL_OCI_BASE 0x40030000 +#define SRAMCTL_SRBAR 0x40030000 +#define SRAMCTL_SRMR 0x40030008 +#define SRAMCTL_SRMAP 0x40030010 +#define SRAMCTL_SREAR 0x40030018 +#define SRAMCTL_SRBV0 0x40030020 +#define SRAMCTL_SRBV1 0x40030028 +#define SRAMCTL_SRBV2 0x40030030 +#define SRAMCTL_SRBV3 0x40030038 +#define SRAMCTL_SRCHSW 0x40030040 + +#endif // __SRAMCTL_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/tod_firmware_registers.h b/src/ssx/pgp/registers/tod_firmware_registers.h new file mode 100755 index 0000000..7a700d7 --- /dev/null +++ b/src/ssx/pgp/registers/tod_firmware_registers.h @@ -0,0 +1,58 @@ +#ifndef __TOD_FIRMWARE_REGISTERS_H__ +#define __TOD_FIRMWARE_REGISTERS_H__ + +// $Id: tod_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:23 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tod_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file tod_firmware_registers.h +/// \brief C register structs for the TOD unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union tod_value_reg { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t tod_incrementer : 60; + uint64_t tod_wof : 4; +#else + uint64_t tod_wof : 4; + uint64_t tod_incrementer : 60; +#endif // _BIG_ENDIAN + } fields; +} tod_value_reg_t; + + +#endif // __ASSEMBLER__ +#endif // __TOD_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/tod_register_addresses.h b/src/ssx/pgp/registers/tod_register_addresses.h new file mode 100755 index 0000000..ac7d136 --- /dev/null +++ b/src/ssx/pgp/registers/tod_register_addresses.h @@ -0,0 +1,22 @@ +#ifndef __TOD_REGISTER_ADDRESSES_H__ +#define __TOD_REGISTER_ADDRESSES_H__ + +// $Id: tod_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tod_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file tod_register_addresses.h +/// \brief Symbolic addresses for the TOD unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define TOD_PIB_BASE 0x00040000 +#define TOD_VALUE_REG 0x00040020 + +#endif // __TOD_REGISTER_ADDRESSES_H__ + diff --git a/src/ssx/pgp/registers/tpc_firmware_registers.h b/src/ssx/pgp/registers/tpc_firmware_registers.h new file mode 100644 index 0000000..62f1c42 --- /dev/null +++ b/src/ssx/pgp/registers/tpc_firmware_registers.h @@ -0,0 +1,213 @@ +#ifndef __TPC_FIRMWARE_REGISTERS_H__ +#define __TPC_FIRMWARE_REGISTERS_H__ + +// $Id: tpc_firmware_registers.h,v 1.1.1.1 2013/12/11 21:03:25 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tpc_firmware_registers.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file tpc_firmware_registers.h +/// \brief C register structs for the TPC unit + +// *** WARNING *** - This file is generated automatically, do not edit. + +#ifndef SIXTYFOUR_BIT_CONSTANT +#ifdef __ASSEMBLER__ +#define SIXTYFOUR_BIT_CONSTANT(x) x +#else +#define SIXTYFOUR_BIT_CONSTANT(x) x##ull +#endif +#endif + +#ifndef __ASSEMBLER__ + +#include <stdint.h> + + + + +typedef union tpc_perv_gp3 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t tp_chiplet_chiplet_en_dc : 1; + uint64_t put_in_later0 : 25; + uint64_t tp_chiplet_fence_pcb_dc : 1; + uint64_t put_in_later1 : 37; +#else + uint64_t put_in_later1 : 37; + uint64_t tp_chiplet_fence_pcb_dc : 1; + uint64_t put_in_later0 : 25; + uint64_t tp_chiplet_chiplet_en_dc : 1; +#endif // _BIG_ENDIAN + } fields; +} tpc_perv_gp3_t; + + + +typedef union tpc_gp0 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t put_in_later0 : 40; + uint64_t tc_node_id_dc : 3; + uint64_t tc_chip_id_dc : 3; + uint64_t put_in_later1 : 18; +#else + uint64_t put_in_later1 : 18; + uint64_t tc_chip_id_dc : 3; + uint64_t tc_node_id_dc : 3; + uint64_t put_in_later0 : 40; +#endif // _BIG_ENDIAN + } fields; +} tpc_gp0_t; + + + +typedef union tpc_gp0_and { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t put_in_later0 : 40; + uint64_t tc_node_id_dc : 3; + uint64_t tc_chip_id_dc : 3; + uint64_t put_in_later1 : 18; +#else + uint64_t put_in_later1 : 18; + uint64_t tc_chip_id_dc : 3; + uint64_t tc_node_id_dc : 3; + uint64_t put_in_later0 : 40; +#endif // _BIG_ENDIAN + } fields; +} tpc_gp0_and_t; + + + +typedef union tpc_gp0_or { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t put_in_later0 : 40; + uint64_t tc_node_id_dc : 3; + uint64_t tc_chip_id_dc : 3; + uint64_t put_in_later1 : 18; +#else + uint64_t put_in_later1 : 18; + uint64_t tc_chip_id_dc : 3; + uint64_t tc_node_id_dc : 3; + uint64_t put_in_later0 : 40; +#endif // _BIG_ENDIAN + } fields; +} tpc_gp0_or_t; + + + +typedef union tpc_hpr2 { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t hang_pulse_reg : 6; + uint64_t suppress_hang : 1; + uint64_t _reserved0 : 57; +#else + uint64_t _reserved0 : 57; + uint64_t suppress_hang : 1; + uint64_t hang_pulse_reg : 6; +#endif // _BIG_ENDIAN + } fields; +} tpc_hpr2_t; + + + +typedef union tpc_device_id { + + uint64_t value; + struct { +#ifdef _BIG_ENDIAN + uint32_t high_order; + uint32_t low_order; +#else + uint32_t low_order; + uint32_t high_order; +#endif // _BIG_ENDIAN + } words; + struct { +#ifdef _BIG_ENDIAN + uint64_t cfam_id : 32; + uint64_t fuse_nx_allow_crypto : 1; + uint64_t fuse_vmx_crypto_dis : 1; + uint64_t fuse_fp_throttle_en : 1; + uint64_t reserved32 : 1; + uint64_t socket_id : 3; + uint64_t chippos_id : 1; + uint64_t _reserved0 : 24; +#else + uint64_t _reserved0 : 24; + uint64_t chippos_id : 1; + uint64_t socket_id : 3; + uint64_t reserved32 : 1; + uint64_t fuse_fp_throttle_en : 1; + uint64_t fuse_vmx_crypto_dis : 1; + uint64_t fuse_nx_allow_crypto : 1; + uint64_t cfam_id : 32; +#endif // _BIG_ENDIAN + } fields; +} tpc_device_id_t; + + +#endif // __ASSEMBLER__ +#endif // __TPC_FIRMWARE_REGISTERS_H__ + diff --git a/src/ssx/pgp/registers/tpc_register_addresses.h b/src/ssx/pgp/registers/tpc_register_addresses.h new file mode 100644 index 0000000..50c7e97 --- /dev/null +++ b/src/ssx/pgp/registers/tpc_register_addresses.h @@ -0,0 +1,30 @@ +#ifndef __TPC_REGISTER_ADDRESSES_H__ +#define __TPC_REGISTER_ADDRESSES_H__ + +// $Id: tpc_register_addresses.h,v 1.1.1.1 2013/12/11 21:03:24 bcbrock Exp $ +// $Source: /afs/awd/projects/eclipz/KnowledgeBase/.cvsroot/eclipz/chips/p8/working/procedures/ssx/pgp/registers/tpc_register_addresses.h,v $ +//----------------------------------------------------------------------------- +// *! (C) Copyright International Business Machines Corp. 2013 +// *! All Rights Reserved -- Property of IBM +// *! *** IBM Confidential *** +//----------------------------------------------------------------------------- + +/// \file tpc_register_addresses.h +/// \brief Symbolic addresses for the TPC unit + +// *** WARNING *** - This file is generated automatically, do not edit. + + +#define TPC_PERVPIB_BASE 0x00050000 +#define TPC_PERV_GP3 0x0005001b +#define TPC_PIB_BASE 0x01000000 +#define TPC_GP0 0x01000000 +#define TPC_GP0_AND 0x01000004 +#define TPC_GP0_OR 0x01000005 +#define TPC_MISCPIB_BASE 0x010f0000 +#define TPC_HPR2 0x010f0022 +#define TPC_TPCHIP_BASE 0x000f0000 +#define TPC_DEVICE_ID 0x000f000f + +#endif // __TPC_REGISTER_ADDRESSES_H__ + |
