diff options
Diffstat (limited to 'src/ppe/hwp/core')
31 files changed, 2682 insertions, 0 deletions
diff --git a/src/ppe/hwp/core/Makefile b/src/ppe/hwp/core/Makefile new file mode 100644 index 0000000..9842d1f --- /dev/null +++ b/src/ppe/hwp/core/Makefile @@ -0,0 +1,54 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/core/Makefile $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the core hardware procedure code. See the +# "corehcdfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/cache +export SUB_OBJDIR = /core + +include img_defs.mk +include corehcdfiles.mk + + +OBJS := $(addprefix $(OBJDIR)/, $(CACHE_OBJECTS)) + +libcore.a: core + $(AR) crs $(OBJDIR)/libcore.a $(OBJDIR)/*.o + +.PHONY: clean core +core: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/ppe/hwp/core/corehcdfiles.mk b/src/ppe/hwp/core/corehcdfiles.mk new file mode 100644 index 0000000..364de0c --- /dev/null +++ b/src/ppe/hwp/core/corehcdfiles.mk @@ -0,0 +1,65 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/core/corehcdfiles.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file corehcdfiles.mk +# +# @brief mk for including core hcode object files +# +# @page ChangeLogs Change Logs +# @section corehcdfiles.mk +# @verbatim +# +# +# Change Log ****************************************************************** +# Flag Defect/Feature User Date Description +# ------ -------------- ---------- ------------ ----------- +# +# @endverbatim +# +########################################################################## +# Object Files +########################################################################## + +CACHE-CPP-SOURCES += p9_hcd_core_arrayinit.C +CACHE-CPP-SOURCES += p9_hcd_core_chiplet_init.C +CACHE-CPP-SOURCES += p9_hcd_core_chiplet_reset.C +CACHE-CPP-SOURCES += p9_hcd_core_gptr_time_initf.C +CACHE-CPP-SOURCES += p9_hcd_core_initf.C +CACHE-CPP-SOURCES += p9_hcd_core_occ_runtime_scom.C +CACHE-CPP-SOURCES += p9_hcd_core_pcb_arb.C +CACHE-CPP-SOURCES += p9_hcd_core_poweron.C +CACHE-CPP-SOURCES += p9_hcd_core_ras_runtime_scom.C +CACHE-CPP-SOURCES += p9_hcd_core_repair_initf.C +CACHE-CPP-SOURCES += p9_hcd_core_runinit.C +CACHE-CPP-SOURCES += p9_hcd_core_scomcust.C +CACHE-CPP-SOURCES += p9_hcd_core_scominit.C +CACHE-CPP-SOURCES += p9_hcd_core_startclocks.C + +CACHE-C-SOURCES += +CACHE-S-SOURCES += + +CACHE_OBJECTS += $(CACHE-CPP-SOURCES:.C=.o) +CACHE_OBJECTS += $(CACHE-C-SOURCES:.c=.o) +CACHE_OBJECTS += $(CACHE-S-SOURCES:.S=.o) + diff --git a/src/ppe/hwp/core/p9_hcd_core.H b/src/ppe/hwp/core/p9_hcd_core.H new file mode 100644 index 0000000..a96280f --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core.H @@ -0,0 +1,54 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core.H +/// @brief Core Chiplet Procedure Includes +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_H__ +#define __P9_HCD_CORE_H__ + +#include <p9_hcd_core_arrayinit.H> +#include <p9_hcd_core_chiplet_init.H> +#include <p9_hcd_core_chiplet_reset.H> +#include <p9_hcd_core_gptr_time_initf.H> +#include <p9_hcd_core_initf.H> +#include <p9_hcd_core_occ_runtime_scom.H> +#include <p9_hcd_core_pcb_arb.H> +#include <p9_hcd_core_poweron.H> +#include <p9_hcd_core_ras_runtime_scom.H> +#include <p9_hcd_core_repair_initf.H> +#include <p9_hcd_core_runinit.H> +#include <p9_hcd_core_scomcust.H> +#include <p9_hcd_core_scominit.H> +#include <p9_hcd_core_startclocks.H> + +#endif // __P9_HCD_CORE_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_arrayinit.C b/src/ppe/hwp/core/p9_hcd_core_arrayinit.C new file mode 100644 index 0000000..58c6ecc --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_arrayinit.C @@ -0,0 +1,156 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_arrayinit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_arrayinit.C +/// @brief Core Initialize arrays +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Use ABIST engine to zero out all arrays +/// Upon completion, scan0 flush all rings except Vital,Repair,GPTR,and TIME +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_arrayinit.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Core Initialize arrays +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_arrayinit( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) + +{ + +#if 0 + fapi2::buffer<uint64_t> data; + + // Procedure Prereq : P0 is pointing to the targeted EX chiplet + // submodules: + // seeprom_array_init_module + // ex_scan0 + + FAPI_INF("<p9_hcd_core_arrayinit> : \ + *** Array Init and Scan0 Cleanup for EX Chiplets ***"); + + // SBE Address Base Register Setups + // Setup PRV_BASE_ADDR1; points to selected EX chiplet + // - mr P1, P0 + FAPI_INF("<p9_hcd_core_arrayinit> : \ + Copy selected EX info from P0 to P1"); + + // Step 1: Array Init for selected EX chiplet + // ARRAY INIT module -> see p9_sbe_tp_array_init.S + // + // At entry: + // + // P1 : The chiplet ID/Multicast Group + // D1 : Clock Regions for Array Init + // + // At exit: + // + // P0, D0, D1, CTR : destroyed + // P1, A0, A1 : maintained + // + FAPI_INF("<p9_hcd_core_arrayinit> : \ + Calling Array Init Subroutine"); + + // >>> Sleep + // - li D1, SCAN_CLK_CORE_ONLY + + // Execute the array init + // - bsr seeprom_array_init_module + + // Restore P0 with selected EX chiplet info + // - mr P0, P1 + FAPI_INF("<p9_hcd_core_arrayinit> : \ + Copy selected EX info back from P1 to P0"); + + // Step 2: Scan0 for selected EX chiplet except PRV, GPTR, TIME and DPLL + FAPI_INF("<p9_hcd_core_arrayinit> : \ + Calling Scan0 Subroutine"); + + // taken from p9_sbe_ex_chiplet_init + + // >>> Sleep scan flush - core only + + // Hook to bypass in Sim + // - hooki 0, 0xFF04 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,2f + + FAPI_DBG("EX ArrayInit: Scan0 Module executed: \ + Scan all core chains except GPTR and TIME"); + + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the + // the longest ring is defined by P9_SCAN0_FUNC_REPEAT. When the design + // ALWAYS has all stumps less than 8191, the repeat (eg .rept) can be + // removed. + // Implementation note: this is not done in a loop (or included in the + // ex_scan0_module itself) as the D0 and D1 registers are used in + // ex_scan0_module and there is no convenient place to temporaily store + // the 2-64b values values. Argueably, PIBMEM could be used for this + // but was not utilized. + + // - .rept P9_SCAN0_FUNC_REPEAT + // - ex_scan0 SCAN_CORE_ALL_BUT_GPTRTIMEREP, SCAN_CLK_CORE_ONLY + // - .endr + // - 2: + + FAPI_INF("<p9_hcd_core_arrayinit> : \ + *** End of Procedure ***"); + + return fapi2::FAPI2_RC_SUCCESS; + +clean_up: + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_arrayinit.H b/src/ppe/hwp/core/p9_hcd_core_arrayinit.H new file mode 100644 index 0000000..b0eeb5e --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_arrayinit.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_arrayinit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_arrayinit.H +/// @brief Core Initialize arrays +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_ARRAYINIT_H__ +#define __P9_HCD_CORE_ARRAYINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_arrayinit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_arrayinit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +/// @brief Core Initialize arrays +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_arrayinit( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_ARRAYINIT_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_chiplet_init.C b/src/ppe/hwp/core/p9_hcd_core_chiplet_init.C new file mode 100644 index 0000000..3d3763a --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_chiplet_init.C @@ -0,0 +1,136 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_chiplet_init.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_chiplet_init.C +/// @brief Core Flush/Initialize +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Switch the core glitchless mux to allow DPLL clocks on the clock grid +/// Scan0 flush all chiplet rings except VITAL, GPTR and TIME +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_chiplet_init.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ +//#define SIM_PLL +//#define SIM_SPEEDUP +////#define SCAN0_DISABLE +//#define STEP_CHIPLET_INIT_0 0x0 // Resetting DPLL +//#define STEP_CHIPLET_INIT_1 0x1 // Core+ECO glmux switch (IPL/Winkle) +//#define STEP_CHIPLET_INIT_2 0x2 // Core glmux switch (Sleep) +//#define STEP_CHIPLET_INIT_3 0x3 // Before Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_4 0x4 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_5 0x5 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_6 0x6 // Before Core GPTR flush for Sleep +//#define STEP_CHIPLET_INIT_7 0x7 // After Core GPTR flush for Sleep +//#define STEP_CHIPLET_INIT_8 0x8 // Before Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_9 0x9 // After Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_A 0xA // Before Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_B 0xB // After Core Func flush for Sleep +//#define PORE_REFCLK_CYCLES 1 // \todo need real value for hdw +//#define DPLL_LOCK_DELAY 8192*PORE_REFCLK_CYCLES + +//------------------------------------------------------------------------------ +// Procedure: Core Flush/Initialize +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_chiplet_init( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + +#if 0 + + fapi2::buffer<uint64_t> data; + + // Procedure Prereq: + // p9_sbe_ex_chiplet_reset, p9_sbe_ex_dpll_initf, p9_sbe_ex_pll_initf + + FAPI_INF("<p9_hcd_cache_chiplet_init>: Entering procedure"); + + // Look for PSCOM error on any chip, fail if we find one + // scan0 flush all configured chiplet rings except EX DPLL + // call ex_scan0_module( ) + + // >>> Sleep GPTR flush - core only + // This is done after the swing of the Glitchless Mux above + // Hook to bypass in sim while providing a trace + + // Hook to bypass in sim while providing a trace + // - hooki 0, 0xFF04 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + FAPI_DBG("EX Reset: Scan0 Module executed for Sleep: \ + Scan the all but GPTR/TIME/REP rings"); + + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the + // the longest ring is defined by P9_SCAN0_FUNC_REPEAT. When the design + // ALWAYS has all stumps less than 8191, the repeat (eg .rept) can be + // removed. + // Implementation note: this is not done in a loop (or included in the + // ex_scan0_module itself) as the D0 and D1 registers are used in + // ex_scan0_module and there is no convenient place to temporaily store + // the 2-64b values values. Argueably, PIBMEM could be used for this + // but was not utilized. + // - updatestep STEP_CHIPLET_INIT_A, D0, P1 + // - .rept P9_SCAN0_FUNC_REPEAT + // - ex_scan0 SCAN_CORE_ALL_BUT_GPTRTIMEREP, SCAN_CLK_CORE_ONLY + // - .endr + // - updatestep STEP_CHIPLET_INIT_B, D0, P1 + // - 1: + + FAPI_INF("<p9_hcd_cache_chiplet_init>: Exiting procedure"); + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/core/p9_hcd_core_chiplet_init.H b/src/ppe/hwp/core/p9_hcd_core_chiplet_init.H new file mode 100644 index 0000000..be081ef --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_chiplet_init.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_chiplet_init.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_chiplet_init.H +/// @brief Core Flush/Initialize +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_CHIPLET_INIT_H__ +#define __P9_HCD_CORE_CHIPLET_INIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_chiplet_init_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_chiplet_init_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief Core Flush/Initialize +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_chiplet_init( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_CHIPLET_INIT_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_chiplet_reset.C b/src/ppe/hwp/core/p9_hcd_core_chiplet_reset.C new file mode 100644 index 0000000..1874f0f --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_chiplet_reset.C @@ -0,0 +1,196 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_chiplet_reset.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_chiplet_reset.C +/// @brief Core Chiplet Reset +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Reset chiplet logic +/// (TODO: check with Andreas on the effect of a CME based Endpoint reset +/// relative to the CorePPM path) +/// Scan0 flush entire core chiplet +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_chiplet_reset.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +// GP3 Bits +// 1 - PCB_EP_RESET +// 2 - GLMMUX Reset +// 3 - PLL_TEST Enable +// 4 - PLLRST - PLL Reset +// 5 - PLL Bypass +// 11 - D_MODE for Vital +// 13 - MPW2 for Vital +// 14 - PMW1 for Vital +// 18 - FENCE_EN for chiplet +// 22 - Resonant Clock disable +// 23:24 - Glitchless Mux Sel +// 25: - ?? (set because System Pervasive flow does this) +// Background: system pervasive as the following setting in their tests: +// 7C1623C000000000 +// Bits set: +// 1, 2, 3, 4, 5, 11, 13, 14, 18, 22, 23, 24, 25 +//#define GP3_INIT_VECTOR (BITS(1,5)|BIT(11)|BIT(13)|BIT(14)|BIT(18)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) + +// hang counter inits +//#define HANG_P1_INIT 0x0400000000000000 +//#define PCB_SL_ERROR_REG_RESET 0xFFFFFFFFFFFFFFFF +//#define STEP_CHIPLET_RESET_1 0x1 // After start of vital clocks +//#define STEP_CHIPLET_RESET_2 0x2 // After fence drop +//#define STEP_CHIPLET_RESET_3 0x3 // Before GPTR flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_4 0x4 // After GPTR flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_5 0x5 // Before Func flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_6 0x6 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_7 0x7 // Before GPTR flush for Sleep +//#define STEP_CHIPLET_RESET_8 0x8 // After GPTR flush for Sleep + +//------------------------------------------------------------------------------ +// Procedure: Core Chiplet Reset +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_chiplet_reset( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + + ///////////////////////////////////////////////////////////////// + // repeat some init steps of chiplet_init + ///////////////////////////////////////////////////////////////// + + // If there is a unused, powered-off EX chiplet which needs to be + // configured in the following steps to setup the PCB endpoint. + + // Skip the PCB endpoint config steps for sleep so that fences don't + // get dropped (eg by dropping chiplet_enable (GP3(0)). + + // The following is performed for both IPL/Winkle and Sleep + + // Note: These are executed for sleep as well as these fences will have + // already been dropped + + FAPI_DBG("<p9_hcd_core_chiplet_reset>: \ + Remove pervasive ECO fence;"); + // ECO Fence in 22 + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(22)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer<uint64_t>().flush<1>().clearBit<22>())); + + FAPI_DBG("<p9_hcd_core_chiplet_reset>: \ + Remove winkle mode before scan0 on EX chiplets is executed"); + // PM Exit States: WINKLE_EXIT_DROP_ELEC_FENCE + + FAPI_DBG("<p9_hcd_core_chiplet_reset>: \ + Remove logical pervasive/pcbs-pm fence"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(39)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer<uint64_t>().flush<1>().clearBit<39>())); + + FAPI_DBG("<p9_hcd_core_chiplet_reset>: \ + Remove PB Winkle Electrical Fence GP3(27)"); + // = sti EX_GP3_AND_0x100F0013,P0,~(BIT(27)) + FAPI_TRY(putScom(i_target, EX_GP3_AND_0x100F0013, + fapi2:buffer<uint64_t>().flush<1>().clearBit<27>())); + + FAPI_DBG("<p9_hcd_core_chiplet_reset>: \ + Configuring chiplet hang counters") ; + // = sti EX_HANG_P1_0x100F0021,P0,HANG_P1_INIT + FAPI_TRY(putScom(i_target, EX_HANG_P1_0x100F0021, HANG_P1_INIT)); + // - updatestep STEP_CHIPLET_RESET_2, D0, P1 + + ////////////////////////////////////////////////////////////// + // perform scan0 module for pervasive chiplet (GPTR_TIME_REPR) + ////////////////////////////////////////////////////////////// + + // For the Sleep case, the DPLL is running but the core mesh is force to + // the "constant" or "off" state. In order to flush or scan, the mesh must + // be reenabled via the Glitchless Mux. + + // Read-modify-write (vs sti AND and sti OR) is done so that glitchless + // mux change field change is atomic (eg 1 store) + // - setp1_mcreadand D1 + // = ld D1,EX_PMGP0_0x100F0100,P1 + FAPI_TRY(fapi2::getScom(i_target, EX_PMGP0_0x100F0100, data)); + + // Set the core glitchless mux to use the primary input (b00). + // Upon Sleep entry, hardware will switch the glitchless mux to 0b10 + // (constant). EX PM GP0 bits 32-33) + FAPI_INF("EX Chiplet -> Set glitchless mux select for core domain to 00 ") + // = andi D1, D1, ~(BIT(32)|BIT(33)) + + // Store the final result to the hardware + // = std D1,EX_PMGP0_0x100F0100,P0 + data.insertFromRight<32,2>(0x0); + FAPI_TRY(putScom(i_target, EX_PMGP0_0x100F0100, data)); + // - updatestep STEP_CHIPLET_RESET_7, D0, P1 + + // Hook to bypass in sim while providing a trace + // - hooki 0, 0xFF03 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + FAPI_DBG("EX Reset: Scan0 Module executed for Sleep: \ + Scan the GPTR/TIME/REP rings"); + + // - .rept P9_SCAN0_GPTR_REPEAT + // - ex_scan0 SCAN_CORE_GPTR_TIME_REP, SCAN_CLK_CORE_ONLY + // - .endr + // - 1: + // - updatestep STEP_CHIPLET_RESET_8, D0, P1 + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/core/p9_hcd_core_chiplet_reset.H b/src/ppe/hwp/core/p9_hcd_core_chiplet_reset.H new file mode 100644 index 0000000..6d95c93 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_chiplet_reset.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_chiplet_reset.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_chiplet_reset.H +/// @brief Core Chiplet Reset +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_CHIPLET_RESET_H__ +#define __P9_HCD_CORE_CHIPLET_RESET_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_chiplet_reset_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_chiplet_reset_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief Core Chiplet Reset +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_chiplet_reset( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_CHIPLET_RESET_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.C b/src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.C new file mode 100644 index 0000000..e6b54ed --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.C @@ -0,0 +1,112 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_gptr_time_initf.C +/// @brief Load Core GPTR and Time rings +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// to produce #G VPD contents +/// Check for the presence of core override GPTR ring from image +/// (this is new for P9) +/// if found, apply; if not, apply core GPTR from image +/// Check for the presence of core override TIME ring from image; +/// if found, apply; if not, apply core base TIME from image +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_gptr_time_initf.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Load Core GPTR and Time rings +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_gptr_time_initf( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + +#if 0 + + // >>> For sleep, bypass the pull back of the scan ratio + // - ifsleep D0, 1f + // Set EX scan ratio to 1:1 as EX is still at refclock + FAPI_INF("<p9_hcd_core_gptr_time_initf> : \ + Set EX scan ratio to 1:1 ...") + // = sti EX_OPCG_CNTL0_0x10030002, P0, 0x0 + FAPI_TRY(fapi2::putScom(i_target, EX_OPCG_CNTL0_0x10030002, 0x0)); + // - 1: + + // scan ring content shared among all chiplets + FAPI_DBG("Scanning EX core GPTR rings...") + // - load_ring ex_gptr_core skipoverride=1 + // - load_ring ex_gptr_l2 skipoverride=1 + + // scan chiplet specific ring content + FAPI_DBG("Scanning EX core TIME rings...") + // - load_ring_vec_ex ex_time_core + + // Set EX scan ratio back to 8:1 + FAPI_INF("<p9_hcd_core_gptr_time_initf> : \ + Set EX scan ratio to 8:1 ...") + //Inputs: A1 and P0 and D0, destroys D0 & D1 + // - .pibmem_port (PORE_SPACE_PIBMEM & 0xf) + // - lpcs P1, PIBMEM0_0x00080000 + // - ld D0, ex_scan_ratio_override, P1 + // - bsr set_scan_ratio_d0 + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.H b/src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.H new file mode 100644 index 0000000..881f493 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_gptr_time_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_gptr_time_initf.H +/// @brief Load Core GPTR and Time rings +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_GPTR_TIME_INIT_H__ +#define __P9_HCD_CORE_GPTR_TIME_INIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_gptr_time_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_gptr_time_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +/// @brief Load Core GPTR and Time rings +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem ATTR_CORE_GPTR_TIME_RING - EC target, uint32 +/// pointer to RS4 content<br> +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_gptr_time_initf( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_GPTR_TIME_INIT_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_initf.C b/src/ppe/hwp/core/p9_hcd_core_initf.C new file mode 100644 index 0000000..fad2046 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_initf.C @@ -0,0 +1,95 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_initf.C +/// @brief Core scan init +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// Check for the presence of core FUNC override rings from image; +/// if found, apply; if not, apply core base FUNC rings from image +/// Note: FASTINIT ring (eg CMSK ring) is setup at this point to limit the +/// stumps that participate in FUNC ring scanning (this is new for P9). +/// (TODO to make sure the image build support is in place) +/// Note : if in fused mode, both core rings will be initialized to the same +/// values via multicast scans +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_initf.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Core scan init +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_initf( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + +#if 0 + + fapi2::buffer<uint64_t> data; + + // - load_ring ex_func_core conditional_override=1 + // - load_ring ex_regf_core conditional_override=1 + // - load_ring ex_fary_l2 conditional_override=1 + // - load_ring ex_lbst_core conditional_override=1 + // - load_ring ex_abfa_core conditional_override=1 + // - load_ring ex_cmsk_core conditional_override=1 + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_initf.H b/src/ppe/hwp/core/p9_hcd_core_initf.H new file mode 100644 index 0000000..7a9682d --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_initf.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_initf.H +/// @brief Core scan init +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_INITF_H__ +#define __P9_HCD_CORE_INITF_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief Core scan init +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem ATTR_CORE_FUNC_RING - EC target, uint32 +/// pointer to RS4 content<br> +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_initf( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_INITF_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.C b/src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.C new file mode 100644 index 0000000..ccc4c0e --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.C @@ -0,0 +1,94 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_occ_runtime_scom.C +/// @brief Core OCC runtime SCOMS +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates from OCC code that are put somewhere TBD +/// (TODO . revisit with OCC FW team) +/// OCC FW sets up value in the TBD SCOM section +/// This was not leverage in P8 with the demise of CPMs +/// Placeholder at this point +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_occ_runtime_scom.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- +#define host_runtime_scom 0 + +//----------------------------------------------------------------------------- +// Procedure: Core OCC runtime SCOMS +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_occ_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + +#if 0 + + fapi2::buffer<uint64_t> data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, occ_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + //FAPI_INF("Launching OCC Runtime SCOM routine") + // - bsrd D0 + // - 1: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.H b/src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.H new file mode 100644 index 0000000..0221370 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_occ_runtime_scom.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_occ_runtime_scom.H +/// @brief Core OCC runtime SCOMS +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__ +#define __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_occ_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_occ_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief Core OCC runtime SCOMS +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem ATTR_CORE_OCC_SCOM_LOC - EC target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_occ_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_OCC_RUNTIME_SCOM_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_pcb_arb.C b/src/ppe/hwp/core/p9_hcd_core_pcb_arb.C new file mode 100644 index 0000000..4dbf22e --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_pcb_arb.C @@ -0,0 +1,83 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_pcb_arb.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_pcb_arb.C +/// @brief Core Chiplet PCB Arbitration +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// If CME, +/// 1.Request PCB Mux, via write to PCB_MUX_REQ_C0 @ CCSCR_OR +/// - setBit(5) @ CME_LOCAL_CORE_STOP_CONTROL_REGISTER_OR_0510 +/// 2.Poll for PCB Mux grant, via read from +/// Polled Timeout: ns +/// - getBit() @ +/// Else (SBE), +/// Nop (as the CME is not running in bringing up the first Core) +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_pcb_arb.H" + +//----------------------------------------------------------------------------- +// Constant Definitions: Core Chiplet PCB Arbitration +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_pcb_arb( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + +#if 0 + + fapi2::buffer<uint64_t> data; + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/core/p9_hcd_core_pcb_arb.H b/src/ppe/hwp/core/p9_hcd_core_pcb_arb.H new file mode 100644 index 0000000..4029514 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_pcb_arb.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_pcb_arb.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_pcb_arb.H +/// @brief Core Chiplet PCB Arbitration +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_PCB_ARB_H__ +#define __P9_HCD_CORE_PCB_ARB_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_pcb_arb_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_pcb_arb_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +/// @brief Core Chiplet PCB Arbitration +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_pcb_arb( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_PCB_ARB_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_poweron.C b/src/ppe/hwp/core/p9_hcd_core_poweron.C new file mode 100644 index 0000000..e215c27 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_poweron.C @@ -0,0 +1,84 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_poweron.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_poweron.C +/// @brief Core Chiplet Power-on +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// 1.Command the core PFET controller to power-on, via putscom to CPPM +/// - +/// 2.Check for valid power on completion, via getscom from CPPM +/// Polled Timeout: 100us +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_poweron.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Core Chiplet Power-on +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_poweron( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint32_t i_operation) +{ + +#if 0 + + fapi2::buffer<uint64_t> data; + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/core/p9_hcd_core_poweron.H b/src/ppe/hwp/core/p9_hcd_core_poweron.H new file mode 100644 index 0000000..970d1e4 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_poweron.H @@ -0,0 +1,67 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_poweron.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_poweron.H +/// @brief Core Chiplet Power-on +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_POWERON_H__ +#define __P9_HCD_CORE_POWERON_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_poweron_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_poweron_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&, + const uint32_t); + + +/// @brief Core Chiplet Power-on +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @param [in] i_operation ENUM(ON,OFF) +/// +/// @attr +/// @attritem ATTR_PFET_* +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_poweron( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target, + const uint32_t i_operation); + + +} // extern C + +#endif // __P9_HCD_CORE_POWERON_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.C b/src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.C new file mode 100644 index 0000000..654e24e --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.C @@ -0,0 +1,165 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_ras_runtime_scom.C +/// @brief FSP/Host run-time SCOMS +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates from FSP based PRD, etc that are put on the core image +/// by STOP API calls +/// Dynamically built pointer where a NULL is checked before execution +/// If NULL (the SBE case), return +/// Else call the function at the pointer; +/// pointer is filled in by STOP image build +/// Run-time updates from Host code that are put on the core image by +/// STOP API calls +/// Restore Hypervisor, Host PRD, etc. SCOMs +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_ras_runtime_scom.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- +#define host_runtime_scom 0 + +//----------------------------------------------------------------------------- +// Procedure: FSP/Host run-time SCOMS +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_ras_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, sp_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + //FAPI_INF("Launching SP Runtime SCOM routine") + // - bsrd D0 + // - 1: + // + + // Run the SCOM sequence if the SCOM procedure is defined. + // - la A0, host_runtime_scom + // - ld D1, 0, A0 + // - braz D1, 1f + + // Prep P1 + // - setp1_mcreadand D0 +#if 0 + // Disable the AISS to allow the override + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - andi D0, D0, ~(BIT(1)) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts + // RAMs (SCOMs actually) in the IPL "Nap" state + // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // - ori D0, D0, (BIT(15)) + // - andi D0, D0, ~(BIT(21)) + // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 +#endif + // Branch to sub_slw_runtime_scom() + FAPI_INF("Launching Host Runtime SCOM routine") + // - bsrd D1 + + // Prep P1 + // - setp1_mcreadand D0 +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // - andi D0, D0, ~(BIT(15)) + // - ori D0, D0, BIT(21) + // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - ori D0, D0, (BIT(1)) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + // - bra 2f + // - 1: + // To accomodate IPL flow, where sub_slw_runtime_scom() is skipped + // - setp1_mcreadand D0 +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - andi D0, D0, ~BIT(1) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // - andi D0, D0, ~(BIT(15)) + // - ori D0, D0, BIT(21) + // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - ori D0, D0, (BIT(1)) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + // - 2: + + // If using cv_multicast, we need to set the magic istep number here + // - la A0, p9_sbe_select_ex_control + // - ldandi D0, 0, A0, P9_CONTROL_INIT_ALL_EX + // - braz D0, 3f + FAPI_DBG("Setting istep num to magic number because cv_multicast is set") + // - lpcs P1, MBOX_SBEVITAL_0x0005001C + // - sti MBOX_SBEVITAL_0x0005001C, P1, (P9_SBE_EX_RAS_RUNTIME_SCOM_MAGIC_ISTEP_NUM << (4+32)) + // - 3: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.H b/src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.H new file mode 100644 index 0000000..aca5bc2 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_ras_runtime_scom.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_ras_runtime_scom.H +/// @brief FSP/Host run-time SCOMS +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__ +#define __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_ras_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_ras_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief FSP/Host run-time SCOMS +/// +/// @param [in] i_target TARGET_TYPE_CORE target +// +/// @attr +/// @attritem ATTR_CORE_RAS_SCOM_LOC - EC target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_ras_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_RAS_RUNTIME_SCOM_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_repair_initf.C b/src/ppe/hwp/core/p9_hcd_core_repair_initf.C new file mode 100644 index 0000000..167c84e --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_repair_initf.C @@ -0,0 +1,89 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_repair_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_repair_initf.C +/// @brief Load Repair ring for core +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Load core ring images from that came from MVPD into the image +/// These rings must contain ALL chip customization data. This includes the +/// following: Array Repair and DTS calibration settings +/// Historically this was stored in MVPD keywords are #R, #G. Still stored +/// in MVPD, but SBE image is customized with rings for booting cores +/// at build time +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_repair_initf.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Load Repair ring for core +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_repair_initf( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + +#if 0 + + fapi2::buffer<uint64_t> data; + + // scan chiplet specific ring content + //FAPI_DBG("Scanning EX core REPAIR rings...") + // - load_ring_vec_ex ex_repr_core + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/core/p9_hcd_core_repair_initf.H b/src/ppe/hwp/core/p9_hcd_core_repair_initf.H new file mode 100644 index 0000000..7c9b831 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_repair_initf.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_repair_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_repair_initf.H +/// @brief Load Repair ring for core +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_REPAIR_INITF_H__ +#define __P9_HCD_CORE_REPAIR_INITF_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_repair_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_repair_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief Load Repair ring for core +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem ATTR_CORE_REPAIR_RING - EC target, uint32 +/// pointer to RS4 content +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_repair_initf( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_REPAIR_INITF_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_runinit.C b/src/ppe/hwp/core/p9_hcd_core_runinit.C new file mode 100644 index 0000000..eedc0fe --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_runinit.C @@ -0,0 +1,75 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_runinit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_runinit.C +/// @brief execute all core init procedures +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_runinit.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_runinit( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + return fapi2::FAPI2_RC_SUCCESS; + +#if 0 + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_runinit.H b/src/ppe/hwp/core/p9_hcd_core_runinit.H new file mode 100644 index 0000000..09881a8 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_runinit.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_runinit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_runinit.H +/// @brief execute all core init procedures +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_RUNINIT_H__ +#define __P9_HCD_CORE_RUNINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_runinit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_runinit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + + +/// @brief Core Customization SCOMs +/// +/// @param [in] i_target TARGET_TYPE_PROC_CHIP target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_runinit( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_RUNINIT_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_scomcust.C b/src/ppe/hwp/core/p9_hcd_core_scomcust.C new file mode 100644 index 0000000..11a1c15 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_scomcust.C @@ -0,0 +1,83 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_scomcust.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_scomcust.C +/// @brief Core Customization SCOMs +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Dynamically built (and installed) routine that is inserted by the .XIP +/// Customization. process. (New for P9) (TODO: this part of the process is +/// a placeholder at this point) +/// Dynamically built pointer where a NULL is checked before execution +/// If NULL (a potential early value); return +/// Else call the function at the pointer; +/// pointer is filled in by XIP Customization +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_scomcust.H" + +//----------------------------------------------------------------------------- +// Constant Definitions: Core Customization SCOMs +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_scomcust( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + +#if 0 + + fapi2::buffer<uint64_t> data; + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/core/p9_hcd_core_scomcust.H b/src/ppe/hwp/core/p9_hcd_core_scomcust.H new file mode 100644 index 0000000..b9643c6 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_scomcust.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_scomcust.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_scomcust.H +/// @brief Core Customization SCOMs +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_SCOMCUST_H__ +#define __P9_HCD_CORE_SCOMCUST_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_scomcust_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_scomcust_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief Core Customization SCOMs +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_scomcust( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + +} // extern C + +#endif // __P9_HCD_CORE_SCOMCUST_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_scominit.C b/src/ppe/hwp/core/p9_hcd_core_scominit.C new file mode 100644 index 0000000..3d4030d --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_scominit.C @@ -0,0 +1,160 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_scominit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_scominit.C +/// @brief Core SCOM Inits +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Apply any coded SCOM initialization to core +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_scominit.H" + + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Core SCOM Inits +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_scominit( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + + /////////////////// + // Core + /////////////////// + + // Force the hardware to think we're in special wakeup so the SCOMs will + // succeed to the core due to the init state of Nap. This does NOT + // influence the PM state machines; only the wire indicating special + // wake-up using the override in PMGP1 + // Bit 6 enables/disables override; bit 8 controls the Special Wake-up + // = sti EX_PMGP1_OR_0x100F0105, P0, BIT(6) | BIT(8) + FAPI_TRY(putScom(i_target, EX_PMGP1_OR_0x100F0105, + fapi2:buffer<uint64_t>().insertFromRight<6,3>(0x5))); + // - setp1_mcreadand D0 +#if 0 + // Disable the AISS to allow the override + // - ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // - andi D0, D0, ~(BIT(1)) + // - std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts + // RAMs (SCOMs actually) in the IPL "Nap" state + // - ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // - ori D0, D0, (BIT(15)) + // - andi D0, D0, ~(BIT(21)) + // - std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 +#endif + //CMO-> Should prob reenable AISS here. But carefully... + + // These are dropped in p9_sbe_ex_host_runtime_scom.S + + /////////////////// + // Clock Controller + /////////////////// + + // Set the OPCG_PAD_VALUE to be fast enough to not allow overrun by the + // OHA in for Deep Sleep Exit. Set for 32 cycles (2 x 16) -> 0b010 + FAPI_INF("Setup OPCG_PAD_VALUE for Deep Sleep scanning ...") + // - ld D1, EX_OPCG_CNTL2_0x10030004, P1 + // - andi D1, D1, ~(BITS(49,3)) + // - ori D1, D1, BIT(50) + // - std D1, EX_OPCG_CNTL2_0x10030004, P0 + FAPI_TRY(getScom(i_target, EX_OPCG_CNTL2_0x10030004, data)); + data.insertFromRight<49,3>(0x2); + FAPI_TRY(putScom(i_target, EX_OPCG_CNTL2_0x10030004, data)); + + /////////////////// + // L2 + /////////////////// + + // set L2 inits to force single member mode if required + FAPI_DBG("Configuring L2 single member mode ..."); + // - l2_single_member + + // set L2 inits to disable L3 if required + FAPI_DBG("Configuring L3 disable ..."); + // - l3_setup L3_SETUP_ACTION_DISABLE, L3_SETUP_UNIT_L2 + + /////////////////// + // DTS + /////////////////// + + // As this routine get runs for IPL, Winkle and Sleep, all Digital + // Thermal Sensor setup is done here. + // For the case of Sleep where the L3 DTS is still active, the + // initialization is redone anyway as, while this operation is going on, + // the atomic lock prevents other entities (eg OCC) from accessing it. + // This keep the flows the same. + + // - setp1_mcreadand D0 + FAPI_INF("Initialize DTS function ...") + + // Enable DTS sampling - bit 5 + // Sample Pulse Count - bits(6:9) set to a small number for sim + // Enable loop 1 DTSs (20:22); loop 2 DTSs (24) + // = ld D1, EX_THERM_MODE_REG_0x1005000F, P1 + // = ori D1, D1, (BIT(5)|BITS(6, 4)|BITS(20,3)|BIT(24)) + // = std D1, EX_THERM_MODE_REG_0x1005000F, P0 + FAPI_TRY(getScom(i_target, EX_THERM_MODE_REG_0x1005000F, data)); + data.insertFromRight<5,5>(0x1F).insertFromRight<20,3>(0xF).setBit<24>(); + FAPI_TRY(putScom(i_target, EX_THERM_MODE_REG_0x1005000F, data)); + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/core/p9_hcd_core_scominit.H b/src/ppe/hwp/core/p9_hcd_core_scominit.H new file mode 100644 index 0000000..9cb570a --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_scominit.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_scominit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_scominit.H +/// @brief Core SCOM Inits +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CORE_SCOMINIT_H__ +#define __P9_HCD_CORE_SCOMINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_scominit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_scominit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + + +/// @brief Core SCOM Inits +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_scominit( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_SCOMINIT_H__ diff --git a/src/ppe/hwp/core/p9_hcd_core_startclocks.C b/src/ppe/hwp/core/p9_hcd_core_startclocks.C new file mode 100644 index 0000000..012f533 --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_startclocks.C @@ -0,0 +1,97 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_startclocks.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_startclocks.C +/// @brief Core Clock Start +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Drop pervasive thold +/// Drop pervasive fence +/// Reset abst clock muxsel, sync muxsel +/// Clear clock controller scan register before start +/// Start arrays + nsl regions +/// Start sl + refresh clock regions +/// Check for clocks started +/// If not, error +/// Check for core xstop (TODO: need for this (?) and then FIR structure in +/// for P9. Note: CME can NOT read Cache FIR) +/// If so, error +/// Clear force align +/// Clear flush mode +/// Check security switch and set trusted boot en bit +/// (TODO: still needed for P9?) +/// Drop the core to cache logical fence +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_core_startclocks.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Core Clock Start +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_core_startclocks( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target) +{ + +#if 0 + + fapi2::buffer<uint64_t> data; + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + diff --git a/src/ppe/hwp/core/p9_hcd_core_startclocks.H b/src/ppe/hwp/core/p9_hcd_core_startclocks.H new file mode 100644 index 0000000..38b6fbd --- /dev/null +++ b/src/ppe/hwp/core/p9_hcd_core_startclocks.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/core/p9_hcd_core_startclocks.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_core_startclocks.H +/// @brief Core Clock Start +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Reshmi Nair <resnair5@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:CME +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CORE_STARTCLOCKS_H__ +#define __P9_HCD_CORE_STARTCLOCKS_H__ + +extern "C" +{ + +/// @typedef p9_hcd_core_startclocks_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_core_startclocks_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>&); + +/// @brief Core Clock Start +/// +/// @param [in] i_target TARGET_TYPE_CORE target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_core_startclocks( + const fapi2::Target<fapi2::TARGET_TYPE_CORE>& i_target); + + +} // extern C + +#endif // __P9_HCD_CORE_STARTCLOCKS_H__ |
