diff options
Diffstat (limited to 'src/ppe/hwp/cache')
31 files changed, 3176 insertions, 0 deletions
diff --git a/src/ppe/hwp/cache/Makefile b/src/ppe/hwp/cache/Makefile new file mode 100644 index 0000000..115a69a --- /dev/null +++ b/src/ppe/hwp/cache/Makefile @@ -0,0 +1,54 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/cache/Makefile $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG + +# This Makefile compiles all of the cache hardware procedure code. See the +# "cachehcdfiles.mk" file in this directory. + +#all generated files from this makefile will end up in obj/cache +export SUB_OBJDIR = /cache + +include img_defs.mk +include cachehcdfiles.mk + + +OBJS := $(addprefix $(OBJDIR)/, $(CACHE_OBJECTS)) + +libcache.a: cache + $(AR) crs $(OBJDIR)/libcache.a $(OBJDIR)/*.o + +.PHONY: clean cache +cache: $(OBJS) + +$(OBJS) $(OBJS:.o=.d): | $(OBJDIR) + +$(OBJDIR): + mkdir -p $(OBJDIR) + +clean: + rm -fr $(OBJDIR) + +ifneq ($(MAKECMDGOALS),clean) +include $(OBJS:.o=.d) +endif diff --git a/src/ppe/hwp/cache/cachehcdfiles.mk b/src/ppe/hwp/cache/cachehcdfiles.mk new file mode 100644 index 0000000..28e36e7 --- /dev/null +++ b/src/ppe/hwp/cache/cachehcdfiles.mk @@ -0,0 +1,65 @@ +# IBM_PROLOG_BEGIN_TAG +# This is an automatically generated prolog. +# +# $Source: src/ppe/hwp/cache/cachehcdfiles.mk $ +# +# OpenPOWER OnChipController Project +# +# Contributors Listed Below - COPYRIGHT 2015 +# [+] International Business Machines Corp. +# +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or +# implied. See the License for the specific language governing +# permissions and limitations under the License. +# +# IBM_PROLOG_END_TAG +# @file cachehcdfiles.mk +# +# @brief mk for including cache hcode object files +# +# @page ChangeLogs Change Logs +# @section cachehcdfiles.mk +# @verbatim +# +# +# Change Log ****************************************************************** +# Flag Defect/Feature User Date Description +# ------ -------------- ---------- ------------ ----------- +# +# @endverbatim +# +########################################################################## +# Object Files +########################################################################## + +CACHE-CPP-SOURCES += p9_hcd_cache_arrayinit.C +CACHE-CPP-SOURCES += p9_hcd_cache_chiplet_init.C +CACHE-CPP-SOURCES += p9_hcd_cache_chiplet_reset.C +CACHE-CPP-SOURCES += p9_hcd_cache_dpll_setup.C +CACHE-CPP-SOURCES += p9_hcd_cache_gptr_time_initf.C +CACHE-CPP-SOURCES += p9_hcd_cache_initf.C +CACHE-CPP-SOURCES += p9_hcd_cache_occ_runtime_scom.C +CACHE-CPP-SOURCES += p9_hcd_cache_poweron.C +CACHE-CPP-SOURCES += p9_hcd_cache_ras_runtime_scom.C +CACHE-CPP-SOURCES += p9_hcd_cache_repair_initf.C +CACHE-CPP-SOURCES += p9_hcd_cache_runinit.C +CACHE-CPP-SOURCES += p9_hcd_cache_scomcust.C +CACHE-CPP-SOURCES += p9_hcd_cache_scominit.C +CACHE-CPP-SOURCES += p9_hcd_cache_startclocks.C + +CACHE-C-SOURCES += +CACHE-S-SOURCES += + +CACHE_OBJECTS += $(CACHE-CPP-SOURCES:.C=.o) +CACHE_OBJECTS += $(CACHE-C-SOURCES:.c=.o) +CACHE_OBJECTS += $(CACHE-S-SOURCES:.S=.o) + diff --git a/src/ppe/hwp/cache/p9_hcd_cache.H b/src/ppe/hwp/cache/p9_hcd_cache.H new file mode 100644 index 0000000..6550690 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache.H @@ -0,0 +1,54 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache.H +/// @brief Cache Chiplet Procedure Includes +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_H__ +#define __P9_HCD_CACHE_H__ + +#include <p9_hcd_cache_arrayinit.H> +#include <p9_hcd_cache_chiplet_init.H> +#include <p9_hcd_cache_chiplet_reset.H> +#include <p9_hcd_cache_dpll_setup.H> +#include <p9_hcd_cache_gptr_time_initf.H> +#include <p9_hcd_cache_initf.H> +#include <p9_hcd_cache_occ_runtime_scom.H> +#include <p9_hcd_cache_poweron.H> +#include <p9_hcd_cache_ras_runtime_scom.H> +#include <p9_hcd_cache_repair_initf.H> +#include <p9_hcd_cache_runinit.H> +#include <p9_hcd_cache_scomcust.H> +#include <p9_hcd_cache_scominit.H> +#include <p9_hcd_cache_startclocks.H> + +#endif // __P9_HCD_CACHE_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_arrayinit.C b/src/ppe/hwp/cache/p9_hcd_cache_arrayinit.C new file mode 100644 index 0000000..465b413 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_arrayinit.C @@ -0,0 +1,170 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_arrayinit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_arrayinit.C +/// @brief EX Initialize arrays +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Use ABIST engine to zero out all arrays +/// Upon completion, scan0 flush all rings +/// except Vital, Repair, GPTR, TIME and DPLL +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_arrayinit.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//----------------------------------------------------------------------------- +// Procedure: Initialize Cache Arrays +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_arrayinit( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + uint32_t scan; + uint32_t loop; + + // Procedure Prereq : P0 is pointing to the targeted EX chiplet + // submodules: + // seeprom_array_init_module + // ex_scan0 + + FAPI_INF("<p9_hcd_cache_arrayinit> : \ + *** Array Init and Scan0 Cleanup for EX Chiplets ***"); + + // SBE Address Base Register Setups + // Setup PRV_BASE_ADDR1; points to selected EX chiplet + // - mr P1, P0 + FAPI_INF("<p9_hcd_cache_arrayinit> : \ + Copy selected EX info from P0 to P1"); + + // Step 1: Array Init for selected EX chiplet + // ARRAY INIT module -> see p9_sbe_tp_array_init.S + // + // At entry: + // + // P1 : The chiplet ID/Multicast Group + // D1 : Clock Regions for Array Init + // + // At exit: + // + // P0, D0, D1, CTR : destroyed + // P1, A0, A1 : maintained + // + FAPI_INF("<p9_hcd_cache_arrayinit> : \ + Calling Array Init Subroutine"); + + // >>> IPL/Winkle + // \bug Need to exclude DPLL ring for IPL + // li D1, SCAN_ALLREGIONEXVITAL + // = li D1, SCAN_CLK_ALLEXDPLL + scan = SCAN_CLK_ALLEXDPLL; + + // Execute the array init + // = bsr seeprom_array_init_module + seeprom_array_init_module(scan); + + // Restore P0 with selected EX chiplet info + // - mr P0, P1 + FAPI_INF("<p9_hcd_cache_arrayinit> : \ + Copy selected EX info back from P1 to P0"); + + // Step 2: Scan0 for selected EX chiplet except PRV, GPTR, TIME and DPLL + FAPI_INF("<p9_hcd_cache_arrayinit> : \ + Calling Scan0 Subroutine"); + + // taken from p9_sbe_ex_chiplet_init + + // >>> IPL/Winkle scan flush - all except vital + + // Hook to bypass in Sim + // - hooki 0, 0xFF02 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + FAPI_DBG("EX Init: Scan0 Module executed: \ + Scan all except vital, DPL, GPTR, and TIME scan chains"); + + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the + // the longest ring is defined by P9_SCAN0_FUNC_REPEAT. When the design + // ALWAYS has all stumps less than 8191, the repeat (eg .rept) can be + // removed. + // Implementation note: this is not done in a loop (or included in the + // ex_scan0_module itself) as the D0 and D1 registers are used in + // ex_scan0_module and there is no convenient place to temporaily store + // the 2-64b values values. Argueably, PIBMEM could be used for this + // but was not utilized. + + // \bug remove DPLL ring + // ex_scan0 SCAN_ALL_BUT_VITALDPLLGPTRTIME, SCAN_CLK_ALL + // = .rept P9_SCAN0_FUNC_REPEAT + // = ex_scan0 SCAN_ALL_BUT_VITALDPLLGPTRTIME, SCAN_CLK_ALLEXDPLL + // = .endr + for(loop=0;loop<P9_SCAN0_FUNC_REPEAT;loop++) + { + ex_scan0(SCAN_ALL_BUT_VITALDPLLGPTRTIME,SCAN_CLK_ALLEXDPLL); + } + // - 1: + + FAPI_INF("<p9_hcd_cache_arrayinit> : \ + *** End of Procedure ***"); + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_arrayinit.H b/src/ppe/hwp/cache/p9_hcd_cache_arrayinit.H new file mode 100644 index 0000000..530c4db --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_arrayinit.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_arrayinit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_arrayinit.H +/// @brief EX Initialize arrays +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_ARRAYINIT_H__ +#define __P9_HCD_CACHE_ARRAYINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_arrayinit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_arrayinit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + +/// @brief EX Initialize arrays +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_arrayinit( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_ARRAYINIT_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.C b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.C new file mode 100644 index 0000000..a73ad42 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.C @@ -0,0 +1,140 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_init.C +/// @brief EX Flush/Initialize +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Scan0 flush all configured chiplet rings except Vital, GPTR, TIME and DPLL +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_chiplet_init.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- +//#define SIM_PLL +//#define SIM_SPEEDUP +////#define SCAN0_DISABLE +//#define STEP_CHIPLET_INIT_0 0x0 // Resetting DPLL +//#define STEP_CHIPLET_INIT_1 0x1 // Core+ECO glmux switch (IPL/Winkle) +//#define STEP_CHIPLET_INIT_2 0x2 // Core glmux switch (Sleep) +//#define STEP_CHIPLET_INIT_3 0x3 // Before Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_4 0x4 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_5 0x5 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_INIT_6 0x6 // Before Core GPTR flush for Sleep +//#define STEP_CHIPLET_INIT_7 0x7 // After Core GPTR flush for Sleep +//#define STEP_CHIPLET_INIT_8 0x8 // Before Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_9 0x9 // After Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_A 0xA // Before Core Func flush for Sleep +//#define STEP_CHIPLET_INIT_B 0xB // After Core Func flush for Sleep +//#define PORE_REFCLK_CYCLES 1 // \todo need real value for hdw +//#define DPLL_LOCK_DELAY 8192*PORE_REFCLK_CYCLES + +//----------------------------------------------------------------------------- +// Procedure: EX Flush/Initialize +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_chiplet_init( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + uint32_t loop; + + // Procedure Prereq: + // p9_sbe_ex_chiplet_reset, p9_sbe_ex_dpll_initf, p9_sbe_ex_pll_initf + + FAPI_INF("<p9_hcd_cache_chiplet_init>: Entering procedure"); + + // Look for PSCOM error on any chip, fail if we find one + // scan0 flush all configured chiplet rings except EX DPLL + // call ex_scan0_module( ) + + // >>> IPL/Winkle scan flush - all except vital + + // Hook to bypass in Sim + // - hooki 0, 0xFF02 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + FAPI_DBG("EX Init: Scan0 Module executed: \ + Scan all except vital, DPL, GPTR, and TIME scan chains"); + // - updatestep STEP_CHIPLET_INIT_6, D0, P1 + + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the + // the longest ring is defined by P9_SCAN0_FUNC_REPEAT. When the design + // ALWAYS has all stumps less than 8191, the repeat (eg .rept) can be + // removed. + // Implementation note: this is not done in a loop (or included in the + // ex_scan0_module itself) as the D0 and D1 registers are used in + // ex_scan0_module and there is no convenient place to temporaily store + // the 2-64b values values. Argueably, PIBMEM could be used for this + // but was not utilized. + // = .rept P9_SCAN0_FUNC_REPEAT + // = ex_scan0 SCAN_ALL_BUT_VITALDPLLGPTRTIME, SCAN_CLK_ALLEXDPLL + // = .endr + for(loop=0;loop<P9_SCAN0_FUNC_REPEAT;loop++) + { + ex_scan0(SCAN_ALL_BUT_VITALDPLLGPTRTIME,SCAN_CLK_ALLEXDPLL); + } + // - updatestep STEP_CHIPLET_INIT_7, D0, P1 + // - 1: + + FAPI_INF("<p9_hcd_cache_chiplet_init>: Exiting procedure"); + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.H b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.H new file mode 100644 index 0000000..8dfacbc --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_chiplet_init.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_init.H +/// @brief EX Flush/Initialize +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_CHIPLET_INIT_H__ +#define __P9_HCD_CACHE_CHIPLET_INIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_chiplet_init_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_init_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + + +/// @brief EX Flush/Initialize +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_chiplet_init( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_CHIPLET_INIT_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.C b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.C new file mode 100644 index 0000000..a4fa4ce --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.C @@ -0,0 +1,313 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_reset.C +/// @brief Cache Chiplet Reset +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Reset quad chiplet logic +/// Scan0 flush entire cache chiplet +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_chiplet_reset.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +// GP3 Bits +// 1 - PCB_EP_RESET +// 2 - GLMMUX Reset +// 3 - PLL_TEST Enable +// 4 - PLLRST - PLL Reset +// 5 - PLL Bypass +// 11 - D_MODE for Vital +// 13 - MPW2 for Vital +// 14 - PMW1 for Vital +// 18 - FENCE_EN for chiplet +// 22 - Resonant Clock disable +// 23:24 - Glitchless Mux Sel +// 25: - ?? (set because System Pervasive flow does this) +// Background: system pervasive as the following setting in their tests: +// 7C1623C000000000 +// Bits set: +// 1, 2, 3, 4, 5, 11, 13, 14, 18, 22, 23, 24, 25 +//#define GP3_INIT_VECTOR (BITS(1,5)|BIT(11)|BIT(13)|BIT(14)|BIT(18)|BIT(22)|BIT(23)|BIT(24)|BIT(25)) + +// hang counter inits +//#define HANG_P1_INIT 0x0400000000000000 +//#define PCB_SL_ERROR_REG_RESET 0xFFFFFFFFFFFFFFFF +//#define STEP_CHIPLET_RESET_1 0x1 // After start of vital clocks +//#define STEP_CHIPLET_RESET_2 0x2 // After fence drop +//#define STEP_CHIPLET_RESET_3 0x3 // Before GPTR flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_4 0x4 // After GPTR flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_5 0x5 // Before Func flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_6 0x6 // After Func flush for IPL/Winkle +//#define STEP_CHIPLET_RESET_7 0x7 // Before GPTR flush for Sleep +//#define STEP_CHIPLET_RESET_8 0x8 // After GPTR flush for Sleep + +//------------------------------------------------------------------------------ +// Procedure: Cache Chiplet Reset +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_chiplet_reset( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + +#if 0 + uint32_t loop; + + ///////////////////////////////////////////////////////////////// + // repeat some init steps of chiplet_init + ///////////////////////////////////////////////////////////////// + + // If there is a unused, powered-off EX chiplet which needs to be + // configured in the following steps to setup the PCB endpoint. + + // Skip the PCB endpoint config steps for sleep so that fences don't + // get dropped (eg by dropping chiplet_enable (GP3(0)). + + FAPI_INF("<p9_hcd_cache_chiplet_reset>: \ + Repeat dedicated pervasive init steps for EX "); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Reset GP3 for EX chiplet, step needed for hotplug"); + // = sti GENERIC_GP3_0x000F0012,P0,GP3_INIT_VECTOR + FAPI_TRY(putScom(i_target, GENERIC_GP3_0x000F0012, + fapi2:buffer<uint64_t>(23452345))); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Drop aync reset to Glitchless Mux"); + // = sti GENERIC_GP3_AND_0x000F0013,P0,~BIT(2) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2:buffer<uint64_t>().flush<1>().clearBit<2>())); + + // 19:21 PM_PI_DECODE needs to be 010 for functional operation(set bit 20) + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Put DPLL in functional mode"); + // = sti GENERIC_GP3_OR_0x000F0014,P0, BIT(20) + FAPI_TRY(putScom(i_target, GENERIC_GP3_OR_0x000F0014, + fapi2::buffer<uint64_t>().setBit<20>())); + + // - updatestep STEP_CHIPLET_RESET_1, D0, P1 + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Release endpoint reset for PCB"); + // = sti GENERIC_GP3_AND_0x000F0013,P0,~BIT(1) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2:buffer<uint64_t>().flush<1>().clearBit<1>())); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Partial good setting"); + // = sti GENERIC_GP3_OR_0x000F0014,P0,BIT(0) + FAPI_TRY(putScom(i_target, GENERIC_GP3_OR_0x000F0014, + fapi2::buffer<uint64_t>().setBit<0>())); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + PCB slave error reg reset"); + // = sti MASTER_PCB_ERR_0x000F001F,P0,PCB_SL_ERROR_REG_RESET + FAPI_TRY(putScom(i_target, MASTER_PCB_ERR_0x000F001F, + fapi2:buffer<uint64_t>(643564))); + + FAPI_DBG("Use timer mode for DPLL lock when enabled"); + // = sti EX_PMGP0_OR_0x100F0102, P0, BIT(7) + FAPI_TRY(putScom(i_target, EX_PMGP0_OR_0x100F0102, + fapi2::buffer<uint64_t>().setBit<7>())); + + // Set the DPLL Timer value for waiting on DPLL HOLDs in 35:36 + // 00 = 1024 cycles <---- + // 01 = 512 cycles + // 10 = 256 cycles + // 11 = 128 cycles + FAPI_DBG("Set the timer value for waiting on DPLL THOLDs"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(35)|BIT(36)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer<uint64_t>().flush<1>().insertFromRight<35,2>(0))); + + // Only perform the disablement of PCBS-PM for the IPL work-around when + // doing IPL (eg skip if winkle; this whole section is skipped for sleep) + // >>> IPL + // FAPI_DBG("Disable the PCBS-PM as part of winkle enablement"); + // = sti EX_PMGP0_OR_0x100F0102, P0, BIT(0) + FAPI_TRY(putScom(i_target, EX_PMGP0_OR_0x100F0102, + fapi2:buffer<uint64_t>().setBit<0>())); + + // The following is performed for both IPL/Winkle and Sleep + + // Note: These are executed for sleep as well as these fences will have + // already been dropped + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Remove pervasive ECO fence;"); + // ECO Fence in 22 + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(22)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer<uint64_t>().flush<1>().clearBit<22>())); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Remove winkle mode before scan0 on EX chiplets is executed"); + // PM Exit States: WINKLE_EXIT_DROP_ELEC_FENCE + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Remove logical pervasive/pcbs-pm fence"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(39)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer<uint64_t>().flush<1>().clearBit<39>())); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Remove PB Winkle Electrical Fence GP3(27)"); + // = sti EX_GP3_AND_0x100F0013,P0,~(BIT(27)) + FAPI_TRY(putScom(i_target, EX_GP3_AND_0x100F0013, + fapi2:buffer<uint64_t>().flush<1>().clearBit<27>())); + + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Configuring chiplet hang counters") ; + // = sti EX_HANG_P1_0x100F0021,P0,HANG_P1_INIT + data = 34654; // HANG_P1_INIT + FAPI_TRY(putScom(i_target, EX_HANG_P1_0x100F0021, + fapi2:buffer<uint64_t>(34654))); + // - updatestep STEP_CHIPLET_RESET_2, D0, P1 + + ////////////////////////////////////////////////////////////// + // perform scan0 module for pervasive chiplet (GPTR_TIME_REPR) + ////////////////////////////////////////////////////////////// + + // >>> IPL/Winkle scan flush - core and EX + + // Hook to bypass in sim while providing a trace + // - hooki 0, 0xFF01 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + // \todo WORKAROUND UNTIL LOGIC CHANGES + // Drop the core2cache and cache2core fences to allow for L2 scanning + FAPI_DBG("<p9_hcd_cache_chiplet_reset>: \ + Remove pervasive ECO fence;"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(20) | BIT(21)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer<uint64_t>().flush<1>().insertFromRight<20,2>(0))); + + FAPI_DBG("EX Reset: Scan0 Module executed: \ + Scan the GPTR/TIME/REP rings"); + // - updatestep STEP_CHIPLET_RESET_3, D0, P1 + + // = .rept P9_SCAN0_GPTR_REPEAT + // = ex_scan0 SCAN_GPTR_TIME_REP, SCAN_CLK_ALL + // = .endr + for(loop=0;loop<P9_SCAN0_GPTR_REPEAT;loop++) + { + ex_scan0(SCAN_GPTR_TIME_REP, SCAN_CLK_ALL); + } + + // - updatestep STEP_CHIPLET_RESET_4, D0, P1 + + // - 1: + // Hook to bypass in sim while providing a trace + // - hooki 0, 0xFF02 + // - ifslwcntlbitset P9_SLW_SKIP_FLUSH,1f + + FAPI_DBG("EX Reset: Scan0 Module executed: \ + Scan the all but GPTR/TIME/REP rings"); + // - updatestep STEP_CHIPLET_RESET_5, D0, P1 + + // Each scan0 will rotate the ring 8191 latches (2**13 - 1) and the + // the longest ring is defined by P9_SCAN0_FUNC_REPEAT. When the design + // ALWAYS has all stumps less than 8191, the repeat (eg .rept) can be + // removed. + // Implementation note: this is not done in a loop (or included in the + // ex_scan0_module itself) as the D0 and D1 registers are used in + // ex_scan0_module and there is no convenient place to temporarily store + // the 2-64b values values. Argueably, PIBMEM could be used for this + // but was not utilized. + // = .rept P9_SCAN0_FUNC_REPEAT + // = ex_scan0 SCAN_ALL_BUT_GPTRTIMEREP, SCAN_CLK_ALL + // = .endr + for(loop=0;loop<P9_SCAN0_FUNC_REPEAT;loop++) + { + ex_scan0(SCAN_ALL_BUT_GPTRTIMEREP, SCAN_CLK_ALL); + } + + // - updatestep STEP_CHIPLET_RESET_6, D0, P1 + + // Ensure CC interrupts are disabled before starting clock domains and dpll + // But only do it for Murano-DD1.x! + // - lpcs P1, STBY_CHIPLET_0x00000000 + // - ldandi D0, PCBMS_DEVICE_ID_0x000F000F, P1, BITS(0, 32) + // - andi D0, D0, CFAM_CHIP_ID_CHIP_MAJOR_MASK + // - cmpibrane D0, 1f, CFAM_CHIP_ID_MURANO_1 + + // - mr A0, P0 + // - mr D1, ETR + // - ls P0, CHIPLET0 + // - ls CTR, MAX_CORES + // - bra end_core_loop + + // - begin_core_loop: + // Inspect presence of current ex chiplet + // - andi D0, D1, BIT(32) + // - braz D0, continue_core + // Disable CC interrupts. + // - ld D0, EX_SYNC_CONFIG_0x10030000, P0 + // - ori D0, D0, BIT(6) + // - std D0, EX_SYNC_CONFIG_0x10030000, P0 + + // - continue_core: + // - adds P0, P0, 1 //Increment ex chiplet + // - rols D1, D1, 1 //Shift ex chiplet mask left + + // - end_core_loop: + // - loop begin_core_loop + // - mr P0, A0 + // - 1: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.H b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.H new file mode 100644 index 0000000..8dc6167 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_chiplet_reset.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_chiplet_reset.H +/// @brief Cache Chiplet Reset +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_CHIPLET_RESET_H__ +#define __P9_HCD_CACHE_CHIPLET_RESET_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_chiplet_reset_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_chiplet_reset_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +/// @brief Cache Chiplet Reset +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_chiplet_reset( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_CHIPLET_RESET_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.C b/src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.C new file mode 100644 index 0000000..0175c98 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.C @@ -0,0 +1,282 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_dpll_setup.C +/// @brief Quad DPLL Setup +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// DPLL tune bits are not dependent on frequency +/// Put DPLL into bypass +/// Set DPLL syncmux sel +/// Set clock controller scan ratio to 1:1 as this is done at refclk speeds +/// Load the EX DPLL scan ring +/// Set clock controller scan ratio to 8:1 for future scans +/// Frequency is controlled by the Quad PPM +/// Actual frequency value for boot is stored into the Quad PPM by +/// p9_hcd_setup_evid.C in istep 2 +/// In real cache STOP exit, the frequency value is persistent +/// Enable the DPLL in the correct mode +/// non-dynamic +/// Slew rate established per DPLL team +/// Take the cache glitchless mux out of reset +/// (TODO: is there still a reset on P9?) +/// Remove DPLL bypass +/// Drop DPLL Tholds +/// Check for DPLL lock +/// Timeout: 200us +/// Switch cache glitchless mux to use the DPLL +/// + +//----------------------------------------------------------------------------- +// Includes +//----------------------------------------------------------------------------- +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_dpll_setup.H" + +//----------------------------------------------------------------------------- +// Constant Definitions +//----------------------------------------------------------------------------- + +//#define DPLL_LOCK_BIT, 50 +//#define DPLL_LOCK_MAX_POLL_LOOPS, 0x1600 +//#define DPLL_LOCK_DELAY_CYCLES, 0x10 +//#define STEP_SBE_DPLL_SETUP_LOCK, 1 +//#define STEP_SBE_DPLL_GMUX_SET, 2 +//#define STEP_SBE_DPLL_SETUP_COMPLETE, 3 + +// For a 2000GHz nest (500MHz Pervasive), 2ns clocks exists +// For a DPLL lock time of >150us from power on, 150000/2 = 75000 +// d75000 => 0x124F8 ----> round up to 0x15000 + +// For a 2400GHz nest (600MHz Pervasive), 1.667ns clocks exists +// For a DPLL lock time of >150us from power on, 150000/1.667 = 89982 +// d90000 => 0x15f90 ----> round up to 0x16000 + +//#define DPLL_LOCK_DELAY 0x10 +//#define DPLL_LOCK_LOOP_NUMBER 0x1600 + +//#define ex_dpll_lock_delay_mult 0x1600 +//#define ex_glsmux_post_delay_mult 0x1 + +//----------------------------------------------------------------------------- +// Procedure: Quad DPLL Setup +//----------------------------------------------------------------------------- + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_dpll_setup( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + + FAPI_INF("EX Chiplet -> Start DPLL setup" ) + + // The setup of P0 happens external to this procedure + // P0 is set to point to either a single EX core, or to multiple EX + // cores using multicast + FAPI_DBG("EX Chiplet dpll_setup P0 -> 0x%02llx" , io_pore.p0.read()) + + // Skip DPLL and Glitchless mux setup for Sleep + // Glitchless mux change for the core (Sleep) done in + // p9_sbe_ex_chiplet_reset. + + // - ifsleep D0, glm_end + // >>> IPL/WINKLE + + // - dpll_start: + + // - setp1_mcreadand D0 + + FAPI_INF("Set up CPM PARM register for DPLL") + // = ld D0, EX_DPLL_CPM_PARM_REG_0x100F0152, P1 + FAPI_TRY(getScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152, data)); + + // ----- Make sure that ff_bypass is set to "1" ----- + // This is necessary to ensure that the DPLL is in Mode 1. If not, + // the lock times will go from ~30us to 3-5ms + // Set bit 11 of DPLL Mode register 0x150F0152 + + FAPI_DBG("Put DPLL into Mode 1 by asserting ff_bypass.") + FAPI_DBG(">>> Work around <<<<: Also disabling ping-pong synchronizer" ) + // = ori D0, D0, (BIT(11)|BIT(32)) + data.setBit<11>().setBit<32>(); + + FAPI_DBG("Clear bits 15,16,18-23 and set bit 17 of DPLL reg 0x10F0152") + // = andi D0, D0, 0xFFFE00FFFFFFFFFF + // = ori D0, D0, BIT(17) + data.insertFromRight<15,9>(0x40); + + FAPI_DBG("Set slew rate to a modest value") + // = ori D0, D0, 0x8000000000000000 + // = std D0, EX_DPLL_CPM_PARM_REG_0x100F0152, P0 + data.setBit<0>(); + FAPI_TRY(putScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152, data)); + + // ----- Clear dpllclk_muxsel (syncclk_muxsel) to "0" ----- + FAPI_INF("Reset syncclk_muxsel or dpllclk_muxsel") + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BIT(1) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2:buffer<uint64_t>().flush<1>().clearBit<1>())); + + // = sti EX_PMGP0_AND_0x100F0101, P0, ~(BIT(11)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer<uint64_t>().flush<1>().clearBit<11>())); + + // ----- Take DPLL out of bypass ----- + // Clear bit 5 of EX GP3 Register + FAPI_INF("EX Chiplet -> Take DPLL out of bypass" ) + // = sti EX_GP3_AND_0x100F0013, P0, ~(BIT(5)) + FAPI_TRY(putScom(i_target, EX_GP3_AND_0x100F0013, + fapi2:buffer<uint64_t>().flush<1>().clearBit<5>())); + + // ----- Drop DPLL tholds ----- + // Clear bit 3 of EX PMGP0 Register + FAPI_INF("EX Chiplet -> Drop internal DPLL THOLD" ) + // = sti EX_PMGP0_AND_0x100F0101, P0, ~(BIT(3)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer<uint64_t>().flush<1>().clearBit<3>())); + + // ----- Delay to wait for DPLL to lock ----- + // TODO: Determine whether or not we should POLL instead of put delay here. + // Wait for >150us + + FAPI_INF("Wait for DPLL to lock" ) + // - waits DPLL_LOCK_LOOP_NUMBER*DPLL_LOCK_DELAY + + // Check for lock + // - ldandi D0, EX_PMGP0_0x100F0100, P1, BIT(DPLL_LOCK_BIT) + // - braz D0, dpll_nolock + + // ----- Recycle DPLL in and out of bypass ----- + // Clear bit 5 of EX GP3 Register + FAPI_INF("EX Chiplet -> Recycle DPLL in and out of bypass" ) + // = sti EX_GP3_OR_0x100F0014, P0, BIT(5) + FAPI_TRY(putScom(i_target, EX_GP3_OR_0x100F0014, + fapi2:buffer<uint64_t>().setBit<5>())); + + // = sti EX_GP3_AND_0x100F0013, P0, ~(BIT(5)) + FAPI_TRY(putScom(i_target, EX_GP3_AND_0x100F0013, + fapi2:buffer<uint64_t>().flush<1>().clearBit<5>())); + + FAPI_INF("EX Chiplet -> EX DPLL is locked" ) + // - updatestep STEP_SBE_DPLL_SETUP_LOCK, D0, P1 + + // - glm_start: + + // ----- Set Glitch-Less MUXes for IPL/Winkle case ---- + // For Sleep, the core glitchless mux is change earlier as the DPLL + // was already up and locked. + // + // Set various gl muxes to pass the output of the DPLLs to the clock grid. + + // Read-modify-write (vs sti AND and sti OR) is done so that glitchless + // mux change field change is atomic (eg 1 store) + // - setp1_mcreadand D1 + + // = ld D1,EX_PMGP0_0x100F0100,P1 + FAPI_TRY(getScom(i_target, EX_PMGP0_0x100F0100, data)); + + // IPL/Winkle - Switch glitchless mux primary source to 001 = DPLL for bits + // 27:29 + + // Note: GLM async reset occured in p9_sbe_ex_chiplet_reset. + + // Set tp_clkglm_sel_dc to "001" (EX PM GP0 bits 27-29) + FAPI_INF("EX Chiplet -> Set glitchless mux select for primary chiplet clock source to 001 ") + // Set tp_clkglm_eco_sel_dc to "0" (EX PM GP0 bit 30) + // Set the core glitchless mux to use the primary input (b00). + // EX PM GP0 bits 32-33) + FAPI_INF("EX Chiplet -> Set glitchless mux select for core and eco domain to 0 ") + // = andi D1, D1, ~(BIT(27)|BIT(28)|BIT(30)|BIT(32)|BIT(33)) + // = ori D1, D1, (BIT(29)) + data.insertFromRight<27,4>(0x2).inerstFromRight<32,2>(0x0); + + // Store the final result to the hardware + // = std D1,EX_PMGP0_0x100F0100,P0 + FAPI_TRY(putScom(i_target, EX_PMGP0_0x100F0100, data)); + + // - glm_end: + + // - updatestep STEP_SBE_DPLL_GMUX_SET, D0, P1 + + // ----- Drop ff_bypass to enable slewing ----- + // ----- (Change from Mode 1 to mode 2) ----- + // Clear bit 11 of DPLL Mode register 0x150F0152 + // CMO20131125-Further, drop the pp synchronizer bit32. + // CMO20131219-Keep the pp sync bit32 asserted to avoid x-leakage(HW276931). + FAPI_INF("EX Chiplet -> Clear ff_bypass to switch into slew-controlled mode") + // - setp1_mcreadand D1 + // = ld D1, EX_DPLL_CPM_PARM_REG_0x100F0152, P1 + // = andi D1, D1, ~(BIT(11)) + // = std D1, EX_DPLL_CPM_PARM_REG_0x100F0152, P0 + FAPI_TRY(getScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152, data)); + data.clearBit<11>(); + FAPI_TRY(putScom(i_target, EX_DPLL_CPM_PARM_REG_0x100F0152, data)); + + // ----- Drop other tholds ----- + // Clear bit 3 of EX PM GP0 Register + // FAPI_INF("EX Chiplet -> Drop DPLL thold" ) + // sti EX_PMGP0_AND_0x100F0101,P0, ~(BIT(3)) + + // - updatestep STEP_SBE_DPLL_SETUP_COMPLETE, D0, P1 + FAPI_INF("EX Chiplet -> DPLL setup completed" ) + + // DEBUG only + // - setp1_mcreadand D1 + // = ld D0,EX_GP0_0x10000000,P1 + FAPI_TRY(getScom(i_target, EX_GP0_0x10000000, data)); + + // - dpll_nolock: + FAPI_ERR("EX_DPLL -> Failed to lock"); + // - reqhalt RC_SBE_DPLL_SETUP_NOLOCK + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.H b/src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.H new file mode 100644 index 0000000..df13cf0 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_dpll_setup.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_dpll_setup.H +/// @brief Quad DPLL Setup +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_DPLL_SETUP_H__ +#define __P9_HCD_CACHE_DPLL_SETUP_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_dpll_setup_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_dpll_setup_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +/// @brief Quad DPLL Setup +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_DPLL_REPAIR_RING - EQ target, uint32 +/// repair dpll ring content<br> +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_dpll_setup( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_DPLL_SETUP_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.C b/src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.C new file mode 100644 index 0000000..498ae79 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.C @@ -0,0 +1,110 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_gptr_time_initf.C +/// @brief Load GPTR and Time for EX non-core +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// to produce #G VPD contents +/// Check for the presence of core override GPTR ring from image +/// (this is new fvor P9) +/// if found, apply; if not, apply core GPTR from image +/// Check for the presence of core override TIME ring from image; +/// if found, apply; if not, apply core base TIME from image +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_gptr_time_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Load GPTR and Time for EX non-core +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_gptr_time_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target) +{ + +#if 0 + + // Set EX scan ratio to 1:1 as EX is still at refclock + FAPI_INF("<p9_sbe_ex_gptr_time_initf> : Set EX scan ratio to 1:1 ..."); + // = sti EX_OPCG_CNTL0_0x10030002, P0, 0x0 + FAPI_TRY(fapi2::putScom(i_target, EX_OPCG_CNTL0_0x10030002, 0x0)); + + // scan ring content shared among all chiplets + FAPI_DBG("Scanning EX GPTR rings...") + // - load_ring ex_gptr_perv skipoverride=1 + // - load_ring ex_gptr_dpll skipoverride=1 + // - load_ring ex_gptr_l3 skipoverride=1 + // - load_ring ex_gptr_l3refr skipoverride=1 + + // scan chiplet specific ring content + FAPI_DBG("Scanning EX TIME rings...") + // - load_ring_vec_ex ex_time_eco + + + // Set EX scan ratio back to 8:1 + FAPI_INF("<p9_sbe_ex_gptr_time_initf> : Set EX scan ratio to 8:1 ..."); + // Inputs: A1 and P0 and D0, destroys D0 & D1 + // - .pibmem_port (PORE_SPACE_PIBMEM & 0xf) + // - lpcs P1, PIBMEM0_0x00080000 + // - ld D0, ex_scan_ratio_override, P1 + // - bsr set_scan_ratio_d0 + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.H b/src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.H new file mode 100644 index 0000000..17d001f --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_gptr_time_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_gptr_time_initf.H +/// @brief Load GPTR and Time for EX non-core +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_GPTR_TIME_INIT_H__ +#define __P9_HCD_CACHE_GPTR_TIME_INIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_gptr_time_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_gptr_time_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&); + +/// @brief Load GPTR and Time for EX non-core +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// +/// @attr +/// @attritem ATTR_CACHE_GPTR_TIME_RING - EX target, uint32 +/// pointer to RS4 content.<br> +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_gptr_time_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_GPTR_TIME_INIT_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_initf.C b/src/ppe/hwp/cache/p9_hcd_cache_initf.C new file mode 100644 index 0000000..630940b --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_initf.C @@ -0,0 +1,99 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_initf.C +/// @brief EX (non-core) scan init +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Initfiles in procedure defined on VBU ENGD wiki (TODO add link) +/// Check for the presence of cache FUNC override rings from image; +/// if found, apply; if not, apply cache base FUNC rings from image +/// Note: FASTINIT ring (eg CMSK ring) is setup at this point to limit the +/// stumps that participate in FUNC ring scanning (this is new for P9). +/// (TODO to make sure the image build support is in place) +/// Note: all caches that are in the Cache Multicast group will be +/// initialized to the same values via multicast scans +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: EX (non-core) scan init +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + + // - load_ring ex_lbst_eco conditional_override=1 + // - load_ring ex_abfa_eco conditional_override=1 + // - load_ring ex_cmsk_eco conditional_override=1 + // - load_ring ex_func_perv conditional_override=1 + // - load_ring ex_func_l3 conditional_override=1 + // - load_ring ex_func_l3refr conditional_override=1 + + //Sim Speedup for L3 refresh cycles + // - load_ring ex_regf_l3 conditional_override=1 + // - load_ring ex_regf_l3refr conditional_override=1 + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_initf.H b/src/ppe/hwp/cache/p9_hcd_cache_initf.H new file mode 100644 index 0000000..9f7ffdc --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_initf.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_initf.H +/// @brief EX (non-core) scan init +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_INITF_H__ +#define __P9_HCD_CACHE_INITF_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + +/// @brief EX (non-core) scan init +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem ATTR_CACHE_L2_FUNC_RING - EX target, uint32 +/// @attritem ATTR_CACHE_L3_FUNC_RING - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_INITF_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.C b/src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.C new file mode 100644 index 0000000..8e1c82e --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.C @@ -0,0 +1,93 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_occ_runtime_scom.C +/// @brief EX OCC runtime scoms +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates from OCC code that are put somewhere TBD +/// (TODO . revisit with OCC FW team) +/// OCC FW sets up value in the TBD SCOM section +/// This was not leverage in P8 with the demise of CPMs +/// Placeholder at this point +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_occ_runtime_scom.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ +#define host_runtime_scom 0 + +//------------------------------------------------------------------------------ +// Procedure: EX OCC runtime SCOMS +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_occ_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, occ_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + FAPI_INF("Launching OCC Runtime SCOM routine") + // - bsrd D0 + // - 1: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.H b/src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.H new file mode 100644 index 0000000..e82b6b2 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_occ_runtime_scom.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_occ_runtime_scom.H +/// @brief EX OCC runtime scoms +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ +#define __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_occ_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_occ_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + + +/// @brief EX OCC runtime scoms +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem ATTR_CACHE_OCC_SCOM_LOC - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_occ_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_OCC_RUNTIME_SCOM_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_poweron.C b/src/ppe/hwp/cache/p9_hcd_cache_poweron.C new file mode 100644 index 0000000..0aa81a1 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_poweron.C @@ -0,0 +1,84 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_poweron.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_poweron.C +/// @brief Cache Chiplet Power-on +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Command the cache PFET controller to power-on +/// Check for valid power on completion +/// Polled Timeout: 100us +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_poweron.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Cache Chiplet Power-on +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_poweron( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target, + const uint32_t i_operation) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_poweron.H b/src/ppe/hwp/cache/p9_hcd_cache_poweron.H new file mode 100644 index 0000000..89bcffc --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_poweron.H @@ -0,0 +1,66 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_poweron.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_poweron.H +/// @brief Cache Chiplet Power-on +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_POWERON_H__ +#define __P9_HCD_CACHE_POWERON_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_poweron_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_poweron_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>&, + const uint32_t); + + +/// @brief Cache Chiplet Power-on +/// +/// @param [in] i_target TARGET_TYPE_EQ target +/// @param [in] i_operation ENUM(ON,OFF) +/// +/// @attr +/// @attritem ATTR_PFET_* +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_poweron( + const fapi2::Target<fapi2::TARGET_TYPE_EQ>& i_target, + const uint32_t i_operation); + + +} // extern C + +#endif // __P9_HCD_CACHE_POWERON_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.C b/src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.C new file mode 100644 index 0000000..88a0518 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.C @@ -0,0 +1,171 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_ras_runtime_scom.C +/// @brief EX FSP/Host runtime scoms +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Run-time updates by FSP/Host(including HostServices and Hypervisors) +/// that are put on the cache image by STOP API calls +/// Dynamically built pointer where a NULL is checked before execution +/// If NULL (the SBE case), return +/// Else call the function at the pointer; pointer is filled in by +/// STOP image build +/// Powerbus (MCD) and L3 BAR settings +/// Runtime FIR mask updates from PRD +/// L2/L3 Repairs +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_ras_runtime_scom.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ +#define host_runtime_scom 0 + +//------------------------------------------------------------------------------ +// Procedure: EX FSP/HOST runtime scoms +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_ras_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + + // Run the SCOM sequence if the SCOM procedure is defined + // - la A0, sp_runtime_scom + // - ld D0, 0, A0 + // - braz D0, 1f + //FAPI_INF("Launching SP Runtime SCOM routine") + // - bsrd D0 + // - 1: + // + + // Run the SCOM sequence if the SCOM procedure is defined. + // - la A0, host_runtime_scom + // - ld D1, 0, A0 + // - braz D1, 1f + + // Prep P1 + // - setp1_mcreadand D0 + +#if 0 + // Disable the AISS to allow the override + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = andi D0, D0, ~(BIT(1)) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // Drop PSCOM fence to allow SCOM and set pm_wake-up to PC to accepts + // RAMs (SCOMs actually) in the IPL "Nap" state + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = ori D0, D0, (BIT(15)) + // = andi D0, D0, ~(BIT(21)) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 +#endif + + // Branch to sub_slw_runtime_scom() + FAPI_INF("Launching Host Runtime SCOM routine") + // - bsrd D1 + + // Prep P1 + // - setp1_mcreadand D0 + +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = andi D0, D0, ~(BIT(15)) + // = ori D0, D0, BIT(21) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = ori D0, D0, (BIT(1)) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + + // - bra 2f + // - 1: + + // To accomodate IPL flow, where sub_slw_runtime_scom() is skipped + // - setp1_mcreadand D0 + +#if 0 + // Clear regular wake-up and restore PSCOM fence in OHA + // These were established in p9_sbe_ex_scominit.S + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = andi D0, D0, ~BIT(1) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = andi D0, D0, ~(BIT(15)) + // = ori D0, D0, BIT(21) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + // Enable the AISS to allow further operation + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = ori D0, D0, (BIT(1)) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 +#endif + // - 2: + + // If using cv_multicast, we need to set the magic istep number here + // - la A0, p9_sbe_select_ex_control + // - ldandi D0, 0, A0, P9_CONTROL_INIT_ALL_EX + // - braz D0, 3f + FAPI_DBG("Setting istep num to magic number because cv_multicast is set") + // - lpcs P1, MBOX_SBEVITAL_0x0005001C + // - sti MBOX_SBEVITAL_0x0005001C, P1, (P9_SBE_EX_RAS_RUNTIME_SCOM_MAGIC_ISTEP_NUM << (4+32)) + // - 3: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.H b/src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.H new file mode 100644 index 0000000..ec9a389 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_ras_runtime_scom.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_ras_runtime_scom.H +/// @brief EX FSP/Host runtime scoms +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ +#define __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_ras_runtime_scom_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_ras_runtime_scom_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + +/// @brief EX FSP/Host runtime scoms +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem ATTR_CACHE_RAS_SCOM_LOC - EX target, uint32 +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_ras_runtime_scom( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_RAS_RUNTIME_SCOM_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_repair_initf.C b/src/ppe/hwp/cache/p9_hcd_cache_repair_initf.C new file mode 100644 index 0000000..e986a81 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_repair_initf.C @@ -0,0 +1,87 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_repair_initf.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_repair_initf.C +/// @brief Load Repair ring for EX non-core +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Load cache ring images from MVPD +/// These rings must contain ALL chip customization data. +/// This includes the following: Repair Power headers, and DTS +/// Historically this was stored in MVPD keywords are #R, #G. Still stored in /// MVPD, but SBE image is customized with rings for booting cores +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_repair_initf.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Load Repair ring for cache +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_repair_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + + // scan chiplet specific ring content + FAPI_DBG("Scanning EX REPAIR rings...") + // - load_ring_vec_ex ex_repr_eco + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_repair_initf.H b/src/ppe/hwp/cache/p9_hcd_cache_repair_initf.H new file mode 100644 index 0000000..ab8484f --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_repair_initf.H @@ -0,0 +1,64 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_repair_initf.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_repair_initf.H +/// @brief Load Repair ring for EX non-core +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_REPAIR_INITF_H__ +#define __P9_HCD_CACHE_REPAIR_INITF_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_repair_initf_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_repair_initf_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + + +/// @brief Load Repair ring for EX non-core +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem ATTR_CACHE_REPAIR_RING - EX target, uint32 +/// pointer to RS4 content, VPD #R Keyword content(RS4)<br> +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_repair_initf( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_REPAIR_INITF_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_runinit.C b/src/ppe/hwp/cache/p9_hcd_cache_runinit.C new file mode 100644 index 0000000..eb6f5fe --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_runinit.C @@ -0,0 +1,73 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_runinit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_runinit.C +/// @brief execute all cache init procedures +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_runinit.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_runinit( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target) +{ + return fapi2::FAPI2_RC_SUCCESS; + +#if 0 + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; +#endif + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_runinit.H b/src/ppe/hwp/cache/p9_hcd_cache_runinit.H new file mode 100644 index 0000000..2b22d35 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_runinit.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_runinit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_runinit.H +/// @brief execute all cache init procedures +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_RUNINIT_H__ +#define __P9_HCD_CACHE_RUNINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_runinit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_runinit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>&); + + +/// @brief execute all cache init procedures +/// +/// @param [in] i_target TARGET_TYPE_PROC_CHIP target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_runinit( + const fapi2::Target<fapi2::TARGET_TYPE_PROC_CHIP>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_RUNINIT_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_scomcust.C b/src/ppe/hwp/cache/p9_hcd_cache_scomcust.C new file mode 100644 index 0000000..789f954 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_scomcust.C @@ -0,0 +1,93 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_scomcust.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scomcust.C +/// @brief Core Chiplet PCB Arbitration +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// If CME, request PCB Mux. +/// Poll for PCB Mux grant +/// Else (SBE) +/// Nop (as the CME is not running in bringing up the first Core) +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_scomcust.H" + +//------------------------------------------------------------------------------ +// Constant Definitions: Core Chiplet PCB Arbitration +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_scomcust( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) +{ + +#if 0 + + fapi2::buffer<uint64_t> data; + + //Dynamically built (and installed) routine that is inserted by the .XIP + //Customization. process. (New for P9) + //(TODO: this part of the process is a placeholder at this point) + //Dynamically built pointer where a NULL is checked before execution + //If NULL (a potential early value); return + //Else call the function at the pointer; + //pointer is filled in by XIP Customization + //Customization items: + //Epsilon settings scan flush to super safe + //Customize Epsilon settings for system config + //LCO setup (chiplet specific) + //FW setups up based victim caches + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_scomcust.H b/src/ppe/hwp/cache/p9_hcd_cache_scomcust.H new file mode 100644 index 0000000..9837513 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_scomcust.H @@ -0,0 +1,62 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_scomcust.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scomcust.H +/// @brief Core Chiplet PCB Arbitration +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_SCOMCUST_H__ +#define __P9_HCD_CACHE_SCOMCUST_H__ +extern "C" +{ + +/// @typedef p9_hcd_cache_scomcust_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_scomcust_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + + +/// @brief Core Chiplet PCB Arbitration +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_scomcust( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_SCOMCUST_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_scominit.C b/src/ppe/hwp/cache/p9_hcd_cache_scominit.C new file mode 100644 index 0000000..869de65 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_scominit.C @@ -0,0 +1,130 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_scominit.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scominit.C +/// @brief Cache Customization SCOMs +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Apply any SCOM initialization to the cache +/// Stop L3 configuration mode +/// Configure Trace Stop on Xstop +/// DTS Initialization sequense +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_scominit.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Procedure: Cache Customization SCOMs +//------------------------------------------------------------------------------ + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_scominit( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + + /////// + // NCU + /////// + + /////// + // L3 + /////// + + FAPI_DBG("Configuring L3 disable"); + // - l3_setup L3_SETUP_ACTION_DISABLE, L3_SETUP_UNIT_L3 + + /////// + // OHA + /////// + + FAPI_DBG("Enable OHA to accept idle operations \ + by removing idle state override"); + // - setp1_mcreadand D1 + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + FAPI_TRY(getScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + + //FAPI_DBG("Read OHA_MODE value: 0x%16llx", io_pore.d0.read()); + // = andi D0, D0, ~BIT(6) + data.clearBit<6>(); + + //FAPI_DBG("Updated OHA_MODE value: 0x%16llx", io_pore.d0.read()); + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + FAPI_TRY(putScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + + // set trace stop on checkstop + // Get the ECID to apply trace setup to only Murano DD2+ / Venice + // - lpcs P1, STBY_CHIPLET_0x00000000 + // - ldandi D0, PCBMS_DEVICE_ID_0x000F000F, P1, (CFAM_CHIP_ID_CHIP_MASK | CFAM_CHIP_ID_MAJOR_EC_MASK) + // - cmpibraeq D0, 1f, (CFAM_CHIP_ID_MURANO | CFAM_CHIP_ID_MAJOR_EC_1 ) + + FAPI_DBG("Configuring EX chiplet trace arrays \ + to stop on checkstop/recoverable errors") + // = sti GENERIC_DBG_MODE_REG_0x000107C0, P0, BIT(7) | BIT(8) + FAPI_TRY(putScom(i_target, GENERIC_DBG_MODE_REG_0x000107C0, + fapi2:buffer<uint64_t>().insertFromRight<7,2>(0x3))); + + // = sti GENERIC_DBG_TRACE_REG2_0x000107CB, P0, BIT(17) + FAPI_TRY(putScom(i_target, GENERIC_DBG_TRACE_REG2_0x000107CB, + fapi2:buffer<uint64_t>().setBit<17>())); + // - 1: + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_scominit.H b/src/ppe/hwp/cache/p9_hcd_cache_scominit.H new file mode 100644 index 0000000..0fd37c6 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_scominit.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_scominit.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_scominit.H +/// @brief Cache Customization SCOMs +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + +#ifndef __P9_HCD_CACHE_SCOMINIT_H__ +#define __P9_HCD_CACHE_SCOMINIT_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_scominit_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_scominit_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + + +/// @brief Cache Customization SCOMs +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_scominit( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_SCOMINIT_H__ diff --git a/src/ppe/hwp/cache/p9_hcd_cache_startclocks.C b/src/ppe/hwp/cache/p9_hcd_cache_startclocks.C new file mode 100644 index 0000000..3731f2e --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_startclocks.C @@ -0,0 +1,275 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_startclocks.C $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_startclocks.C +/// @brief Quad Clock Start +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// +/// Procedure Summary: +/// Set (to be sure they are set under all conditions) core logical fences +/// (new for P9) +/// Drop pervasive thold +/// Setup L3 EDRAM/LCO +/// Drop pervasive fence +/// Reset abst clock muxsel, sync muxsel +/// Set fabric node/chip ID from the nest version +/// Clear clock controller scan register before start +/// Start arrays + nsl regions +/// Start sl + refresh clock regions +/// Check for clocks started +/// If not, error +/// Clear force align +/// Clear flush mode +/// Drop the chiplet fence to allow PowerBus traffic +/// + +//------------------------------------------------------------------------------ +// Includes +//------------------------------------------------------------------------------ +#include <fapi2.H> +//#include <common_scom_addresses.H> +//will be replaced with real scom address header file +#include "p9_hcd_cache_startclocks.H" + +//------------------------------------------------------------------------------ +// Constant Definitions +//------------------------------------------------------------------------------ + +#define STEP_EX_START_CLOCKS_NSL 0x1 +#define STEP_EX_START_CLOCKS_SL 0x2 +#define STEP_EX_START_CLOCKS_RUNNING 0x3 +#define STEP_EX_START_CLOCKS_SUCCESS 0x4 + + +//------------------------------------------------------------------------------ +// Procedure: Quad Clock Start +//------------------------------------------------------------------------------ + + +extern "C" +{ + +fapi2::ReturnCode +p9_hcd_cache_startclocks( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target) +{ + +#if 0 + fapi2::buffer<uint64_t> data; + + FAPI_INF("<p9_hcd_cache_startclocks>: \ + P8 Start EX-Clocks started"); + + // Drop the Pervasive THOLD + // PM Exit States: WINKLE_EXIT_DROP_PERV_THOLD + // = sti EX_PMGP0_AND_0x100F0101,P0, ~(BIT(4)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer<uint64_t>().flush<1>().clearBit<4>())); + + FAPI_DBG("Enabling L3 EDRAM/LCO setup"); + // - l3_setup L3_SETUP_ACTION_ENABLE, L3_SETUP_UNIT_L3_EDRAM + + // Drop perv fence GP0.63 multicast scomreg write + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BIT(63) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2:buffer<uint64_t>().flush<1>().clearBit<63>())); + + // Reset abstclk_muxsel, synclk_muxsel (io_clk_sel) + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BITS(0,2) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2:buffer<uint64_t>().flush<1>().insertFromRight<0,2>(0x0))); + + // Set ABIST_MODE_DC for core chiplets (core recovery) + // = sti GENERIC_GP0_OR_0x00000005, P0, BIT(11)|BIT(13) + FAPI_TRY(putScom(i_target, GENERIC_GP0_OR_0x00000005, + fapi2:buffer<uint64_t>().setBit<11>().setBit<13>())); + + // set fabric node/chip ID values (read from nest chiplet) + // read from nest chiplet + // - lpcs P1, NEST_CHIPLET_0x02000000 + // - ldandi D0, NEST_GP0_0x02000000, P1, BITS(40, 6) + // = std D0, GENERIC_GP0_OR_0x00000005, P0 + //FAPI_TRY(putScom(i_target, GENERIC_GP0_OR_0x00000005, data)); + + // Write ClockControl, Scan Region Register, + // set all bits to zero prior clock start + // = sti GENERIC_CLK_SCANSEL_0x00030007, P0, 0x0000000000000000 + FAPI_TRY(putScom(i_target, GENERIC_CLK_SCANSEL_0x00030007, 0x0)); + + // Write ClockControl, Clock Region Register, Clock Start command + // (arrays + nsl only, not refresh clock region) EX Chiplet + // = sti GENERIC_CLK_REGION_0x00030006, P0, 0x4FF0060000000000 + FAPI_TRY(putScom(i_target, GENERIC_CLK_REGION_0x00030006, + fapi2:buffer<uint64_t>(0x4FF0060000000000))); + // - updatestep STEP_EX_START_CLOCKS_NSL, D0, P1 + + // Write ClockControl, Clock Region Register, Clock Start command + // (sl + refresh clock region) EX Chiplet + // = sti GENERIC_CLK_REGION_0x00030006, P0, 0x4FF00E0000000000 + FAPI_TRY(putScom(i_target, GENERIC_CLK_REGION_0x00030006, + fapi2:buffer<uint64_t>(0x4FF00E0000000000))); + // - updatestep STEP_EX_START_CLOCKS_SL, D0, P1 + + // Read Clock Status Register (EX chiplet) + // check for bits 27:29 eq. zero, no tholds on + // 27 ROX CLOCK_STATUS_DPLL_FUNC_SL status of dpll_func_sl_thold + // 28 ROX CLOCK_STATUS_DPLL_FUNC_NSL status of dpll_func_nsl_thold + // output not used + // 29 ROX CLOCK_STATUS_DPLL_ARY_NSL status of dpll_ary_nsl_thold + // output not used + + // Needed to resolve SLW reading using a multicast group + // Get P1 setup for the chiplets to be targeted. + // - setp1_mcreadand D0 + + // = ld D0, GENERIC_CLK_STATUS_0x00030008, P1 + FAPI_TRY(getScom(i_target, GENERIC_CLK_STATUS_0x00030008, data)); + // - xori D0, D0, 0x00000003FFFFFFFF + // - branz D0, error_clock_start + + FAPI_DBG("<p9_hcd_cache_startclocks>: \ + EX clock running now"); + // - updatestep STEP_EX_START_CLOCKS_RUNNING, D0, P1 + + // Read the Global Checkstop FIR of dedicated EX chiplet + // - setp1_mcreador D0 + // = ld D0, GENERIC_XSTOP_0x00040000, P1 + FAPI_TRY(getScom(i_target, GENERIC_XSTOP_0x00040000, data)); + // - branz D0, error_checkstop_fir + + FAPI_DBG("<p9_hcd_cache_startclocks>: \ + All checkstop FIRs on initialized EX are zero"); + + // Clear force_align in all Chiplet GP0 + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BIT(3) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2:buffer<uint64_t>().flush<1>().clearBit<3>())); + + // Clear flushmode_inhibit in Chiplet GP0 + // Can't do this on Murano & Venice DD1.x due to a logic bug in L3 HW250462 + // - lpcs P1, PCBMS_DEVICE_ID_0x000F000F + // - ldandi D0, PCBMS_DEVICE_ID_0x000F000F, P1, CFAM_CHIP_ID_MAJOR_EC_MASK + // - cmpibraeq D0, 1f, CFAM_CHIP_ID_MAJOR_EC_1 + // = sti GENERIC_GP0_AND_0x00000004, P0, ~BIT(2) + FAPI_TRY(putScom(i_target, GENERIC_GP0_AND_0x00000004, + fapi2:buffer<uint64_t>().flush<1>().clearBit<2>())); + // - 1: + + // Clear core2cache and cache2core fences. Necessary for Sleep, + // redundant (already clear) but not harmful for IPL/Winkle + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(20)|BIT(21)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer<uint64_t>().flush<1>().insertFromRight<20,2>(0x0))); + + // Disable PM and DPLL override + FAPI_INF("<p9_hcd_cache_startclocks>: \ + Disable PM and DPLL override"); + // = sti EX_PMGP0_AND_0x100F0101,P0,~(BIT(0)|BIT(3)) + FAPI_TRY(putScom(i_target, EX_PMGP0_AND_0x100F0101, + fapi2:buffer<uint64_t>().flush<1>().insertFromRight<0,4>(0x6))); + + // PM Exit States: WINKLE_EXIT_WAIT_ON_OHA + // Drop fence GP3.18 to unfence the chiplet + // CMO-20130516: First clear the pbus purge request bit(14) from AISS + // - setp1_mcreador D0 + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = andi D0, D0, ~BIT(1) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + FAPI_TRY(getScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + data.clearBit<1>(); + FAPI_TRY(putScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + // = ld D0, EX_OHA_AISS_IO_REG_0x10020014, P1 + // = andi D0, D0, ~BIT(14) + // = std D0, EX_OHA_AISS_IO_REG_0x10020014, P0 + FAPI_TRY(getScom(i_target, EX_OHA_AISS_IO_REG_0x10020014, data)); + data.clearBit<14>(); + FAPI_TRY(putScom(i_target, EX_OHA_AISS_IO_REG_0x10020014, data)); + // = ld D0, EX_OHA_MODE_REG_RWx1002000D, P1 + // = ori D0, D0, BIT(1) + // = std D0, EX_OHA_MODE_REG_RWx1002000D, P0 + FAPI_TRY(getScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + data.setBit<1>(); + FAPI_TRY(putScom(i_target, EX_OHA_MODE_REG_RWx1002000D, data)); + // Now drop pb fence bit(18) + // = sti GENERIC_GP3_AND_0x000F0013,P0, ~BIT(18) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2:buffer<uint64_t>().flush<1>().clearBit<18>())); + + // Drop fence GP3.26 to allow PCB operations to the chiplet + // = sti GENERIC_GP3_AND_0x000F0013,P0, ~BIT(26) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2:buffer<uint64_t>().flush<1>().clearBit<26>())); + // - updatestep STEP_EX_START_CLOCKS_SUCCESS, D0, P1 + FAPI_INF("<p9_hcd_cache_startclocks>: \ + Exiting procedure successfully"); + + // - ifidle D0, 1f + //Not idle Check secure mode + // - ifbitclrscom D1, D1, OTPC_M_SECURITY_SWITCH_0x00010005, P1, 1, 1f + //Trusted boot is set, set core trusted boot. + // = sti EX_TRUSTED_BOOT_EN_0x10013C03, P0, BIT(0) + FAPI_TRY(putScom(i_target, GENERIC_GP3_AND_0x000F0013, + fapi2:buffer<uint64_t>().flush<1>().clearBit<0>())); + // - 1: + +//------------------------------------------------------------------------------ +// ERROR -- Clocks failed to start +//------------------------------------------------------------------------------ +error_clock_start: + FAPI_ERR("<p9_hcd_cache_startclocks>: \ + Clock Start Error on EX detected"); + // - reqhalt RC_SBE_EX_STARTCLOCKS_CLOCKS_NOT_STARTED + +//------------------------------------------------------------------------------ +// ERROR -- Checkstop detected +//------------------------------------------------------------------------------ +error_checkstop_fir: + FAPI_ERR("<p9_hcd_cache_startclocks>: \ + Checkstop FIR on initialized EX is not zero, \ + VITAL register was updated"); + // - reqhalt RC_SBE_EX_STARTCLOCKS_CHIP_XSTOPPED + + return fapi2::FAPI2_RC_SUCCESS; + + FAPI_CLEANUP(); + return fapi2::FAPI2_RC_PLAT_ERR_SEE_DATA; + +#endif + + return fapi2::FAPI2_RC_SUCCESS; + +} // Procedure + + +} // extern C + + + + diff --git a/src/ppe/hwp/cache/p9_hcd_cache_startclocks.H b/src/ppe/hwp/cache/p9_hcd_cache_startclocks.H new file mode 100644 index 0000000..a6aa1d6 --- /dev/null +++ b/src/ppe/hwp/cache/p9_hcd_cache_startclocks.H @@ -0,0 +1,63 @@ +/* IBM_PROLOG_BEGIN_TAG */ +/* This is an automatically generated prolog. */ +/* */ +/* $Source: src/ppe/hwp/cache/p9_hcd_cache_startclocks.H $ */ +/* */ +/* OpenPOWER OnChipController Project */ +/* */ +/* Contributors Listed Below - COPYRIGHT 2015 */ +/* [+] International Business Machines Corp. */ +/* */ +/* */ +/* Licensed under the Apache License, Version 2.0 (the "License"); */ +/* you may not use this file except in compliance with the License. */ +/* You may obtain a copy of the License at */ +/* */ +/* http://www.apache.org/licenses/LICENSE-2.0 */ +/* */ +/* Unless required by applicable law or agreed to in writing, software */ +/* distributed under the License is distributed on an "AS IS" BASIS, */ +/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or */ +/* implied. See the License for the specific language governing */ +/* permissions and limitations under the License. */ +/* */ +/* IBM_PROLOG_END_TAG */ +/// +/// @file p9_hcd_cache_startclocks.H +/// @brief Quad Clock Start +/// +/// *HWP HWP Owner : David Du <daviddu@us.ibm.com> +/// *HWP FW Owner : Sangeetha T S <sangeet2@in.ibm.com> +/// *HWP Team : PM +/// *HWP Consumed by : SBE:SGPE +/// *HWP Level : 1 +/// + + +#ifndef __P9_HCD_CACHE_STARTCLOCKS_H__ +#define __P9_HCD_CACHE_STARTCLOCKS_H__ + +extern "C" +{ + +/// @typedef p9_hcd_cache_startclocks_FP_t +/// function pointer typedef definition for HWP call support +typedef fapi2::ReturnCode (*p9_hcd_cache_startclocks_FP_t) ( + const fapi2::Target<fapi2::TARGET_TYPE_EX>&); + +/// @brief Quad Clock Start +/// +/// @param [in] i_target TARGET_TYPE_EX target +/// +/// @attr +/// @attritem NONE +/// +/// @retval FAPI_RC_SUCCESS +fapi2::ReturnCode +p9_hcd_cache_startclocks( + const fapi2::Target<fapi2::TARGET_TYPE_EX>& i_target); + + +} // extern C + +#endif // __P9_HCD_CACHE_STARTCLOCKS_H__ |
