diff options
Diffstat (limited to 'src/occ/gpe')
| -rwxr-xr-x | src/occ/gpe/apss_altitude.pS | 163 | ||||
| -rwxr-xr-x | src/occ/gpe/apss_composite.pS | 169 | ||||
| -rwxr-xr-x | src/occ/gpe/apss_constants.h | 68 | ||||
| -rwxr-xr-x | src/occ/gpe/apss_init.pS | 230 | ||||
| -rwxr-xr-x | src/occ/gpe/apss_meas_read_complete.pS | 143 | ||||
| -rwxr-xr-x | src/occ/gpe/apss_meas_read_cont.pS | 161 | ||||
| -rwxr-xr-x | src/occ/gpe/apss_meas_read_start.pS | 144 | ||||
| -rwxr-xr-x | src/occ/gpe/gpe_export.h | 67 | ||||
| -rwxr-xr-x | src/occ/gpe/gpe_macros.h | 178 | ||||
| -rwxr-xr-x | src/occ/gpe/pore_nop.pS | 41 | ||||
| -rwxr-xr-x | src/occ/gpe/pore_test.pS | 74 | ||||
| -rwxr-xr-x | src/occ/gpe/pore_test_error.pS | 246 | ||||
| -rwxr-xr-x | src/occ/gpe/pore_test_pss.pS | 444 | ||||
| -rwxr-xr-x | src/occ/gpe/pss_constants.h | 71 | ||||
| -rwxr-xr-x | src/occ/gpe/pss_macros.h | 192 |
15 files changed, 2391 insertions, 0 deletions
diff --git a/src/occ/gpe/apss_altitude.pS b/src/occ/gpe/apss_altitude.pS new file mode 100755 index 0000000..6deac1d --- /dev/null +++ b/src/occ/gpe/apss_altitude.pS @@ -0,0 +1,163 @@ +# ***************************************************************************** +# @file apss_altitude.S +# @brief Read the altitude from the APSS +# + +# ***************************************************************************** +# +# @page ChangeLogs Change Logs +# @section apss_altitude.S APSS_ALTITUDE.S +# @verbatim +# +# Flag Def/Fea Userid Date Description +# ------- ---------- -------- ---------- ---------------------------------- +# @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments +# +# @endverbatim +# +# ***************************************************************************** + + + ////////////////////////////////////////////////////////////////////// + // Includes + ////////////////////////////////////////////////////////////////////// + .nolist +#include "pgp.h" +#include "pgas.h" + .list + + ////////////////////////////////////////////////////////////////////// + // Define Address Space + ////////////////////////////////////////////////////////////////////// + .oci + + ////////////////////////////////////////////////////////////////////// + // Define Symbols + ////////////////////////////////////////////////////////////////////// + +#include <pss_constants.h> + +#define GPE_PROG_ID 0x0002 + + ////////////////////////////////////////////////////////////////////// + // Define Structures + ////////////////////////////////////////////////////////////////////// + + // Declare the offsets of the struct that will be passed to the + // GPE program via the ETR register + // + // struct G_gpe_apss_read_altitude_args = + // { + .struct 0 +ERROR_RC: + .struct ERROR_RC + 8 +ERROR_FFDC: + .struct ERROR_FFDC + 8 +ALTITUDE: + // }; + + + ////////////////////////////////////////////////////////////////////// + // Begin Program + ////////////////////////////////////////////////////////////////////// + + .text + +#include <gpe_macros.h> +#include <pss_macros.h> + + + //-------------------------------------------------------------------- + // PORE-GPE Routine Specification: + // + // Name: GPE_apss_read_altitude + // + // Description: Initialize APSS GPIO pins for Input/Output, Interrupt + // Drive H/L + // + // Inputs: G_gpe_apss_read_altitude_args + // struct { + // PoreGpeErrorStruct error; + // uint16_t altitude; // This is where the altitude will be stored (output) + // uint8_t reserved[6]; // Requried since GPE only does 8 byte writes. + // } G_gpe_apss_read_altitude_args + // struct { + // uint64_t rc; // This should be read as 63:32=addr, 31:0=rc + // uint64_t ffdc; // Whatever GPE program puts in for FFDC data + // } PoreGpeErrorStruct; + // + // Outputs: Altitude (and FFDC on failure) + // + // Flow: 7/20/11 FN=GPE_apss_set_composite_mode + // + // References: APSS FUnctional Specification v0.7.18 + // GPE_apss_access_scoms.odt (summary of regisers/data) + // + // End PORE-GPE Routine Specification + //-------------------------------------------------------------------- + .global GPE_apss_read_altitude +GPE_apss_read_altitude: + + // Copy passed Structure Pointer into A1 + mr A1, ETR + + // Wait for SPI operations to be complete (10usec timeout) + _wait_for_spi_ops_complete 10, error_timeout + + // Setup control regs + // frame_size=16, out_count=16, in_delay1=never, in_count2=16 + _putscom SPIPSS_P2S_CTRL_REG0, 0x410FC00004000000 + // bridge_enable, clock_divider=7, 2 frames + _putscom SPIPSS_P2S_CTRL_REG1, 0x801C400000000000 + // inter_frame_delay=25 (2.5usec) + _putscom SPIPSS_P2S_CTRL_REG2, 0x000C800000000000 + + // APSS command to get the altitude (APSS cmd 0x9000) + li D0, 0x9000000000000000 + _putscom_d0 SPIPSS_P2S_WDATA_REG + + // Start SPI transaction + _putscom SPIPSS_P2S_COMMAND_REG, 0x8000000000000000 + + // wait 10usec for command to complete + waits (10 * MICROSECONDS) + + // Wait for SPI operations to be complete (10usec timeout) + _wait_for_spi_ops_complete 10, error_altitude_timeout + + // Read altitude and store in structure + _getscom SPIPSS_P2S_RDATA_REG + // The scom data for that cmd is in 2nd two bytes of the register (shift left 2 bytes) + rols D0, D0, 16 + std D0, ALTITUDE, A1 + + halt // End of GPE_apss_initialize_gpio + + +error_statusreg: + // An error/reserved bit was set when reading p2s status register... + // D0: P2S_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0002 + halt + + +error_timeout: + // p2s_ongoing bit was never cleared after several retries... + // D0: P2S_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0001 + halt + + +error_altitude_timeout: + // After sending the read altitude command, the p2s_ongoing bit was + // never cleared after several retries... + // D0: P2S_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0003 + halt + + + ////////////////////////////////////////////////////////////////////// + // End of Program + ////////////////////////////////////////////////////////////////////// + + diff --git a/src/occ/gpe/apss_composite.pS b/src/occ/gpe/apss_composite.pS new file mode 100755 index 0000000..7325eb0 --- /dev/null +++ b/src/occ/gpe/apss_composite.pS @@ -0,0 +1,169 @@ +# ***************************************************************************** +# @file apss_composite.S +# @brief Set APSS into composite mode so OCC can read ADC, Temp & GPIO data +# + +# ***************************************************************************** +# +# @page ChangeLogs Change Logs +# @section apss_composite.S APSS_COMPOSITE.S +# @verbatim +# +# Flag Def/Fea Userid Date Description +# ------- ---------- -------- ---------- ---------------------------------- +# @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments +# @th032 thallet 04/16/2013 Tuleta HW Bringup +# @at023 910877 alvinwan 01/09/2014 Excessive fan increase requests error for mfg +# @gm026 916029 milesg 02/17/2014 revert back to auto2 mode without reading GPIO's +# @gm038 926761 milesg 05/16/2014 slowed SPI bus down from 12MHz to 10MHz on venice (8MHz on murano) +# @gs039 936836 gjsilva 08/28/2014 slowed SPI bus down from 10MHz to 8MHz on venice (~6MHz on murano) +# +# @endverbatim +# +# ***************************************************************************** + + + ////////////////////////////////////////////////////////////////////// + // Includes + ////////////////////////////////////////////////////////////////////// + .nolist +#include "pgp.h" +#include "pgas.h" + .list + + ////////////////////////////////////////////////////////////////////// + // Define Address Space + ////////////////////////////////////////////////////////////////////// + .oci + + ////////////////////////////////////////////////////////////////////// + // Define Symbols + ////////////////////////////////////////////////////////////////////// + +#include <pss_constants.h> + +#define GPE_PROG_ID 0x0003 + + ////////////////////////////////////////////////////////////////////// + // Define Structures + ////////////////////////////////////////////////////////////////////// + + // Declare the offsets of the struct that will be passed to the + // GPE program via the ETR register + // + // struct G_gpe_apss_read_altitude_args = + // { + .struct 0 +ERROR_RC: + .struct ERROR_RC + 8 +ERROR_FFDC: + .struct ERROR_FFDC + 8 +CONFIG: + // }; + + + ////////////////////////////////////////////////////////////////////// + // Begin Program + ////////////////////////////////////////////////////////////////////// + + .text + +#include <gpe_macros.h> +#include <pss_macros.h> + + + //-------------------------------------------------------------------- + // PORE-GPE Routine Specification: + // + // Name: GPE_apss_set_composite_mode + // + // Description: Set APSS into composite mode so OCC can read ADC, Temp & GPIO data + // + // Inputs: G_gpe_apss_set_composite_mode_args + // struct { + // PoreGpeErrorStruct error; + // apssCompositeConfigStruct_t config; // G_apss_composite_config (input to APSS) + // } G_gpe_apss_set_composite_mode_args; + // struct { + // uint64_t rc; // This should be read as 63:32=addr, 31:0=rc + // uint64_t ffdc; // Whatever GPE program puts in for FFDC data + // } PoreGpeErrorStruct; + // struct { + // uint8_t numAdcChannelsToRead; + // uint8_t numGpioPortsToRead; + // } apssCompositeConfigStruct + // + // Outputs: None (except FFDC on failure) + // + // Flow: 7/20/11 FN=GPE_apss_set_composite_mode + // + // References: APSS FUnctional Specification v0.7.18 + // GPE_apss_access_scoms.odt (summary of regisers/data) + // + // End PORE-GPE Routine Specification + //-------------------------------------------------------------------- + .global GPE_apss_set_composite_mode +GPE_apss_set_composite_mode: + + // Copy passed Structure Pointer into A1 + mr A1, ETR + + // Wait for SPI operations to be complete (10usec timeout) + _wait_for_spi_ops_complete 10, error_timeout + + // Initialize SPIPSS -- Don't do this. Value is platform dependent and set by HWP outside of OCC (gm026) + //_putscom SPIPSS_100NS_REG, 0x0000003200000000 + + // Setup control regs + // frame size=16, out_count1=16, in_delay1=never, in_count2=16 + _putscom SPIPSS_P2S_CTRL_REG0, 0x4100000000000000 + // bridge_enable, clock_divider=7, 1 frame + //_putscom SPIPSS_P2S_CTRL_REG1, 0x8060000000000000 + //_putscom SPIPSS_P2S_CTRL_REG1, 0x8074000000000000 //gm038 + _putscom SPIPSS_P2S_CTRL_REG1, 0x8090000000000000 //@gs039 + // inter_frame_delay=25 (2.5usec) + _putscom SPIPSS_P2S_CTRL_REG2, 0x0019000000000000 + + // APSS command to set composite data streaming mode (APSS cmd 0x8xxx, reserved bits are 1) + li D0, 0x8C00000000000000 + // last ADC channel address (0 = 1 ADC, etc) + ldandi D1, CONFIG, A1, 0x1F00000000000000 + srdi D1, D1, 56 + subs D1, D1, 1 + sldi D1, D1, 54 + or D0, D0, D1 + // number of GPIO ports to return (0 = 0 GPIOs, etc...) + ldandi D1, CONFIG, A1, 0x0003000000000000 // @at023c + or D0, D0, D1 + ////_putscom_d0 SPIPSS_P2S_WDATA_REG + _putscom SPIPSS_P2S_WDATA_REG, 0x3FC0000000000000 // gm026 -- use auto2 mode (more reliable than composite mode) + + // Start SPI transaction + _putscom SPIPSS_P2S_COMMAND_REG, 0x8000000000000000 + + // Wait 20usec for apss becoming ready to send out the frame of composite mode + // 10usec is not enough and 20use is ok from test result. + waits (20 * MICROSECONDS) // @at023c + + halt // End of GPE_apss_initialize_gpio + + +error_statusreg: + // An error/reserved bit was set when reading p2s status register... + // D0: P2S_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0002 + halt + + +error_timeout: + // p2s_ongoing bit was never cleared after several retries... + // D0: P2S_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0001 + halt + + + ////////////////////////////////////////////////////////////////////// + // End of Program + ////////////////////////////////////////////////////////////////////// + + diff --git a/src/occ/gpe/apss_constants.h b/src/occ/gpe/apss_constants.h new file mode 100755 index 0000000..ddda1b4 --- /dev/null +++ b/src/occ/gpe/apss_constants.h @@ -0,0 +1,68 @@ +/****************************************************************************** +// @file apss_constants.h +// @brief Constants used by APSS communications GPE programs +*/ +/****************************************************************************** + * + * @page ChangeLogs Change Logs + * @section apss_constants.h APSS_CONSTANTS.H + * @verbatim + * + * Flag Def/Fea Userid Date Description + * ------- ---------- -------- ---------- ---------------------------------- + * + * @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments + * + * @endverbatim + * + *///*************************************************************************/ + +//************************************************************************* +// Includes +//************************************************************************* + +//************************************************************************* +// Externs +//************************************************************************* + +//************************************************************************* +// Macros +//************************************************************************* + +//************************************************************************* +// Defines/Enums +//************************************************************************* +#define SPIPSS_REGISTER_BASE 0x00020000 +#define SPIPSS_ADC_CTRL_REG0 (SPIPSS_REGISTER_BASE + 0x00) +#define SPIPSS_ADC_CTRL_REG1 (SPIPSS_REGISTER_BASE + 0x01) +#define SPIPSS_ADC_CTRL_REG2 (SPIPSS_REGISTER_BASE + 0x02) +#define SPIPSS_ADC_STATUS_REG (SPIPSS_REGISTER_BASE + 0x03) +#define SPIPSS_ADC_COMMAND_REG (SPIPSS_REGISTER_BASE + 0x04) +#define SPIPSS_ADC_WDATA_REG (SPIPSS_REGISTER_BASE + 0x10) +#define SPIPSS_ADC_RDATA_REG0 (SPIPSS_REGISTER_BASE + 0x20) +#define SPIPSS_ADC_RDATA_REG1 (SPIPSS_REGISTER_BASE + 0x21) +#define SPIPSS_ADC_RDATA_REG2 (SPIPSS_REGISTER_BASE + 0x22) +#define SPIPSS_ADC_RDATA_REG3 (SPIPSS_REGISTER_BASE + 0x23) +#define SPIPSS_P2S_CTRL_REG0 (SPIPSS_REGISTER_BASE + 0x40) +#define SPIPSS_P2S_CTRL_REG1 (SPIPSS_REGISTER_BASE + 0x41) +#define SPIPSS_P2S_CTRL_REG2 (SPIPSS_REGISTER_BASE + 0x42) +#define SPIPSS_P2S_STATUS_REG (SPIPSS_REGISTER_BASE + 0x43) +#define SPIPSS_P2S_COMMAND_REG (SPIPSS_REGISTER_BASE + 0x44) +#define SPIPSS_P2S_WDATA_REG (SPIPSS_REGISTER_BASE + 0x50) +#define SPIPSS_P2S_RDATA_REG (SPIPSS_REGISTER_BASE + 0x60) + +//************************************************************************* +// Strustures +//************************************************************************* + +//************************************************************************* +// Globals +//************************************************************************* + +//************************************************************************* +// Function Prototypes +//************************************************************************* + +//************************************************************************* +// Functions +//************************************************************************* diff --git a/src/occ/gpe/apss_init.pS b/src/occ/gpe/apss_init.pS new file mode 100755 index 0000000..fd66147 --- /dev/null +++ b/src/occ/gpe/apss_init.pS @@ -0,0 +1,230 @@ +# ***************************************************************************** +# @file apss_init.S +# @brief Initialize the APSS GPIOs +# + +# ***************************************************************************** +# +# @page ChangeLogs Change Logs +# @section apss_init.S APSS_INIT.S +# @verbatim +# +# Flag Def/Fea Userid Date Description +# ------- ---------- -------- ---------- ---------------------------------- +# @gm038 926761 milesg 05/16/2014 slowed SPI bus down from 12MHz to 10MHz on venice (8MHz on murano) +# @gs039 936836 gjsilva 08/28/2014 slowed SPI bus down from 10MHz to 8MHz on venice (~6MHz on murano) +# +# @endverbatim +# +# ***************************************************************************** + + + ////////////////////////////////////////////////////////////////////// + // Includes + ////////////////////////////////////////////////////////////////////// + .nolist +#include "pgp.h" +#include "pgas.h" + .list + + ////////////////////////////////////////////////////////////////////// + // Define Address Space + ////////////////////////////////////////////////////////////////////// + .oci + + ////////////////////////////////////////////////////////////////////// + // Define Symbols + ////////////////////////////////////////////////////////////////////// + +#include <pss_constants.h> + +#define GPE_PROG_ID 0x0001 + + ////////////////////////////////////////////////////////////////////// + // Define Structures + ////////////////////////////////////////////////////////////////////// + + // Declare the offsets of the struct that will be passed to the + // GPE program via the ETR register + // + // struct G_gpe_apss_initialize_gpio_args = + // { + .struct 0 +ERROR_RC: + .struct ERROR_RC + 8 +ERROR_FFDC: + .struct ERROR_FFDC + 8 +CONFIG: + // }; + + + ////////////////////////////////////////////////////////////////////// + // Begin Program + ////////////////////////////////////////////////////////////////////// + + .text + +#include <gpe_macros.h> +#include <pss_macros.h> + + + //-------------------------------------------------------------------- + // Name: _perform_spi_transaction (MACRO) + // + // Description: Start SPI transaction, wait for 5usec, and then + // wait for operation to complete. + // + // Inputs: None + // + // Outputs: None (on error, D0 will contain status register) + // + // Modifies: CTR, D0, D1 + //-------------------------------------------------------------------- + .macro _perform_spi_transaction + + // Start SPI transaction + _putscom SPIPSS_P2S_COMMAND_REG, 0x8000000000000000 + + // wait 5usec + waits (5 * MICROSECONDS) + + _wait_for_spi_ops_complete 10, error_timeout + + .endm + + + //-------------------------------------------------------------------- + // PORE-GPE Routine Specification: + // + // Name: GPE_apss_initialize_gpio + // + // Description: Initialize APSS GPIO pins for Input/Output, Interrupt + // Drive H/L + // + // Inputs: G_gpe_apss_initialize_gpio_args - Error and G_gpio_config + // struct { + // PoreGpeErrorStruct error; + // apssGpioConfigStruct gpio_config0 // G_gpio_config[0] (input to APSS) + // apssGpioConfigStruct gpio_config1 // G_gpio_config[1] (input to APSS) + // } G_gpe_apss_initialize_gpio_args + // struct { + // uint64_t rc; // This should be read as 63:32=addr, 31:0=rc + // uint64_t ffdc; // Whatever GPE program puts in for FFDC data + // } PoreGpeErrorStruct; + // struct apssGpioConfigStruct + // { + // uint8_t direction; + // uint8_t drive; + // uint8_t interrupt; + // } + // + // Outputs: None (except FFDC on failure) + // + // Flow: 7/20/11 FN=GPE_apss_initialize_gpio + // + // References: APSS FUnctional Specification v0.7.18 + // GPE_apss_access_scoms.odt (summary of regisers/data) + // + // End PORE-GPE Routine Specification + //-------------------------------------------------------------------- + .global GPE_apss_initialize_gpio +GPE_apss_initialize_gpio: + + // Copy passed Structure Pointer into A1 + mr A1, ETR + halt // TULETA_HW_BRINGUP + + // Wait for SPI operations to be complete (up to 10usec timeout) + _wait_for_spi_ops_complete 10, error_timeout + + // Setup control regs + // frame_size=16, out_count=16, in_delay1=never, in_count2=16 + _putscom SPIPSS_P2S_CTRL_REG0, 0x410FC00004000000 + // bridge_enable, clock_divider=7, 2 frames + //_putscom SPIPSS_P2S_CTRL_REG1, 0x801C400000000000 + //_putscom SPIPSS_P2S_CTRL_REG1, 0x8074400000000000 //gm038 + _putscom SPIPSS_P2S_CTRL_REG1, 0x8090400000000000 //@gs039 + // inter_frame_delay=50 (5usec) + _putscom SPIPSS_P2S_CTRL_REG2, 0x0019000000000000 + + // Build apss commands based on gpio_config arguments + // Arguments are each 1 byte long and contain default + // value to be used to init each item (Direction/Drive/Interrupt) + + //// Port 0 + + // Port 0 - Direction (APSS cmd 0x40xx) + ldandi D0, CONFIG, A1, 0xFF00000000000000 + srdi D0, D0, 8 + ori D0, D0, 0x4000000000000000 + _putscom_d0 SPIPSS_P2S_WDATA_REG + + _perform_spi_transaction + + // Port 0 - Drive (APSS cmd 0x50xx) + ldandi D0, CONFIG, A1, 0x00FF000000000000 + ori D0, D0, 0x5000000000000000 + _putscom_d0 SPIPSS_P2S_WDATA_REG + + _perform_spi_transaction + + // Port 0 - Interrupt (APSS cmd 0x60xx) + ldandi D0, CONFIG, A1, 0x0000FF0000000000 + ori D0, D0, 0x0060000000000000 + sldi D0, D0, 8 + _putscom_d0 SPIPSS_P2S_WDATA_REG + + _perform_spi_transaction + + //// Port 1 + + // Port 1 - Direction (APSS cmd 0x41xx) + ldandi D0, CONFIG, A1, 0x000000FF00000000 + ori D0, D0, 0x0000410000000000 + sldi D0, D0, 16 + _putscom_d0 SPIPSS_P2S_WDATA_REG + + _perform_spi_transaction + + // Port 1 - Drive (APSS cmd 0x51xx) + ldandi D0, CONFIG, A1, 0x00000000FF000000 + ori D0, D0, 0x0000005100000000 + sldi D0, D0, 24 + _putscom_d0 SPIPSS_P2S_WDATA_REG + + _perform_spi_transaction + + // Port 1 - Interrups (APSS cmd 0x61xx) + ldandi D0, CONFIG, A1, 0x0000000000FF0000 + ori D0, D0, 0x0000000061000000 + sldi D0, D0, 32 + _putscom_d0 SPIPSS_P2S_WDATA_REG + + // Start SPI transaction (dont need to wait for p2s_ongoing bit since last cmd) + _putscom SPIPSS_P2S_COMMAND_REG, 0x8000000000000000 + + // wait 5usec + waits (5 * MICROSECONDS) + + halt // End of GPE_apss_initialize_gpio + + +error_statusreg: + // An error/reserved bit was set when reading p2s status register... + // D0: P2S_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0002 + halt + + +error_timeout: + // p2s_ongoing bit was never cleared after several retries... + // D0: P2S_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0001 + halt + + + ////////////////////////////////////////////////////////////////////// + // End of Program + ////////////////////////////////////////////////////////////////////// + + diff --git a/src/occ/gpe/apss_meas_read_complete.pS b/src/occ/gpe/apss_meas_read_complete.pS new file mode 100755 index 0000000..f16afb6 --- /dev/null +++ b/src/occ/gpe/apss_meas_read_complete.pS @@ -0,0 +1,143 @@ +# ***************************************************************************** +# @file apss_meas_read_complete.S +# @brief Finish reading power measurements from APSS +# + +# ***************************************************************************** +# +# @page ChangeLogs Change Logs +# @section apss_meas_read_complete.S APSS_MEAS_READ_COMPLETE.S +# @verbatim +# +# Flag Def/Fea Userid Date Description +# ------- ---------- -------- ---------- ---------------------------------- +# @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments +# @at023 910877 alvinwan 01/09/2014 Excessive fan increase requests error for mfg +# @gm026 916029 milesg 02/17/2014 revert back to auto2 mode without reading GPIO's +# +# @endverbatim +# +# ***************************************************************************** + + + ////////////////////////////////////////////////////////////////////// + // Includes + ////////////////////////////////////////////////////////////////////// + .nolist +#include "pgp.h" +#include "pgas.h" + .list + + ////////////////////////////////////////////////////////////////////// + // Define Address Space + ////////////////////////////////////////////////////////////////////// + .oci + + ////////////////////////////////////////////////////////////////////// + // Define Symbols + ////////////////////////////////////////////////////////////////////// + +#include <pss_constants.h> + +#define GPE_PROG_ID 0x0006 + + ////////////////////////////////////////////////////////////////////// + // Define Structures + ////////////////////////////////////////////////////////////////////// + + // Declare the offsets of the struct that will be passed to the + // GPE program via the ETR register + // + // struct G_gpe_apss_continue_pwr_meas_read_args = + // { + .struct 0 +ERROR_RC: + .struct ERROR_RC + 8 +ERROR_FFDC: + .struct ERROR_FFDC + 8 +MEASUREMENTS: + .struct MEASUREMENTS + 24 +MEASUREMENTS_TOD: + // }; + + + ////////////////////////////////////////////////////////////////////// + // Begin Program + ////////////////////////////////////////////////////////////////////// + + .text + +#include <gpe_macros.h> +#include <pss_macros.h> + + //-------------------------------------------------------------------- + // PORE-GPE Routine Specification: + // + // Name: GPE_apss_complete_pwr_meas_read + // + // Description: Kick of the power measurement from APSS + // + // Inputs: G_gpe_complete_pwr_meas_read_args + // struct { + // PoreGpeErrorStruct error; + // ApssPwrMeas_t meas; + // uint64_t meas_data[4]; // G_apss_pwr_meas (2nd block of data) (output from APSS) + // } G_gpe_complete_pwr_meas_read_args + // struct { + // uint64_t rc; // This should be read as 63:32=addr, 31:0=rc + // uint64_t ffdc; // Whatever GPE program puts in for FFDC data + // } PoreGpeErrorStruct; + // + // Outputs: ApssPwrMeas (measurement data) + // GPE_complete_pwr_meas_read (error on failure) + // + // Flow: 7/20/11 FN=GPE_apss_complete_pwr_meas_read + // + // References: APSS FUnctional Specification v0.7.18 + // GPE_apss_access_scoms.odt (summary of regisers/data) + // + // End PORE-GPE Routine Specification + //-------------------------------------------------------------------- + .global GPE_apss_complete_pwr_meas_read +GPE_apss_complete_pwr_meas_read: + + // Copy passed Structure Pointer into A1 + mr A1, ETR + + // Wait for up to 5us for spi op complete, else branch to error_timeout + _wait_for_adc_ops_complete 100, error_timeout + + // Read/save last 32 bytes of data and Time of Day + //_getscom SPIPSS_ADC_RDATA_REG0 + //std D0, MEASUREMENTS, A1 //gm026 + + //_getscom SPIPSS_ADC_RDATA_REG1 + //std D0, (MEASUREMENTS + 8), A1 //gm026 + + // REG2,3 not needed (all measurements fit in above data) + + _getscom TOD_VALUE_REG + std D0, MEASUREMENTS_TOD, A1 + + halt // End of GPE_apss_complete_pwr_meas_read + + +error_statusreg: + // An error/reserved bit was set when reading adc status register... + // D0: ADC_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0002 + halt + + +error_timeout: + // adc_ongoing bit was never cleared after several retries... + // D0: ADC_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0001 + halt + + + ////////////////////////////////////////////////////////////////////// + // End of Program + ////////////////////////////////////////////////////////////////////// + + diff --git a/src/occ/gpe/apss_meas_read_cont.pS b/src/occ/gpe/apss_meas_read_cont.pS new file mode 100755 index 0000000..1b71c9b --- /dev/null +++ b/src/occ/gpe/apss_meas_read_cont.pS @@ -0,0 +1,161 @@ +# ***************************************************************************** +# @file apss_meas_read_cont.S +# @brief Continue reading power measurements from APSS +# + +# ***************************************************************************** +# +# @page ChangeLogs Change Logs +# @section apss_meas_read_cont.S APSS_MEAS_READ_CONT.S +# @verbatim +# +# Flag Def/Fea Userid Date Description +# ------- ---------- -------- ---------- ---------------------------------- +# @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments +# @ly003 861535 lychen 11/19/2012 Remove APSS configuration/gathering of Altitude & Temperature +# @at023 910877 alvinwan 01/09/2014 Excessive fan increase requests error for mfg +# @gm026 916029 milesg 02/17/2014 revert back to auto2 mode without reading GPIO's +# @gm038 926761 milesg 05/16/2014 slowed SPI bus down from 12MHz to 10MHz on venice (8MHz on murano) +# +# @endverbatim +# +# ***************************************************************************** + + + ////////////////////////////////////////////////////////////////////// + // Includes + ////////////////////////////////////////////////////////////////////// + .nolist +#include "pgp.h" +#include "pgas.h" + .list + + ////////////////////////////////////////////////////////////////////// + // Define Address Space + ////////////////////////////////////////////////////////////////////// + .oci + + ////////////////////////////////////////////////////////////////////// + // Define Symbols + ////////////////////////////////////////////////////////////////////// + +#include <pss_constants.h> + +#define GPE_PROG_ID 0x0005 + + ////////////////////////////////////////////////////////////////////// + // Define Structures + ////////////////////////////////////////////////////////////////////// + + // Declare the offsets of the struct that will be passed to the + // GPE program via the ETR register + // + // struct G_gpe_apss_continue_pwr_meas_read_args = + // { + .struct 0 +ERROR_RC: + .struct ERROR_RC + 8 +ERROR_FFDC: + .struct ERROR_FFDC + 8 +MEASUREMENTS: + // }; + + + ////////////////////////////////////////////////////////////////////// + // Begin Program + ////////////////////////////////////////////////////////////////////// + + .text + +#include <gpe_macros.h> +#include <pss_macros.h> + + //-------------------------------------------------------------------- + // PORE-GPE Routine Specification: + // + // Name: GPE_apss_continue_pwr_meas_read + // + // Description: Kick of the power measurement from APSS + // + // Inputs: G_gpe_continue_pwr_meas_read_args + // struct { + // PoreGpeErrorStruct error; + // uint64_t meas_data[4]; // G_apss_pwr_meas (1st block of data) (output from APSS) + // } G_gpe_continue_pwr_meas_read_args + // struct { + // uint64_t rc; // This should be read as 63:32=addr, 31:0=rc + // uint64_t ffdc; // Whatever GPE program puts in for FFDC data + // } PoreGpeErrorStruct; + // + // Outputs: GPE_continue_pwr_meas_read (error on failure) + // + // Flow: 7/20/11 FN=GPE_apss_continue_pwr_meas_read + // + // References: APSS FUnctional Specification v0.7.18 + // GPE_apss_access_scoms.odt (summary of regisers/data) + // + // End PORE-GPE Routine Specification + //-------------------------------------------------------------------- + .global GPE_apss_continue_pwr_meas_read +GPE_apss_continue_pwr_meas_read: + + // Copy passed Structure Pointer into A1 + mr A1, ETR + + // Wait for up to 5us for spi op complete, else branch to error_timeout + _wait_for_adc_ops_complete 100, error_timeout + + // Read/save first 32 bytes of data + _getscom SPIPSS_ADC_RDATA_REG0 // Verified + std D0, MEASUREMENTS, A1 + + _getscom SPIPSS_ADC_RDATA_REG1 // Verified + std D0, (MEASUREMENTS + 8), A1 + + _getscom SPIPSS_ADC_RDATA_REG2 // Verified + std D0, (MEASUREMENTS + 16), A1 + + _getscom SPIPSS_ADC_RDATA_REG3 // Verified + std D0, (MEASUREMENTS + 24), A1 + + // Commented out reading of GPIO data -- gm026 + // Delay between frames. Interframe delay are all 5usec + // Without this delay, can't get correct gpio data + //waits (5 * MICROSECONDS) // @at023a + // Setup control regs + // frame_size=16, out_count=16, in_count=16 + //_putscom SPIPSS_ADC_CTRL_REG0, 0x4000100000000000 // @at023c + // ADC FSM, clock_divider=7, frames=2 // @ly003c ignore temperature + //_putscom SPIPSS_ADC_CTRL_REG1, 0x8060400000000000 + //_putscom SPIPSS_ADC_CTRL_REG1, 0x8074400000000000 //gm038 + // ADC interframe delay (5usec) + //_putscom SPIPSS_ADC_CTRL_REG2, 0x0019000000000000 + + // APSS command to continue previous command + //_putscom SPIPSS_ADC_WDATA_REG, 0x0000000000000000 + + // Start SPI transaction + //_putscom SPIPSS_ADC_COMMAND_REG, 0x8000000000000000 + + halt // End of GPE_apss_initialize_gpio + + +error_statusreg: + // An error/reserved bit was set when reading adc status register... + // D0: ADC_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0002 + halt + + +error_timeout: + // adc_ongoing bit was never cleared after several retries... + // D0: ADC_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0001 + halt + + + ////////////////////////////////////////////////////////////////////// + // End of Program + ////////////////////////////////////////////////////////////////////// + + diff --git a/src/occ/gpe/apss_meas_read_start.pS b/src/occ/gpe/apss_meas_read_start.pS new file mode 100755 index 0000000..b8cae79 --- /dev/null +++ b/src/occ/gpe/apss_meas_read_start.pS @@ -0,0 +1,144 @@ +# ***************************************************************************** +# @file apss_meas_read_start.S +# @brief Kick of the reading of power measurement from APSS +# + +# ***************************************************************************** +# +# @page ChangeLogs Change Logs +# @section apss_meas_read_start.S APSS_MEAS_READ_START.S +# @verbatim +# +# Flag Def/Fea Userid Date Description +# ------- ---------- -------- ---------- ---------------------------------- +# @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments +# @gm038 926761 milesg 05/16/2014 slowed SPI bus down from 12MHz to 10MHz on venice (8MHz on murano) +# @gs039 936836 gjsilva 08/28/2014 slowed SPI bus down from 10MHz to 8MHz on venice (~6MHz on murano) +# +# @endverbatim +# +# ***************************************************************************** + + + ////////////////////////////////////////////////////////////////////// + // Includes + ////////////////////////////////////////////////////////////////////// + .nolist +#include "pgp.h" +#include "pgas.h" + .list + + ////////////////////////////////////////////////////////////////////// + // Define Address Space + ////////////////////////////////////////////////////////////////////// + .oci + + ////////////////////////////////////////////////////////////////////// + // Define Symbols + ////////////////////////////////////////////////////////////////////// + +#include <pss_constants.h> + +#define GPE_PROG_ID 0x0004 + + ////////////////////////////////////////////////////////////////////// + // Define Structures + ////////////////////////////////////////////////////////////////////// + + // Declare the offsets of the struct that will be passed to the + // GPE program via the ETR register + // + // struct G_gpe_apss_start_pwr_meas_read_args = + // { + .struct 0 +ERROR_RC: + .struct ERROR_RC + 8 +ERROR_FFDC: + .struct ERROR_FFDC + 8 + // }; + + + ////////////////////////////////////////////////////////////////////// + // Begin Program + ////////////////////////////////////////////////////////////////////// + + .text + +#include <gpe_macros.h> +#include <pss_macros.h> + + //-------------------------------------------------------------------- + // PORE-GPE Routine Specification: + // + // Name: GPE_apss_start_pwr_meas_read + // + // Description: Kick of the power measurement from APSS + // + // Inputs: G_gpe_apss_start_pwr_meas_read_args + // struct { + // PoreGpeErrorStruct error; + // } G_gpe_apss_start_pwr_meas_read_args + // struct { + // uint64_t rc; // This should be read as 63:32=addr, 31:0=rc + // uint64_t ffdc; // Whatever GPE program puts in for FFDC data + // } PoreGpeErrorStruct; + // + // Outputs: GPE_start_pwr_meas_read (error on failure) + // + // Flow: 7/20/11 FN=GPE_apss_start_pwr_meas_read + // + // References: APSS FUnctional Specification v0.7.18 + // GPE_apss_access_scoms.odt (summary of regisers/data) + // + // End PORE-GPE Routine Specification + //-------------------------------------------------------------------- + .global GPE_apss_start_pwr_meas_read +GPE_apss_start_pwr_meas_read: + + // Copy passed Structure Pointer into A1 + mr A1, ETR + + // Wait for up to 5us for spi op complete, else branch to error_timeout + _wait_for_adc_ops_complete 5, error_timeout + + // Setup control regs + // frame_size=16, out_count=16, in_count=16 + ////_putscom SPIPSS_ADC_CTRL_REG0, 0x4100100000000000 + _putscom SPIPSS_ADC_CTRL_REG0, 0x4000100000000000 // Verified + // ADC FSM, clock_divider=7, frames=16 + ////_putscom SPIPSS_ADC_CTRL_REG1, 0x801FC00000000000 + ////_putscom SPIPSS_ADC_CTRL_REG1, 0x8063c00000000000 // Verified + //_putscom SPIPSS_ADC_CTRL_REG1, 0x8077c00000000000 //gm038 + _putscom SPIPSS_ADC_CTRL_REG1, 0x8093c00000000000 //@gs039 + // ADC interframe delay (5usec) + ////_putscom SPIPSS_ADC_CTRL_REG2, 0x0019000000000000 + _putscom SPIPSS_ADC_CTRL_REG2, 0x0019000000000000 // Verified + + // APSS command to continue previous command + _putscom SPIPSS_ADC_WDATA_REG, 0x0000000000000000 // Verified + + // Start SPI transaction + _putscom SPIPSS_ADC_COMMAND_REG, 0x8000000000000000 // Verified + + halt // End of GPE_apss_initialize_gpio + + +error_statusreg: + // An error/reserved bit was set when reading adc status register... + // D0: ADC_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0002 + halt + + +error_timeout: + // adc_ongoing bit was never cleared after several retries... + // D0: ADC_STATUS_REG + _saveffdc GPE_PROG_ID, 0x0001 + halt + + + ////////////////////////////////////////////////////////////////////// + // End of Program + ////////////////////////////////////////////////////////////////////// + + diff --git a/src/occ/gpe/gpe_export.h b/src/occ/gpe/gpe_export.h new file mode 100755 index 0000000..3301a2d --- /dev/null +++ b/src/occ/gpe/gpe_export.h @@ -0,0 +1,67 @@ +/****************************************************************************** +// @file gpe_export.h +// @brief This file contains structures, etc, that are needed +// by applications external to the GPE +*/ +/****************************************************************************** + * + * @page ChangeLogs Change Logs + * @section gpe_export.h GPE_EXPORT.H + * @verbatim + * + * Flag Def/Fea Userid Date Description + * ------- ---------- -------- ---------- ---------------------------------- + * @cc000 cjcain 08/04/2011 Created + * @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments + * + * @endverbatim + * + *///*************************************************************************/ + +#ifndef _GPE_EXPORT_H +#define _GPE_EXPORT_H + +//************************************************************************* +// Includes +//************************************************************************* + +//************************************************************************* +// Externs +//************************************************************************* + +//************************************************************************* +// Macros +//************************************************************************* + +//************************************************************************* +// Defines/Enums +//************************************************************************* + +//************************************************************************* +// Structures +//************************************************************************* +typedef struct { + union + { + struct { + uint32_t rc; + uint32_t addr; + }; + uint64_t error; + }; + uint64_t ffdc; +} PoreGpeErrorStruct; // Same for every GPE program + +//************************************************************************* +// Globals +//************************************************************************* + +//************************************************************************* +// Function Prototypes +//************************************************************************* + +//************************************************************************* +// Functions +//************************************************************************* + +#endif //_GPE_EXPORT_H diff --git a/src/occ/gpe/gpe_macros.h b/src/occ/gpe/gpe_macros.h new file mode 100755 index 0000000..4a54eeb --- /dev/null +++ b/src/occ/gpe/gpe_macros.h @@ -0,0 +1,178 @@ +/****************************************************************************** +// @file gpe_macros.h +// @brief Common macros for the APSS/DPSS code +*/ +/****************************************************************************** + * + * @page ChangeLogs Change Logs + * @section gpe_macros.h GPE_MACROS.H + * @verbatim + * + * Flag Def/Fea Userid Date Description + * ------- ---------- -------- ---------- ---------------------------------- + * + * @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments + * + * @endverbatim + * + *///*************************************************************************/ + +//************************************************************************* +// Includes +//************************************************************************* + +//************************************************************************* +// Externs +//************************************************************************* + +//************************************************************************* +// Macros +//************************************************************************* + + //-------------------------------------------------------------------- + // Macro Specification: + // + // Name: _saveffdc + // + // Description: Save FFDC into error structure + // + // struct { + // uint64_t rc; // This should be read as 63:32=addr, 31:0=rc + // uint64_t ffdc; // Whatever GPE program puts in for FFDC data + // } PoreGpeErrorStruct; + // + // - Copy D0 into PoreGpeErrorStruct->ffdc + // - Copy \gpe_id into PoreGpeErrorStruct->rc[63:32] + // - Copy \rc into PoreGpeErrorStruct->rc[31:0] + // + // Inputs: \gpe_id - Unique GPE program number to identify what prog failed + // \rc - Unique GPE error code that will indicate failure + // ETR - Assumed to be set to base address of + // passed argument structure + // + // End Macro Specification + //-------------------------------------------------------------------- + .macro _saveffdc, gpe_id, rc + + // Make sure passed Structure Pointer is loaded into A1 + mr A1, ETR + + // Save address to send back (upper word of D1) + srdi D1, D1, 32 + // TODO: Simcs does not support SPRG0 yet, so use 24 bit CTR for now + //mr SPRG0, D1 + mr CTR, D1 + + // Check if rc was already saved... + ld D1, 0, A1 + andi D1, D1, 0xFFFFFFFF00000000 + branz D1, 1f + + // Save D0 into FFDC of error structure + std D0, 8, A1 + ld D0, 8, A1 + + // Save address to send back... (truncated to 24 bits) + mr D0, CTR + // Save GPE progam ID + li D1, \gpe_id + sldi D1, D1, 16 + // and return code + ori D1, D1, \rc + sldi D1, D1, 32 + // combine GPE program/RC with address + or D0, D0, D1 + + // Save data into error structure + std D0, 0, A1 + ld D0, 8, A1 + ld D0, 0, A1 + +1: + .endm + + + //-------------------------------------------------------------------- + // Macro Specification: + // + // Name: _getscom + // + // Description: Get a SCOM based on passed in Address, put it in D0 + // + // Inputs: SCOM Address + // + // Outputs: D0 - Result of SCOM + // + // End Macro Specification + //-------------------------------------------------------------------- + .macro _getscom, address + + lpcs P0, \address + ld D0, \address, P0 + + .endm + + //-------------------------------------------------------------------- + // Macro Specification: + // + // Name: _putscom + // + // Description: Store data into SCOM based on passed in Address + // + // Inputs: SCOM Address, Data + // + // Outputs: None + // + // End Macro Specification + //-------------------------------------------------------------------- + .macro _putscom, address, data + + lpcs P0, \address + li D0, \data + std D0, \address, P0 + + .endm + + //-------------------------------------------------------------------- + // Macro Specification: + // + // Name: _putscom_d0 + // + // Description: Store D0 into SCOM based on passed in Address + // + // Inputs: SCOM Address + // + // Outputs: None + // + // End Macro Specification + //-------------------------------------------------------------------- + .macro _putscom_d0, address + + lpcs P0, \address + std D0, \address, P0 + + .endm + +//************************************************************************* +// Defines/Enums +//************************************************************************* + #define TOD_VALUE_REG 0x00040020 + + // Constant for use in wait statments: waits (5 * MICROSECONDS) + #define MICROSECONDS 600 + +//************************************************************************* +// Structures +//************************************************************************* + +//************************************************************************* +// Globals +//************************************************************************* + +//************************************************************************* +// Function Prototypes +//************************************************************************* + +//************************************************************************* +// Functions +//************************************************************************* diff --git a/src/occ/gpe/pore_nop.pS b/src/occ/gpe/pore_nop.pS new file mode 100755 index 0000000..923b00f --- /dev/null +++ b/src/occ/gpe/pore_nop.pS @@ -0,0 +1,41 @@ +// $Id$ + +/// \file pore_nop.S +/// \brief A Quick NOP Program for PORE Model Timing +/// +/// Used to generate the worst case timings for the AMEC +/// sensors. + + .nolist +#include "pgp.h" +#include "pgas.h" + .list + + .oci + + .data + + .text + + .global GPE_pore_nop + + /// Run a nop instruction and then halt GPE +GPE_pore_nop: + nop + + /// ----------------------------------------------------- + /// Only compile this in to test delaying PORE-GPE engine + .ifdef DELAY_PORE_NOP + li CTR, 120 +delay_loop: + waits 600 + nop + loop delay_loop +done: + .endif + /// ----------------------------------------------------- + + halt + + .epilogue GPE_pore_nop + diff --git a/src/occ/gpe/pore_test.pS b/src/occ/gpe/pore_test.pS new file mode 100755 index 0000000..f02c985 --- /dev/null +++ b/src/occ/gpe/pore_test.pS @@ -0,0 +1,74 @@ +# ***************************************************************************** +# @file pore_test.S +# @brief A Quick Test Program for PORE Model +# Delays for X (passed in) uS before halting PORE-GPE +# program. + +# ***************************************************************************** +# +# @page ChangeLogs Change Logs +# @section pore_test.S PORE_TEST.S +# @verbatim +# +# Flag Def/Fea Userid Date Description +# ------- ---------- -------- ---------- ---------------------------------- +# @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments +# +# @endverbatim +# +# ***************************************************************************** + + + .nolist +#include "pgp.h" +#include "pgas.h" + .list + + .oci + +// Parameter offsets + + .data + + .global jmptable + .align 3 +jmptable: // Error Handlers are replaced with Halts + .quad 0x0200000000000000 // Halt on Error 0 + .quad 0x0000000002000000 // Halt on Error 1 + .quad 0x0000000000000000 + .quad 0x0200000000000000 // Halt on error 2 + .quad 0x0000000002000000 // Halt on error 3 + .quad 0x0000000000000000 + .quad 0x0200000000000000 // Halt on Error 4 + .quad 0x0000000002000000 // Halt on error 5 + .quad 0x0000000000000000 + .quad 0x0200000000000000 // Halt on Error 6 + .quad 0x0000000002000000 // Halt on error 7 + .quad 0x0000000000000000 + .quad 0xA200000000003fff // BRAI pore_test + .quad 0xc146000000000000 // second word is not used + + .global scratchspace + .align 3 +scratchspace: + .quad 0x0000000000000010 // Data scratch space + .quad 0x0000000000000020 + .quad 0x0000000000000030 + .quad 0x0000000000000040 + + .text + + .global pore_test +pore_test: + + // Read parameter into CTR + mr CTR, ETR +delay_loop: + waits 600 + nop + loop delay_loop +done: + halt // End of main + +// .epilogue pore_test + diff --git a/src/occ/gpe/pore_test_error.pS b/src/occ/gpe/pore_test_error.pS new file mode 100755 index 0000000..344bdcb --- /dev/null +++ b/src/occ/gpe/pore_test_error.pS @@ -0,0 +1,246 @@ +# ***************************************************************************** +# @file pore_test_error.S +# @brief A Quick Test Program for PORE Model +# Delays for X (passed in) uS before halting PORE-GPE +# program. Always sets an error + +# ***************************************************************************** +# +# @page ChangeLogs Change Logs +# @section pore_test_error.S PORE_TEST_ERROR.S +# @verbatim +# +# Flag Def/Fea Userid Date Description +# ------- ---------- -------- ---------- ---------------------------------- +# @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments +# +# @endverbatim +# +# ***************************************************************************** + + +// Input: +// struct { +// uint64_t rc; // This should be read as 63:32=addr, 31:0=rc +// uint64_t ffdc; // Whatever GPE program puts in for FFDC data +// } PoreGpeErrorStruct; +// +// struct { +// PoreGpeErrorStruct error; +// uint32_t pore_delay; +// } PoreSimpleArgs; +// +// +// + + ////////////////////////////////////////////////////////////////////// + // Includes + ////////////////////////////////////////////////////////////////////// + .nolist +#include "pgp.h" +#include "pgas.h" + .list + + ////////////////////////////////////////////////////////////////////// + // Define Address Space + ////////////////////////////////////////////////////////////////////// + .oci + + ////////////////////////////////////////////////////////////////////// + // Define Symbols + ////////////////////////////////////////////////////////////////////// +#define TOD_VALUE_REG 0x00040020 +#define SPIPSS_REGISTER_BASE 0x00020000 +#define SPIPSS_ADC_CTRL_REG0 (SPIPSS_REGISTER_BASE + 0x00) +#define SPIPSS_ADC_CTRL_REG1 (SPIPSS_REGISTER_BASE + 0x01) +#define SPIPSS_ADC_CTRL_REG2 (SPIPSS_REGISTER_BASE + 0x02) +#define SPIPSS_ADC_STATUS_REG (SPIPSS_REGISTER_BASE + 0x03) +#define SPIPSS_ADC_COMMAND_REG (SPIPSS_REGISTER_BASE + 0x04) +#define SPIPSS_ADC_WDATA_REG (SPIPSS_REGISTER_BASE + 0x10) +#define SPIPSS_ADC_RDATA_REG0 (SPIPSS_REGISTER_BASE + 0x20) +#define SPIPSS_ADC_RDATA_REG1 (SPIPSS_REGISTER_BASE + 0x21) +#define SPIPSS_ADC_RDATA_REG2 (SPIPSS_REGISTER_BASE + 0x22) +#define SPIPSS_ADC_RDATA_REG3 (SPIPSS_REGISTER_BASE + 0x23) +#define SPIPSS_P2S_CTRL_REG0 (SPIPSS_REGISTER_BASE + 0x40) +#define SPIPSS_P2S_CTRL_REG1 (SPIPSS_REGISTER_BASE + 0x41) +#define SPIPSS_P2S_CTRL_REG2 (SPIPSS_REGISTER_BASE + 0x42) +#define SPIPSS_P2S_STATUS_REG (SPIPSS_REGISTER_BASE + 0x43) +#define SPIPSS_P2S_COMMAND_REG (SPIPSS_REGISTER_BASE + 0x44) +#define SPIPSS_P2S_WDATA_REG (SPIPSS_REGISTER_BASE + 0x50) +#define SPIPSS_P2S_RDATA_REG (SPIPSS_REGISTER_BASE + 0x60) + + + .set GPE_PROG_ID, 100 + .set GPE_ERROR_CODE, 0xAA55AA55 + .set GPE_ERROR_RC, 0xBEEFCAFE + + ////////////////////////////////////////////////////////////////////// + // Define Structures + ////////////////////////////////////////////////////////////////////// + + // Declare the offsets of the struct that will be passed to the + // GPE program via the ETR register + // + // struct PoreSimpleArgs = + // { + .struct 0 +RETURN_CODE: + .struct RETURN_CODE + 8 +FFDC: + .struct FFDC + 8 +PORE_DELAY: + // }; + + ////////////////////////////////////////////////////////////////////// + // Begin Program + ////////////////////////////////////////////////////////////////////// + + .text + + //-------------------------------------------------------------------- + // Macro Specification: + // + // Name: _saveffdc + // + // Description: Save off RC, FFDC & Address when there is an error + // in a GPE program. + // + // - Copy D0 into PoreGpeErrorStruct->ffdc + // - Copy D1[63:32] into PoreGpeErrorStruct->rc[63:32] + // - Copy \error_code into PoreGpeErrorStruct->rc[31:0] + // + // Inputs: \error_code - Unique GPE error code that will + // indicate the failure mode of the GPE + // program. + // D0 - Set to FFDC data that will be copied to + // PoreGpeErrorStruct->ffdc + // D1 - Bits[63:32] set to address that will be + // copied to PoreGpeErrorStruct->rc[63:32] + // ETR - Assumed to be set to base address of + // passed argument structure + // + // End Macro Specification + //-------------------------------------------------------------------- + .macro _saveffdc, error_code + + // Make sure passed Structure Pointer is loaded into A1 + mr A1, ETR + + // First save off D0 into FFDC + std D0, FFDC, A1 + + // Then save off SPRG0 into the lower 32 bits of D0 + // TODO: SPRG0 doesn't work in Simics....switching to D1 for now + mr D0, D1 + + // Save off the address of the start of the GPE program into the + // upper 32 bits of D0 + li D1, \error_code + sldi D1, D1, 32 + or D0, D0, D1 + + // Save register off into code_addr + std D0, RETURN_CODE, A1 + + .endm + + + //-------------------------------------------------------------------- + // Macro Specification: + // + // Name: _getscom + // + // Description: Get a SCOM based on passed in Address, put it in D0 + // + // Inputs: SCOM Address + // + // Outputs: D0 - Result of SCOM + // + // End Macro Specification + //-------------------------------------------------------------------- + .macro _getscom, address + + lpcs P0, \address + ld D0, \address, P0 + + .endm + + //-------------------------------------------------------------------- + // Macro Specification: + // + // Name: _putscom + // + // Description: Get a SCOM based on passed in Address, put it in D0 + // + // Inputs: SCOM Address, Data + // + // Outputs: None + // + // End Macro Specification + //-------------------------------------------------------------------- + .macro _putscom, address, data + + lpcs P0, \address + li D0, \data + std D0, \address, P0 + + .endm + + + //-------------------------------------------------------------------- + // PORE-GPE Routine Specification: + // + // Name: pore_test_error + // + // Description: Delays for X (passed in) uS before halting PORE-GPE + // routine. Always sets the ffdc to indicate an error + // with a RC of 0xDEADBEEF + // + // Inputs: PoreSimpleArgs - FFDC & uS to delay. + // + // Outputs: None (except FFDC on failure) + // + // End PORE-GPE Routine Specification + //-------------------------------------------------------------------- + .global pore_test_error +pore_test_error: + // Copy passed Structure Pointer into A1 + mr A1, ETR + + // Read pore_delay parameter into D0 + ld D0, PORE_DELAY, A1 + + // Shift Right so that we only use the upper 32 bits + // (not passed in as 64 bit value) + srdi D0, D0, 32 + + // Copy pore_delay into CTR so that we can loop + mr CTR, D0 + + // Set D0 to a value for some fake operation we are testing out + li D0, GPE_ERROR_CODE + li D1, GPE_ERROR_CODE + + trap +delay_loop: + waits 600 + nop + loop delay_loop + trap + + //bra done +error: + _getscom TOD_VALUE_REG + + _saveffdc 0xDEADBEEF + +done: + + + + halt // End of pore_test + + ////////////////////////////////////////////////////////////////////// + // End of Program + ////////////////////////////////////////////////////////////////////// + diff --git a/src/occ/gpe/pore_test_pss.pS b/src/occ/gpe/pore_test_pss.pS new file mode 100755 index 0000000..a65c935 --- /dev/null +++ b/src/occ/gpe/pore_test_pss.pS @@ -0,0 +1,444 @@ +# ***************************************************************************** +# @file pore_test_pss.S +# @brief A Quick Test Program for PORE Model +# Delays for X (passed in) uS before halting PORE-GPE +# program. Always sets an error + +# ***************************************************************************** +# +# @page ChangeLogs Change Logs +# @section pore_test_pss.S PORE_TEST_PSS.S +# @verbatim +# +# Flag Def/Fea Userid Date Description +# ------- ---------- -------- ---------- ---------------------------------- +# @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments +# +# @endverbatim +# +# ***************************************************************************** + + +// Input: +// struct { +// uint64_t rc; // This should be read as 63:32=addr, 31:0=rc +// uint64_t ffdc; // Whatever GPE program puts in for FFDC data +// } PoreGpeErrorStruct; +// +// struct { +// PoreGpeErrorStruct error; +// uint64_t adc[4]; +// uint64_t tod; +// } PoreSimpleArgs; +// +// +// + + ////////////////////////////////////////////////////////////////////// + // Includes + ////////////////////////////////////////////////////////////////////// + .nolist +#include "pgp.h" +#include "pgas.h" + .list + + ////////////////////////////////////////////////////////////////////// + // Define Address Space + ////////////////////////////////////////////////////////////////////// + .oci + + ////////////////////////////////////////////////////////////////////// + // Define Symbols + ////////////////////////////////////////////////////////////////////// +#define TOD_VALUE_REG 0x00040020 +#define SPIPSS_REGISTER_BASE 0x00020000 +#define SPIPSS_ADC_CTRL_REG0 (SPIPSS_REGISTER_BASE + 0x00) +#define SPIPSS_ADC_CTRL_REG1 (SPIPSS_REGISTER_BASE + 0x01) +#define SPIPSS_ADC_CTRL_REG2 (SPIPSS_REGISTER_BASE + 0x02) +#define SPIPSS_ADC_STATUS_REG (SPIPSS_REGISTER_BASE + 0x03) +#define SPIPSS_ADC_COMMAND_REG (SPIPSS_REGISTER_BASE + 0x04) +#define SPIPSS_ADC_WDATA_REG (SPIPSS_REGISTER_BASE + 0x10) +#define SPIPSS_ADC_RDATA_REG0 (SPIPSS_REGISTER_BASE + 0x20) +#define SPIPSS_ADC_RDATA_REG1 (SPIPSS_REGISTER_BASE + 0x21) +#define SPIPSS_ADC_RDATA_REG2 (SPIPSS_REGISTER_BASE + 0x22) +#define SPIPSS_ADC_RDATA_REG3 (SPIPSS_REGISTER_BASE + 0x23) +#define SPIPSS_P2S_CTRL_REG0 (SPIPSS_REGISTER_BASE + 0x40) +#define SPIPSS_P2S_CTRL_REG1 (SPIPSS_REGISTER_BASE + 0x41) +#define SPIPSS_P2S_CTRL_REG2 (SPIPSS_REGISTER_BASE + 0x42) +#define SPIPSS_P2S_STATUS_REG (SPIPSS_REGISTER_BASE + 0x43) +#define SPIPSS_P2S_COMMAND_REG (SPIPSS_REGISTER_BASE + 0x44) +#define SPIPSS_P2S_WDATA_REG (SPIPSS_REGISTER_BASE + 0x50) +#define SPIPSS_P2S_RDATA_REG (SPIPSS_REGISTER_BASE + 0x60) + + +#define GPE_PROG_ID 0xDEAD + +#define GPE_ERROR_P2S_ONGOING_TIMEOUT 0x0001 +#define GPE_ERROR_PIB_TIMEOUT 0xFF00 + + .set GPE_ERROR_CODE, 0xAA55AA55 + .set GPE_ERROR_RC, 0xBEEFCAFE + + ////////////////////////////////////////////////////////////////////// + // Define Structures + ////////////////////////////////////////////////////////////////////// + + // Declare the offsets of the struct that will be passed to the + // GPE program via the ETR register + // + // struct PoreSimpleArgs = + // { + .struct 0 +RETURN_CODE: + .struct RETURN_CODE + 8 +FFDC: + .struct FFDC + 8 +ADC0: + .struct ADC0 + 8 +ADC1: + .struct ADC1 + 8 +ADC2: + .struct ADC2 + 8 +ADC3: + .struct ADC3 + 8 +TOD: + + // }; + + ////////////////////////////////////////////////////////////////////// + // Begin Program + ////////////////////////////////////////////////////////////////////// + + .text + + //-------------------------------------------------------------------- + // Macro Specification: + // + // Name: _saveffdc + // + // Description: Save off RC, FFDC & Address when there is an error + // in a GPE program. + // + // - Copy D0 into PoreGpeErrorStruct->ffdc + // - Copy D1[63:32] into PoreGpeErrorStruct->rc[63:32] + // - Copy \error_code into PoreGpeErrorStruct->rc[31:0] + // + // Inputs: \error_code - Unique GPE error code that will + // indicate the failure mode of the GPE + // program. + // D0 - Set to FFDC data that will be copied to + // PoreGpeErrorStruct->ffdc + // D1 - Bits[63:32] set to address that will be + // copied to PoreGpeErrorStruct->rc[63:32] + // ETR - Assumed to be set to base address of + // passed argument structure + // + // End Macro Specification + //-------------------------------------------------------------------- + .macro _saveffdc, error_code + + // Make sure passed Structure Pointer is loaded into A1 + mr A1, ETR + +//.ifdef SIMICS_SPRG0_WORKING + // Copy D1[32:63] into SPRG0 + mr D1, SPRG0 + + // Now Read RETURN_CODE into D1, check to see if it is 0 + ld D1, RETURN_CODE, A1 + + // If it is not 0, then don't save off any FFDC + branz D1, 1f +//.endif + + // Copy SPRG0 into D1[32:63] + mr SPRG0, D1 + + // First save off D0 into FFDC + std D0, FFDC, A1 + + // Then save off D1[32:63] into the lower 32 bits [32:63] of D0 + mr D0, D1 + + // Save off the passed \error_code into the upper 32 bits of D0 + li D1, \error_code + sldi D1, D1, 32 + or D0, D0, D1 + + // Save register off into code_addr + std D0, RETURN_CODE, A1 +1: + .endm + + //-------------------------------------------------------------------- + // Macro Specification: + // + // Name: _saveffdc3 + // + // Description: Get a SCOM based on passed in Address, put it in D0 + // + // Inputs: SCOM Address + // + // Outputs: D0 - Result of SCOM + // + // End Macro Specification + //-------------------------------------------------------------------- + .macro _saveffdc3, gpe_id, error_code + + // This will cause an "Invalid Instruction Code" Error in the PORE-GPE + // which will cause an "error event 2" interrupt to the PPC405 + .long 0xAABBCCDD + + // The PPC405 will then be able to read the "Invalid Instruction Code" + // out of the IBUF_01 Register, which will contain the AABBCCDD opcode + // as well as the \gpe_id and \error_code. + .short \gpe_id + .short \error_code + + // The PPC405 ISR will then grab & place into PoreRequestStruct: + // IBUF_01[32:63] (32b) + // DBG0 (64b) + // DBG1 (64b) + // D0 (64b) + // D1[32:63] (32b) + // A0 & A1 (64b) + // -------- ----- + // Total 40 Bytes + + .endm + + + + //-------------------------------------------------------------------- + // Macro Specification: + // + // Name: _getscom + // + // Description: Get a SCOM based on passed in Address, put it in D0 + // + // Inputs: SCOM Address + // + // Outputs: D0 - Result of SCOM + // + // End Macro Specification + //-------------------------------------------------------------------- + .macro _getscom, address + + lpcs P0, \address + ld D0, \address, P0 + + .endm + + //-------------------------------------------------------------------- + // Macro Specification: + // + // Name: _putscom + // + // Description: Put Data in a SCOM address + // + // Inputs: SCOM Address, Data + // + // Outputs: None + // + // End Macro Specification + //-------------------------------------------------------------------- + .macro _putscom, address, data + + lpcs P0, \address + li D0, \data + std D0, \address, P0 + + .endm + + //-------------------------------------------------------------------- + // Macro Specification: + // + // Name: _spin_on_bitclear_scom + // + // Description: Wait for Bit to get cleared in scom register + // + // Inputs: SCOM Address, Mask + // + // Outputs: None + // + // End Macro Specification + //-------------------------------------------------------------------- + .macro _spin_on_bitclear_scom, address, mask +1: + _getscom \address + andi D0, D0, \mask + branz D0, 1b + + .endm + + //-------------------------------------------------------------------- + // PORE-GPE Routine Specification: + // + // Name: pore_test_pss + // + // Description: Delays for X (passed in) uS before halting PORE-GPE + // routine. Always sets the ffdc to indicate an error + // with a RC of 0xDEADBEEF + // + // Inputs: PoreSimpleArgs - FFDC & uS to delay. + // + // Outputs: None (except FFDC on failure) + // + // End PORE-GPE Routine Specification + //-------------------------------------------------------------------- + .global pore_test_pss +pore_test_pss: + // Copy passed Structure Pointer into A1 + mr A1, ETR + + trap + +.ifdef APSS_MODEL_INCLUDED + _spin_on_bitclear_scom SPIPSS_P2S_STATUS_REG 0x8000000000000000 + _spin_on_bitclear_scom SPIPSS_P2S_STATUS_REG 0x8000000000000000 +.endif + + trap + _getscom 0x01000000 + +.ifdef APSS_MODEL_INCLUDED + ////////////////////////////////////////////////// + // Test out a Auto-2 Mode Setup + ////////////////////////////////////////////////// + _putscom SPIPSS_P2S_CTRL_REG0, 0x410FC00004000000 + _putscom SPIPSS_P2S_CTRL_REG1, 0x001C000000000000 + _putscom SPIPSS_P2S_CTRL_REG2, 0x000C800000000000 + _putscom SPIPSS_P2S_WDATA_REG, 0x3FC0000000000000 + _putscom SPIPSS_P2S_COMMAND_REG, 0x8000000000000000 + waits 4000 + _getscom SPIPSS_P2S_RDATA_REG + trap +.endif + +.ifdef APSS_MODEL_INCLUDED + ////////////////////////////////////////////////// + // Test out a GPIO Mode Setup - all High-Z + ////////////////////////////////////////////////// + _putscom SPIPSS_P2S_CTRL_REG0, 0x410FC00004000000 + _putscom SPIPSS_P2S_CTRL_REG2, 0x000C800000000000 + _putscom SPIPSS_P2S_WDATA_REG, 0x50FF000000000000 + _putscom SPIPSS_P2S_COMMAND_REG, 0x8000000000000000 + waits 4000 + _getscom SPIPSS_P2S_RDATA_REG + trap +.endif + +.ifdef APSS_MODEL_INCLUDED + ////////////////////////////////////////////////// + // Test out ADC FSM + ////////////////////////////////////////////////// + _putscom SPIPSS_ADC_CTRL_REG0, 0x4100100000000000 + _putscom SPIPSS_ADC_CTRL_REG1, 0x801FC00000000000 + _putscom SPIPSS_ADC_CTRL_REG2, 0x0019000000000000 + _putscom SPIPSS_ADC_WDATA_REG, 0x0000000000000000 + _putscom SPIPSS_ADC_COMMAND_REG, 0x8000000000000000 + waits 30000 + _getscom SPIPSS_ADC_RDATA_REG0 + std D0, ADC0, A1 + _getscom SPIPSS_ADC_RDATA_REG1 + std D0, ADC1, A1 + _getscom SPIPSS_ADC_RDATA_REG2 + std D0, ADC2, A1 + _getscom SPIPSS_ADC_RDATA_REG3 + std D0, ADC3, A1 + _getscom TOD_VALUE_REG + std D0, TOD, A1 + trap + +.endif + +.ifdef APSS_MODEL_INCLUDED + ////////////////////////////////////////////////// + // Test out a GPIO Port 0 Read from APSS + ////////////////////////////////////////////////// + _putscom SPIPSS_P2S_CTRL_REG0, 0x410FC00004000000 + _putscom SPIPSS_P2S_CTRL_REG1, 0x001C400000000000 + _putscom SPIPSS_P2S_CTRL_REG2, 0x000C800000000000 + _putscom SPIPSS_P2S_WDATA_REG, 0x7000000000000000 + _putscom SPIPSS_P2S_COMMAND_REG, 0x8000000000000000 + waits 4000 + _getscom SPIPSS_P2S_RDATA_REG + trap +.endif + +.ifdef DPSS_MODEL_INCLUDED + ////////////////////////////////////////////////// + // Test out a Fan RPM 7 Read from DPSS + ////////////////////////////////////////////////// + _putscom SPIPSS_P2S_CTRL_REG0, 0x410FC00004000000 + _putscom SPIPSS_P2S_CTRL_REG1, 0x401C400000000000 + _putscom SPIPSS_P2S_CTRL_REG2, 0x000C800000000000 + _putscom SPIPSS_P2S_WDATA_REG, 0x3200000000000000 + _putscom SPIPSS_P2S_COMMAND_REG, 0x8000000000000000 + waits 4000 + _getscom SPIPSS_P2S_RDATA_REG + trap +.endif + +.ifdef DPSS_MODEL_INCLUDED +.print "Building in DPSS Support" + ////////////////////////////////////////////////// + // Test out a Stream of commands to the DPSS + ////////////////////////////////////////////////// + + // Send First(32) & Second(33) command + // Get Response to First command + //tgh_putscom SPIPSS_P2S_CTRL_REG0, 0x410FC04004000000 + _putscom SPIPSS_P2S_CTRL_REG0, 0x4104004004000000 + //_putscom SPIPSS_P2S_CTRL_REG1, 0x401C400000000000 + _putscom SPIPSS_P2S_CTRL_REG1, 0xC01C400000000000 + _putscom SPIPSS_P2S_CTRL_REG2, 0x000C800000000000 + _putscom SPIPSS_P2S_WDATA_REG, 0x2B002C0000000000 + _putscom SPIPSS_P2S_COMMAND_REG, 0x8000000000000000 + waits 4000 + _spin_on_bitclear_scom SPIPSS_P2S_STATUS_REG 0x8000000000000000 + _getscom SPIPSS_P2S_RDATA_REG + trap + + // Send Third (34)& Forth (35) Command + // Get Response to Second & third + _putscom SPIPSS_P2S_CTRL_REG0, 0x4100104004000000 + //_putscom SPIPSS_P2S_CTRL_REG1, 0x401C400000000000 + _putscom SPIPSS_P2S_CTRL_REG1, 0xC01C400000000000 + _putscom SPIPSS_P2S_CTRL_REG2, 0x000C800000000000 + _putscom SPIPSS_P2S_WDATA_REG, 0x2D002E0000000000 + _putscom SPIPSS_P2S_COMMAND_REG, 0x8000000000000000 + waits 4000 + _getscom SPIPSS_P2S_RDATA_REG + trap + _spin_on_bitclear_scom SPIPSS_P2S_STATUS_REG 0x8000000000000000 + + // Send Fifth (36)& Last (00) Command + // Get Response to Forth & Fifth + _putscom SPIPSS_P2S_CTRL_REG0, 0x4100104004000000 + //_putscom SPIPSS_P2S_CTRL_REG1, 0x401C400000000000 + _putscom SPIPSS_P2S_CTRL_REG1, 0xC01C400000000000 + _putscom SPIPSS_P2S_CTRL_REG2, 0x000C800000000000 + _putscom SPIPSS_P2S_WDATA_REG, 0x2F00000000000000 + _putscom SPIPSS_P2S_COMMAND_REG, 0x8000000000000000 + waits 4000 + _getscom SPIPSS_P2S_RDATA_REG + trap + _spin_on_bitclear_scom SPIPSS_P2S_STATUS_REG 0x8000000000000000 + trap + + _saveffdc3 GPE_PROG_ID GPE_ERROR_P2S_ONGOING_TIMEOUT +.endif + bra done + +error: + _saveffdc 0xDEADBEEF + +done: + + halt // End of pore_test + + ////////////////////////////////////////////////////////////////////// + // End of Program + ////////////////////////////////////////////////////////////////////// + diff --git a/src/occ/gpe/pss_constants.h b/src/occ/gpe/pss_constants.h new file mode 100755 index 0000000..79f1cbc --- /dev/null +++ b/src/occ/gpe/pss_constants.h @@ -0,0 +1,71 @@ +/****************************************************************************** +// @file pss_constants.h +// @brief Constants used by PSS communications GPE programs +*/ +/****************************************************************************** + * + * @page ChangeLogs Change Logs + * @section pss_constants.h PSS_CONSTANTS.H + * @verbatim + * + * Flag Def/Fea Userid Date Description + * ------- ---------- -------- ---------- ---------------------------------- + * @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments + * @th00e thallet 06/19/2012 SW133222: Change SPIPSS to 70000 to match HW + * @gm032 918715 milesg 03/19/2014 Improved APSS recovery + * + * @endverbatim + * + *///*************************************************************************/ + +//************************************************************************* +// Includes +//************************************************************************* + +//************************************************************************* +// Externs +//************************************************************************* + +//************************************************************************* +// Macros +//************************************************************************* + +//************************************************************************* +// Defines/Enums +//************************************************************************* +#define SPIPSS_REGISTER_BASE 0x00070000 // @th00e +#define SPIPSS_ADC_CTRL_REG0 (SPIPSS_REGISTER_BASE + 0x00) +#define SPIPSS_ADC_CTRL_REG1 (SPIPSS_REGISTER_BASE + 0x01) +#define SPIPSS_ADC_CTRL_REG2 (SPIPSS_REGISTER_BASE + 0x02) +#define SPIPSS_ADC_STATUS_REG (SPIPSS_REGISTER_BASE + 0x03) +#define SPIPSS_ADC_COMMAND_REG (SPIPSS_REGISTER_BASE + 0x04) +#define SPIPSS_ADC_RESET_REG (SPIPSS_REGISTER_BASE + 0x05) //gm032 +#define SPIPSS_ADC_WDATA_REG (SPIPSS_REGISTER_BASE + 0x10) +#define SPIPSS_ADC_RDATA_REG0 (SPIPSS_REGISTER_BASE + 0x20) +#define SPIPSS_ADC_RDATA_REG1 (SPIPSS_REGISTER_BASE + 0x21) +#define SPIPSS_ADC_RDATA_REG2 (SPIPSS_REGISTER_BASE + 0x22) +#define SPIPSS_ADC_RDATA_REG3 (SPIPSS_REGISTER_BASE + 0x23) +#define SPIPSS_100NS_REG (SPIPSS_REGISTER_BASE + 0x28) +#define SPIPSS_P2S_CTRL_REG0 (SPIPSS_REGISTER_BASE + 0x40) +#define SPIPSS_P2S_CTRL_REG1 (SPIPSS_REGISTER_BASE + 0x41) +#define SPIPSS_P2S_CTRL_REG2 (SPIPSS_REGISTER_BASE + 0x42) +#define SPIPSS_P2S_STATUS_REG (SPIPSS_REGISTER_BASE + 0x43) +#define SPIPSS_P2S_COMMAND_REG (SPIPSS_REGISTER_BASE + 0x44) +#define SPIPSS_P2S_WDATA_REG (SPIPSS_REGISTER_BASE + 0x50) +#define SPIPSS_P2S_RDATA_REG (SPIPSS_REGISTER_BASE + 0x60) + +//************************************************************************* +// Structures +//************************************************************************* + +//************************************************************************* +// Globals +//************************************************************************* + +//************************************************************************* +// Function Prototypes +//************************************************************************* + +//************************************************************************* +// Functions +//************************************************************************* diff --git a/src/occ/gpe/pss_macros.h b/src/occ/gpe/pss_macros.h new file mode 100755 index 0000000..0306d20 --- /dev/null +++ b/src/occ/gpe/pss_macros.h @@ -0,0 +1,192 @@ +/****************************************************************************** +// @file pss_macros.h +// @brief Common macros for the APSS/DPSS code +*/ +/****************************************************************************** + * + * @page ChangeLogs Change Logs + * @section pss_macros.h PSS_MACROS.H + * @verbatim + * + * Flag Def/Fea Userid Date Description + * ------- ---------- -------- ---------- ---------------------------------- + * + * @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments + * @gm032 918715 milesg 03/19/2014 Improved APSS recovery + * + * @endverbatim + * + *///*************************************************************************/ + + +//************************************************************************* +// Includes +//************************************************************************* + +//************************************************************************* +// Externs +//************************************************************************* + +//************************************************************************* +// Macros +//************************************************************************* + //-------------------------------------------------------------------- + // Name: _wait_for_spi_ops_complete (MACRO) + // + // Description: Read SPIPSS_P2S_STATUS_REG and check if p2s_ongoing + // bit is 0 (operations done). If not, wait + // up to timeout usec (~1usec per retry). + // If still not clear, branch to timeout_label + // If error/reserved bits are set, a branch will be + // done to label: "error_status_reg" + // + // Inputs: timeout - # usec to wait for ongoing bit to clear + // timeout_label - label to branch to after timeout + // + // Outputs: None (on error, D0 will contain status register) + // + // Modifies: CTR, D0, D1 + //-------------------------------------------------------------------- + .macro _wait_for_spi_ops_complete, timeout, timeout_label + + _wait_for_ops_complete SPIPSS_P2S_STATUS_REG, \timeout, \timeout_label + + .endm + + + //-------------------------------------------------------------------- + // Name: _wait_for_adc_ops_complete (MACRO) + // + // Description: Read SPIPSS_ADC_STATUS_REG and check if adc_ongoing + // bit is 0 (operations done). If not, wait + // up to timeout usec (~1usec per retry). + // If still not clear, branch to timeout_label + // If error/reserved bits are set, a branch will be + // done to label: "error_status_reg" + // + // Inputs: timeout - # usec to wait for ongoing bit to clear + // timeout_label - label to branch to after timeout + // + // Outputs: None (on error, D0 will contain status register) + // + // Modifies: CTR, D0, D1 + //-------------------------------------------------------------------- + .macro _wait_for_adc_ops_complete, timeout, timeout_label + + _wait_for_ops_complete SPIPSS_ADC_STATUS_REG, \timeout, \timeout_label + + .endm + + + //-------------------------------------------------------------------- + // Name: _wait_for_ops_complete (MACRO) + // + // Description: Read specified register and check if ongoing bit (MSB) + // is 0 (operations done). If not, wait + // up to timeout usec (~1usec per retry). + // If still not clear, branch to timeout_label + // If error/reserved bits are set, a branch will be + // done to label: "error_status_reg" + // + // Inputs: register - SCOM register to read for ongong bit + // timeout - # usec to wait for ongoing bit to clear + // timeout_label - label to branch to after timeout + // + // Outputs: None (on error, D0 will contain status register) + // + // Modifies: CTR, D0, D1 + //-------------------------------------------------------------------- + .macro _wait_for_ops_complete, register, timeout, timeout_label + + // Load CTR with approximate timeout value (1usec delay per retry) + li CTR, (\timeout - 1) +1: + // Read spiadc_p2s_ongoing bit into D0 + _getscom \register + + // Don't fail on these status bits being set. Only fail if we get back invalid power data -- gm032 + // Verify other error bits are not set + // andi D1, D0, 0x7FFFFFFFFFFFFFFF + // branz D1, error_statusreg + + // Operation finished? (spiadc_p2s_ongoing = 0) + andi D1, D0, 0x8000000000000000 + braz D1, 2f + + // no, wait 1usec and retry + waits (1 * MICROSECONDS) + loop 1b + + // Timeout waiting for spiadc_p2s_ongoing + bra \timeout_label +2: + .endm + + + + // TODO - Subroutine would be more efficient than macro, however: + // Subroutines do not currently clear the stack after a halt + // so we can NOT use subroutine (SCOM error, branch on fail, etc..) +#if 0 + //-------------------------------------------------------------------- + // Name: sub_wait_for_spi_ops_complete (SUBROUTINE) + // + // Description: Read SPIPSS_P2S_STATUS_REG and check if p2s_ongoing + // bit is 0 (operations done). If not it will wait + // for 9 additional retries (~10usec). If still not + // done, a branch will be done to timeout code. + // If error/reserved bits are set, a branch will be + // done to error_status_reg. + // + // Inputs: None + // + // Outputs: None (on error, D0 will contain status register) + // + // Modifies: CTR, D0, D1 + //-------------------------------------------------------------------- +sub_wait_for_spi_ops_complete: + // Wait up to 10usec + li CTR, 10 + +read_status: + // Read spiadc_p2s_ongoing bit into D0 + _getscom SPIPSS_P2S_STATUS_REG + + // Verify other error bits are not set + andi D1, D0, 0x7FFFFFFFFFFFFFFF + branz D1, error_statusreg + + // Ready to send command? (spiadc_p2s_ongoing = 0) + andi D1, D0, 0x8000000000000000 + braz D1, ops_are_complete + + // no, wait 1usec and retry + waits (1 * MICROSECONDS) + loop read_status + + // Timeout waiting for spiadc_p2s_ongoing + bra error_timeout +ops_are_complete: + ret +#endif +//************************************************************************* +// Defines/Enums +//************************************************************************* + +//************************************************************************* +// Structures +//************************************************************************* + +//************************************************************************* +// Globals +//************************************************************************* + +//************************************************************************* +// Function Prototypes +//************************************************************************* + +//************************************************************************* +// Functions +//************************************************************************* + + |
