diff options
| -rw-r--r-- | src/include/core_data.h | 20 | ||||
| -rw-r--r-- | src/include/p9_config.h | 4 | ||||
| -rw-r--r-- | src/include/registers/cme_register_addresses.h | 100 | ||||
| -rwxr-xr-x | src/occ_405/amec/amec_sensors_core.c | 22 | ||||
| -rwxr-xr-x | src/occ_405/amec/amec_sys.h | 2 | ||||
| -rwxr-xr-x | src/occ_405/sensor/sensor_enum.h | 31 | ||||
| -rwxr-xr-x | src/occ_405/sensor/sensor_info.c | 2 | ||||
| -rw-r--r-- | src/occ_405/sensor/sensor_main_memory.c | 13 | ||||
| -rwxr-xr-x | src/occ_405/sensor/sensor_table.c | 6 | ||||
| -rw-r--r-- | src/occ_gpe0/core_data.c | 101 | ||||
| -rw-r--r-- | src/occ_gpe0/nest_dts.c | 8 |
11 files changed, 219 insertions, 90 deletions
diff --git a/src/include/core_data.h b/src/include/core_data.h index d3b3078..1ffe5fe 100644 --- a/src/include/core_data.h +++ b/src/include/core_data.h @@ -68,6 +68,13 @@ #define EMPATH_CORE_THREADS 4 +// Droop events cache=bit37, cores = bits 42,46,50,54 +#define CACHE_VDM_LARGE_DROOP 0x0000000004000000ull +#define CORE0_VDM_SMALL_DROOP 0x0000000000200000ull +#define CORE1_VDM_SMALL_DROOP 0x0000000000020000ull +#define CORE2_VDM_SMALL_DROOP 0x0000000000002000ull +#define CORE3_VDM_SMALL_DROOP 0x0000000000000200ull + typedef struct { @@ -85,7 +92,6 @@ typedef struct typedef struct { uint32_t ifu_throttle; - //uint32_t isu_throttle; // No longer exists uint32_t ifu_active; uint32_t undefined; uint32_t v_droop; // new for p9 @@ -106,17 +112,23 @@ typedef struct sensor_result_t cache[2]; } CoreDataDts; +typedef struct +{ + uint32_t cache_large_event; + uint32_t core_small_event; +} DroopEvents; // // The instance of this data object must be 8 byte aligned // -typedef struct // 128 +typedef struct // 136 bytes { CoreDataEmpath empath; //32 CoreDataThrottle throttle; //16 CoreDataPerThread per_thread[EMPATH_CORE_THREADS]; // 64 - CoreDataDts dts; //8 - uint64_t stop_state_hist; + CoreDataDts dts; // 8 + uint64_t stop_state_hist; // 8 + DroopEvents droop; // 8 } CoreData; #ifdef __cplusplus diff --git a/src/include/p9_config.h b/src/include/p9_config.h index 72168e1..017921c 100644 --- a/src/include/p9_config.h +++ b/src/include/p9_config.h @@ -34,6 +34,10 @@ #define THERM_DTS_RESULT 0x00050000 +#define MAX_NUM_CORES 24 +#define CORES_PER_QUAD 4 +#define MAX_NUM_QUADS (MAX_NUM_CORES/CORES_PER_QUAD) + typedef union dts_sensor_result_reg { uint64_t value; diff --git a/src/include/registers/cme_register_addresses.h b/src/include/registers/cme_register_addresses.h index de64e59..6870007 100644 --- a/src/include/registers/cme_register_addresses.h +++ b/src/include/registers/cme_register_addresses.h @@ -28,7 +28,8 @@ /// \file cme_register_addresses.h /// \brief Symbolic addresses for the CME unit -// *** WARNING *** - This file is generated automatically, do not edit. +// Copied from +// ekb/chips/p9/common/pmlib/include/registers/cme_register_addresses.h #define CME_FIRPIB_BASE 0x10012000 @@ -47,21 +48,22 @@ #define CME_SCOM_CSAR 0x1001200d #define CME_SCOM_CSDR 0x1001200e #define CME_SCOM_BCECSR 0x1001200f -#define CME_SCOM_BCEBAR0 0x10012010 -#define CME_SCOM_BCEBAR1 0x10012011 -#define CME_SCOM_QFMR 0x10012012 -#define CME_SCOM_AFSR 0x10012013 -#define CME_SCOM_AFTR 0x10012014 -#define CME_SCOM_VTSR0 0x10012015 -#define CME_SCOM_VTSR1 0x10012016 -#define CME_SCOM_VDSR 0x10012017 -#define CME_SCOM_EIIR 0x10012019 -#define CME_SCOM_FWMR 0x1001201a -#define CME_SCOM_FWMR_CLR 0x1001201b -#define CME_SCOM_FWMR_OR 0x1001201c -#define CME_SCOM_SICR 0x1001201d -#define CME_SCOM_SICR_CLR 0x1001201e -#define CME_SCOM_SICR_OR 0x1001201f +#define CME_SCOM_XIXCR 0x10012010 +#define CME_SCOM_XIRAMRA 0x10012011 +#define CME_SCOM_XIRAMGA 0x10012012 +#define CME_SCOM_XIRAMDBG 0x10012013 +#define CME_SCOM_XIRAMEDR 0x10012014 +#define CME_SCOM_XIDBGPRO 0x10012015 +#define CME_SCOM_XISIB 0x10012016 +#define CME_SCOM_XIMEM 0x10012017 +#define CME_SCOM_CMEXISGB 0x10012018 +#define CME_SCOM_XIICAC 0x10012019 +#define CME_SCOM_XIPCBQ0 0x1001201a +#define CME_SCOM_XIPCBQ1 0x1001201b +#define CME_SCOM_XIPCBMD0 0x1001201c +#define CME_SCOM_XIPCBMD1 0x1001201d +#define CME_SCOM_XIPCBMI0 0x1001201e +#define CME_SCOM_XIPCBMI1 0x1001201f #define CME_SCOM_FLAGS 0x10012020 #define CME_SCOM_FLAGS_CLR 0x10012021 #define CME_SCOM_FLAGS_OR 0x10012022 @@ -73,36 +75,41 @@ #define CME_SCOM_EITR 0x10012028 #define CME_SCOM_EISTR 0x10012029 #define CME_SCOM_EINR 0x1001202a -#define CME_SCOM_SISR 0x1001202b -#define CME_SCOM_ICRR 0x1001202c -#define CME_SCOM_XIXCR 0x10012030 -#define CME_SCOM_XIRAMRA 0x10012031 -#define CME_SCOM_XIRAMGA 0x10012032 -#define CME_SCOM_XIRAMDBG 0x10012033 -#define CME_SCOM_XIRAMEDR 0x10012034 -#define CME_SCOM_XIDBGPRO 0x10012035 -#define CME_SCOM_XISIB 0x10012036 -#define CME_SCOM_XIMEM 0x10012037 -#define CME_SCOM_CMEXISGB 0x10012038 -#define CME_SCOM_XIICAC 0x10012039 -#define CME_SCOM_XIPCBQ0 0x1001203a -#define CME_SCOM_XIPCBQ1 0x1001203b -#define CME_SCOM_XIPCBMD0 0x1001203c -#define CME_SCOM_XIPCBMD1 0x1001203d -#define CME_SCOM_XIPCBMI0 0x1001203e -#define CME_SCOM_XIPCBMI1 0x1001203f +#define CME_SCOM_EIIR 0x1001202b +#define CME_SCOM_VCCR 0x1001202c +#define CME_SCOM_IDCR 0x1001202d +#define CME_SCOM_CIDSR 0x1001202e +#define CME_SCOM_QIDSR 0x1001202f +#define CME_SCOM_BCEBAR0 0x10012030 +#define CME_SCOM_BCEBAR1 0x10012031 +#define CME_SCOM_QFMR 0x10012032 +#define CME_SCOM_AFSR 0x10012033 +#define CME_SCOM_AFTR 0x10012034 +#define CME_SCOM_VDCR 0x10012035 +#define CME_SCOM_VNCR 0x10012036 +#define CME_SCOM_VDSR 0x10012037 +#define CME_SCOM_VECR 0x10012038 +#define CME_SCOM_VCTR 0x10012039 +#define CME_SCOM_LMCR 0x1001203a +#define CME_SCOM_LMCR_CLR 0x1001203b +#define CME_SCOM_LMCR_OR 0x1001203c +#define CME_SCOM_SICR 0x1001203d +#define CME_SCOM_SICR_CLR 0x1001203e +#define CME_SCOM_SICR_OR 0x1001203f #define CME_SCOM_PMSRS0 0x10012040 #define CME_SCOM_PMSRS1 0x10012041 #define CME_SCOM_PMCRS0 0x10012042 #define CME_SCOM_PMCRS1 0x10012043 #define CME_SCOM_PSCRS00 0x10012044 -#define CME_SCOM_PSCRS10 0x10012045 -#define CME_SCOM_PSCRS01 0x10012048 +#define CME_SCOM_PSCRS01 0x10012045 +#define CME_SCOM_PSCRS02 0x10012046 +#define CME_SCOM_PSCRS03 0x10012047 +#define CME_SCOM_PSCRS10 0x10012048 #define CME_SCOM_PSCRS11 0x10012049 -#define CME_SCOM_PSCRS02 0x1001204c -#define CME_SCOM_PSCRS12 0x1001204d -#define CME_SCOM_PSCRS03 0x10012050 -#define CME_SCOM_PSCRS13 0x10012051 +#define CME_SCOM_PSCRS12 0x1001204a +#define CME_SCOM_PSCRS13 0x1001204b +#define CME_SCOM_SISR 0x1001204c +#define CME_SCOM_ICRR 0x1001204d #define CME_LOCAL_BASE 0xC0000000 #define CME_LCL_EISR 0xc0000000 #define CME_LCL_EISR_OR 0xc0000010 @@ -126,7 +133,9 @@ #define CME_LCL_AFSR 0xc0000160 #define CME_LCL_AFTR 0xc0000180 #define CME_LCL_LMCR 0xc00001a0 -#define CME_LCL_BCECSR 0xc00001f0 +#define CME_LCL_LMCR_OR 0xc00001b0 +#define CME_LCL_LMCR_CLR 0xc00001b8 +#define CME_LCL_BCECSR 0xc00001e0 #define CME_LCL_PMSRS0 0xc0000200 #define CME_LCL_PMSRS1 0xc0000220 #define CME_LCL_PMCRS0 0xc0000240 @@ -154,9 +163,14 @@ #define CME_LCL_XIPCBMD1 0xc00005a0 #define CME_LCL_XIPCBMI0 0xc00005c0 #define CME_LCL_XIPCBMI1 0xc00005e0 -#define CME_LCL_VTSR0 0xc0000600 -#define CME_LCL_VTSR1 0xc0000620 +#define CME_LCL_VDCR 0xc0000600 +#define CME_LCL_VNCR 0xc0000620 #define CME_LCL_VDSR 0xc0000640 +#define CME_LCL_VECR 0xc0000660 +#define CME_LCL_VCCR 0xc0000680 +#define CME_LCL_IDCR 0xc00006a0 +#define CME_LCL_CIDSR 0xc00006c0 +#define CME_LCL_QIDSR 0xc00006e0 #define CME_LCL_ICCR 0xc0000700 #define CME_LCL_ICCR_OR 0xc0000710 #define CME_LCL_ICCR_CLR 0xc0000718 diff --git a/src/occ_405/amec/amec_sensors_core.c b/src/occ_405/amec/amec_sensors_core.c index df5fb09..da0a09b 100755 --- a/src/occ_405/amec/amec_sensors_core.c +++ b/src/occ_405/amec/amec_sensors_core.c @@ -56,6 +56,7 @@ extern data_cnfg_t * G_data_cnfg; void amec_calc_dts_sensors(CoreData * i_core_data_ptr, uint8_t i_core); void amec_calc_freq_and_util_sensors(CoreData * i_core_data_ptr, uint8_t i_core); void amec_calc_ips_sensors(CoreData * i_core_data_ptr, uint8_t i_core); +void amec_calc_droop_sensors(CoreData * i_core_data_ptr, uint8_t i_core); //*************************************************************************/ // Code @@ -115,6 +116,11 @@ void amec_update_proc_core_sensors(uint8_t i_core) amec_calc_ips_sensors(l_core_data_ptr,i_core); } + //------------------------------------------------------- + // Update voltage droop counters + //------------------------------------------------------- + amec_calc_droop_sensors(l_core_data_ptr, i_core); + // ------------------------------------------------------ // Update PREVIOUS values for next time // ------------------------------------------------------ @@ -768,6 +774,22 @@ void amec_calc_ips_sensors(CoreData * i_core_data_ptr, uint8_t i_core) sensor_update( AMECSENSOR_ARRAY_PTR(IPSC0,i_core), (uint16_t) temp32); } +// ------------------------------------------------- +// Droop count sum for core and quad +// ------------------------------------------------ +void amec_calc_droop_sensors(CoreData * i_core_data_ptr, uint8_t i_core) +{ + //CoreData only has any new droop events since the last time CoreData was read + uint32_t l_quad_droops = i_core_data_ptr->droop.cache_large_event; + uint32_t l_core_droops = i_core_data_ptr->droop.core_small_event; + int l_quad = i_core / 4; + sensor_t * l_quad_sensor = AMECSENSOR_ARRAY_PTR(VOLTDROOPCNTQ0, l_quad); + sensor_t * l_core_sensor = AMECSENSOR_ARRAY_PTR(VOLTDROOPCNTC0, i_core); + + sensor_update( l_core_sensor, l_core_droops); + sensor_update( l_quad_sensor, l_quad_droops); +} + /*----------------------------------------------------------------------------*/ /* End */ /*----------------------------------------------------------------------------*/ diff --git a/src/occ_405/amec/amec_sys.h b/src/occ_405/amec/amec_sys.h index c084a0c..803ca28 100755 --- a/src/occ_405/amec/amec_sys.h +++ b/src/occ_405/amec/amec_sys.h @@ -295,6 +295,7 @@ typedef struct sensor_t tempc; sensor_t stopdeepreqc; sensor_t stopdeepactc; + sensor_t voltdroopcntc; //----------------------------------- // Previous Tick Data @@ -427,6 +428,7 @@ typedef struct typedef struct { sensor_t tempq; + sensor_t voltdroopcntq; } amec_quad_t; //------------------------------------------------------------- diff --git a/src/occ_405/sensor/sensor_enum.h b/src/occ_405/sensor/sensor_enum.h index 62745d3..f3fe743 100755 --- a/src/occ_405/sensor/sensor_enum.h +++ b/src/occ_405/sensor/sensor_enum.h @@ -130,6 +130,12 @@ enum e_gsid TEMPQ3, TEMPQ4, TEMPQ5, + VOLTDROOPCNTQ0, + VOLTDROOPCNTQ1, + VOLTDROOPCNTQ2, + VOLTDROOPCNTQ3, + VOLTDROOPCNTQ4, + VOLTDROOPCNTQ5, // ------------------------------------------------------ // Regulator Sensors @@ -444,6 +450,31 @@ enum e_gsid STOPDEEPACTC22, STOPDEEPACTC23, + VOLTDROOPCNTC0, + VOLTDROOPCNTC1, + VOLTDROOPCNTC2, + VOLTDROOPCNTC3, + VOLTDROOPCNTC4, + VOLTDROOPCNTC5, + VOLTDROOPCNTC6, + VOLTDROOPCNTC7, + VOLTDROOPCNTC8, + VOLTDROOPCNTC9, + VOLTDROOPCNTC10, + VOLTDROOPCNTC11, + VOLTDROOPCNTC12, + VOLTDROOPCNTC13, + VOLTDROOPCNTC14, + VOLTDROOPCNTC15, + VOLTDROOPCNTC16, + VOLTDROOPCNTC17, + VOLTDROOPCNTC18, + VOLTDROOPCNTC19, + VOLTDROOPCNTC20, + VOLTDROOPCNTC21, + VOLTDROOPCNTC22, + VOLTDROOPCNTC23, + // ------------------------------------------------------ // Memory Sensors // ------------------------------------------------------ diff --git a/src/occ_405/sensor/sensor_info.c b/src/occ_405/sensor/sensor_info.c index 0592908..8602f5c 100755 --- a/src/occ_405/sensor/sensor_info.c +++ b/src/occ_405/sensor/sensor_info.c @@ -328,6 +328,7 @@ const sensor_info_t G_sensor_info[] = SENSOR_INFO_T_ENTRY( PROCOTTHROT, "#\0", AMEC_SENSOR_TYPE_PERF, AMEC_SENSOR_LOC_PROC, AMEC_SENSOR_NONUM, AMEEFP_EVERY_64TH_TICK_HZ, AMEFP( 1, 0) ), SENS_QUAD_ENTRY_SET( TEMPQ, "C\0", AMEC_SENSOR_TYPE_TEMP, AMEC_SENSOR_LOC_PROC, AMEC_SENSOR_NONUM, AMEEFP_EVERY_16TH_TICK_HZ, AMEFP( 1, 0) ), + SENS_QUAD_ENTRY_SET( VOLTDROOPCNTQ, "#\0", AMEC_SENSOR_TYPE_VOLTAGE, AMEC_SENSOR_LOC_PROC, AMEC_SENSOR_NONUM, AMEEFP_EVERY_16TH_TICK_HZ, AMEFP( 1, 0) ), /* ==ReguSensors== NameString Units Type Location Number Freq ScaleFactor */ SENSOR_INFO_T_ENTRY( VOLTVDD, "mV\0", AMEC_SENSOR_TYPE_VOLTAGE, AMEC_SENSOR_LOC_VRM, AMEC_SENSOR_NONUM, AMEEFP_EVERY_2ND_TICK_HZ, AMEFP( 1, -1) ), @@ -349,6 +350,7 @@ const sensor_info_t G_sensor_info[] = SENS_CORE_ENTRY_SET( TEMPC, "C\0", AMEC_SENSOR_TYPE_TEMP, AMEC_SENSOR_LOC_CORE, AMEC_SENSOR_NONUM, AMEEFP_EVERY_16TH_TICK_HZ, AMEFP( 1, 0) ), SENS_CORE_ENTRY_SET( STOPDEEPREQC, "ss\0", AMEC_SENSOR_TYPE_PERF, AMEC_SENSOR_LOC_CORE, AMEC_SENSOR_NONUM, AMEEFP_EVERY_16TH_TICK_HZ, AMEFP( 1, 0) ), SENS_CORE_ENTRY_SET( STOPDEEPACTC, "ss\0", AMEC_SENSOR_TYPE_PERF, AMEC_SENSOR_LOC_CORE, AMEC_SENSOR_NONUM, AMEEFP_EVERY_16TH_TICK_HZ, AMEFP( 1, 0) ), + SENS_CORE_ENTRY_SET( VOLTDROOPCNTC, "#\0",AMEC_SENSOR_TYPE_VOLTAGE, AMEC_SENSOR_LOC_CORE, AMEC_SENSOR_NONUM, AMEEFP_EVERY_16TH_TICK_HZ, AMEFP( 1, 0) ), /* ==MemSensors== NameString Units Type Location Number Freq ScaleFactor */ SENS_MEMC_ENTRY_SET( MRDM, "GBs\0", AMEC_SENSOR_TYPE_PERF, AMEC_SENSOR_LOC_MEM, AMEC_SENSOR_NONUM, AMEEFP_EVERY_8TH_TICK_HZ, AMEFP( 128, -5) ), diff --git a/src/occ_405/sensor/sensor_main_memory.c b/src/occ_405/sensor/sensor_main_memory.c index 70fb8a5..2cc4952 100644 --- a/src/occ_405/sensor/sensor_main_memory.c +++ b/src/occ_405/sensor/sensor_main_memory.c @@ -102,6 +102,17 @@ typedef struct __attribute__ ((packed)) MAIN_MEM_SENSOR(gsid_prefix##23 , smf_mode, master_only) /** + * Macro to build main_mem_sensor_t instance for all quads + */ +#define MAIN_MEM_QUAD_SENSORS(gsid_prefix, smf_mode, master_only) \ + MAIN_MEM_SENSOR(gsid_prefix##0 , smf_mode, master_only) , \ + MAIN_MEM_SENSOR(gsid_prefix##1 , smf_mode, master_only) , \ + MAIN_MEM_SENSOR(gsid_prefix##2 , smf_mode, master_only) , \ + MAIN_MEM_SENSOR(gsid_prefix##3 , smf_mode, master_only) , \ + MAIN_MEM_SENSOR(gsid_prefix##4 , smf_mode, master_only) , \ + MAIN_MEM_SENSOR(gsid_prefix##5 , smf_mode, master_only) + +/** * Macro to build main_mem_sensor_t instances for all memory DIMMs. */ #define MAIN_MEM_DIMM_SENSORS(gsid_prefix, smf_mode, master_only) \ @@ -168,6 +179,8 @@ main_mem_sensor_t G_main_mem_sensors[] = MAIN_MEM_SENSOR (VOLTVDDSENSE, true, false), MAIN_MEM_SENSOR (VOLTVDN, true, false), MAIN_MEM_SENSOR (VOLTVDNSENSE, true, false), + MAIN_MEM_CORE_SENSORS (VOLTDROOPCNTC, true, false), + MAIN_MEM_QUAD_SENSORS (VOLTDROOPCNTQ, true, false), // AMEC_SENSOR_TYPE_TEMP: gsid smf_mode master_only MAIN_MEM_SENSOR (TEMPNEST, false, false), diff --git a/src/occ_405/sensor/sensor_table.c b/src/occ_405/sensor/sensor_table.c index b4128a3..c2dabdb 100755 --- a/src/occ_405/sensor/sensor_table.c +++ b/src/occ_405/sensor/sensor_table.c @@ -366,7 +366,8 @@ const sensor_ptr_t G_amec_sensor_list[] = // ------------------------------------------------------ // Quad Sensors (6 each) // ------------------------------------------------------ - QUAD_SENSOR_PTRS( TEMPQ, &g_amec_sys.proc[0].quad, tempq), + QUAD_SENSOR_PTRS( TEMPQ, &g_amec_sys.proc[0].quad, tempq), + QUAD_SENSOR_PTRS( VOLTDROOPCNTQ, &g_amec_sys.proc[0].quad, voltdroopcntq), // ------------------------------------------------------ // Regulator Sensors @@ -393,6 +394,7 @@ const sensor_ptr_t G_amec_sensor_list[] = CORE_SENSOR_PTRS( TEMPC, &g_amec_sys.proc[0].core, tempc), CORE_SENSOR_PTRS( STOPDEEPREQC, &g_amec_sys.proc[0].core, stopdeepreqc), CORE_SENSOR_PTRS( STOPDEEPACTC, &g_amec_sys.proc[0].core, stopdeepactc), + CORE_SENSOR_PTRS( VOLTDROOPCNTC, &g_amec_sys.proc[0].core, voltdroopcntc), // ------------------------------------------------------ // Memory Sensors @@ -546,6 +548,7 @@ const minisensor_ptr_t G_amec_mini_sensor_list[] INIT_SECTION = // Quad Sensors (6 each) // ------------------------------------------------------ QUAD_MINI_SENSOR_PTRS_NULL( TEMPQ ), + QUAD_MINI_SENSOR_PTRS_NULL( VOLTDROOPCNTQ), // ------------------------------------------------------ // Regulator Sensors @@ -571,6 +574,7 @@ const minisensor_ptr_t G_amec_mini_sensor_list[] INIT_SECTION = CORE_MINI_SENSOR_PTRS_NULL( TEMPC ), CORE_MINI_SENSOR_PTRS_NULL( STOPDEEPREQC ), CORE_MINI_SENSOR_PTRS_NULL( STOPDEEPACTC ), + CORE_MINI_SENSOR_PTRS_NULL( VOLTDROOPCNTC), // ------------------------------------------------------ // Memory Sensors diff --git a/src/occ_gpe0/core_data.c b/src/occ_gpe0/core_data.c index 7dcb613..d4346f3 100644 --- a/src/occ_gpe0/core_data.c +++ b/src/occ_gpe0/core_data.c @@ -31,19 +31,25 @@ #include "p9_config.h" #include "ppe42_msr.h" #include "ppe42_scom.h" +#include "cme_register_addresses.h" + +#define CME_VDSR_BASE (CME_SCOM_VDSR & 0x00ffffff) + +// Global variables +uint32_t g_vdm_cache_large_droop_count[MAX_NUM_QUADS]__attribute__((section (".sbss"))); +uint32_t g_vdm_core_small_droop_count[MAX_NUM_CORES]__attribute__((section (".sbss"))); uint32_t get_core_data(uint32_t i_core, CoreData* o_data) { uint32_t rc = 0; - uint32_t size = sizeof(CoreData) / 8; + uint32_t size = sizeof(CoreData) / sizeof(uint64_t); uint64_t* ptr = (uint64_t*)o_data; uint32_t coreSelect = CHIPLET_CORE_ID(i_core); - uint32_t quadSelect = CHIPLET_CACHE_ID((i_core / 4)); - //volatile uint64_t* scom_reg = (uint64_t*)(0); + uint32_t quadSelect = CHIPLET_CACHE_ID((i_core / CORES_PER_QUAD)); uint64_t value64 = 0; - uint32_t i; + uint32_t i,idx; for(i = 0; i < size; ++i) { @@ -51,28 +57,22 @@ uint32_t get_core_data(uint32_t i_core, } // Turn off MCR bit to prevent machine check on error on scom readings bits 1:7 - // rc == 1 resource occupied (see ppe42_scom.h) Action: return with rc - // rc == 2 Core is fenced, offline Action: return with rc + // rc == 1 resource occupied (see ppe42_scom.h) + // rc == 2 Core is fenced, offline // rc == 3 partial good // rc == 4 address error (Can be caused by other device using bus) // rc == 5 clock error // rc == 6 packet error // rc == 7 timeout - // ACTIONS: - // rc 1,2:- mask the machine check, return rc - // 3-7 Leave as machine check (or as it was) uint32_t org_sem = mfmsr() & MSR_SEM; // Clear SIBRC and SIBRCA - // mask off resource occupied/offline errors - will return these) - // SIB rc 3-7 will machine check (unless already masked) - mtmsr((mfmsr() & ~(MSR_SIBRC | MSR_SIBRCA)) - | 0xe8000000); //MASK SIBRC == 1 | SIBRC == 2 | SIBRC == 4 + // mask off SIB errors as machine checks, return rc instead + mtmsr((mfmsr() & ~(MSR_SIBRC | MSR_SIBRCA)) | MSR_SEM); + // DTS dts_sensor_result_reg_t dts_scom_data; - //scom_reg = (uint64_t*)(quadSelect + THERM_DTS_RESULT); - //dts_scom_data.value = *scom_reg; PPE_LVD(quadSelect + THERM_DTS_RESULT, value64); dts_scom_data.value = value64; @@ -80,57 +80,93 @@ uint32_t get_core_data(uint32_t i_core, o_data->dts.cache[0].result = dts_scom_data.half_words.reading[0]; o_data->dts.cache[1].result = dts_scom_data.half_words.reading[1]; - //scom_reg = (uint64_t*)(coreSelect + THERM_DTS_RESULT); - //dts_scom_data.value = *scom_reg; PPE_LVD(coreSelect + THERM_DTS_RESULT, value64); dts_scom_data.value = value64; o_data->dts.core[0].result = dts_scom_data.half_words.reading[0]; o_data->dts.core[1].result = dts_scom_data.half_words.reading[1]; + // DROOP + // Read Droop events. Event bit == 0 indicates event occurred. + // Side effect of read: event bits are reset to 1 (no event) in hw + // Only quad large droop and core small drop events are of interest + PPE_LVD(quadSelect + CME_VDSR_BASE, value64); + + if((value64 & CACHE_VDM_LARGE_DROOP) == 0) + { + ++g_vdm_cache_large_droop_count[i_core / CORES_PER_QUAD]; + } + + idx = (i_core / CORES_PER_QUAD) * CORES_PER_QUAD; + + if((value64 & CORE0_VDM_SMALL_DROOP) == 0) + { + ++g_vdm_core_small_droop_count[idx]; + } + + if((value64 & CORE1_VDM_SMALL_DROOP) == 0) + { + ++g_vdm_core_small_droop_count[idx+1]; + } + + if((value64 & CORE2_VDM_SMALL_DROOP) == 0) + { + ++g_vdm_core_small_droop_count[idx+2]; + } + + if((value64 & CORE3_VDM_SMALL_DROOP) == 0) + { + ++g_vdm_core_small_droop_count[idx+3]; + } + + // return the event status for the requested core and + // corresponding quad. + // Clear the counter for only the droop events returned. + if(g_vdm_cache_large_droop_count[i_core / CORES_PER_QUAD] != 0) + { + o_data->droop.cache_large_event = 1; + g_vdm_cache_large_droop_count[i_core / CORES_PER_QUAD] = 0; + } + + if(g_vdm_core_small_droop_count[i_core] != 0) + { + o_data->droop.core_small_event = 1; + g_vdm_core_small_droop_count[i_core] = 0; + } + + // EMPATH // Send command to select which emmpath counter to read uint64_t empath_scom_data = CORE_RAW_CYCLES; - //scom_reg = (uint64_t*)(coreSelect + PC_OCC_SPRC); - //*scom_reg = empath_scom_data; PPE_STVD(coreSelect + PC_OCC_SPRC, empath_scom_data) - // Read counters. // Counter selected auto increments to the next counter after each read. //CORE_RAW_CYCLES - //scom_reg = (uint64_t*)(coreSelect + PC_OCC_SPRD); - //empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->empath.raw_cycles = (uint32_t)empath_scom_data; //CORE_RUN_CYCLES - //empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->empath.run_cycles = (uint32_t)empath_scom_data; //CORE_WORKRATE_BUSY - //empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->empath.freq_sens_busy = (uint32_t)empath_scom_data; //CORE_WORKRATE_FINISH - //empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->empath.freq_sens_finish = (uint32_t)empath_scom_data; //CORE_MEM_HIER_A_LATENCY - // empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->empath.mem_latency_a = (uint32_t)empath_scom_data; //CORE_MEM_HIER_B_LATENCY - // empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->empath.mem_latency_b = (uint32_t)empath_scom_data; //CORE_MEM_HIER_C_ACCESS - //empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->empath.mem_access_c = (uint32_t)empath_scom_data; @@ -139,45 +175,36 @@ uint32_t get_core_data(uint32_t i_core, for( ; thread < EMPATH_CORE_THREADS; ++thread ) { // THREAD_RUN_CYCLES - //empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->per_thread[thread].run_cycles = (uint32_t)empath_scom_data; // THREAD_INST_DISP_UTIL - //empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->per_thread[thread].dispatch = (uint32_t)empath_scom_data; // THREAD_INST_COMP_UTIL - //empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->per_thread[thread].completion = (uint32_t)empath_scom_data; // THREAD_MEM_HEIR_C_ACCESS - //empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->per_thread[thread].mem_c = (uint32_t)empath_scom_data; } //IFU_THROTTLE_BLOCK_FETCH - //empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->throttle.ifu_throttle = (uint32_t)empath_scom_data; //IFU_THROTTLE_ACTIVE - //empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->throttle.ifu_active = (uint32_t)empath_scom_data; //VOLT_DROOP_THROTTLE_ACTIVE - //empath_scom_data = *scom_reg; PPE_LVD(coreSelect + PC_OCC_SPRD, empath_scom_data); o_data->throttle.v_droop = (uint32_t)empath_scom_data; // TOD value - //scom_reg = (uint64_t*)TOD_VALUE_REG; PPE_LVD(TOD_VALUE_REG, empath_scom_data); - //empath_scom_data = *scom_reg; o_data->empath.tod_2mhz = (uint32_t)(empath_scom_data >> 8); //[24..56] // STOP_STATE_HIST_OCC_REG diff --git a/src/occ_gpe0/nest_dts.c b/src/occ_gpe0/nest_dts.c index cdb615c..74ece94 100644 --- a/src/occ_gpe0/nest_dts.c +++ b/src/occ_gpe0/nest_dts.c @@ -22,6 +22,7 @@ /* permissions and limitations under the License. */ /* */ /* IBM_PROLOG_END_TAG */ + #include <nest_dts.h> #include <ppe42_msr.h> #include <ppe42_scom.h> @@ -49,10 +50,8 @@ uint32_t get_nest_dts(NestDts_t* o_data) uint32_t org_sem = mfmsr() & MSR_SEM; // Clear SIBRC and SIBRCA - // mask off resource occupied/offline errors - will return these) - // SIB rc 3-7 will machine check (unless already masked) - mtmsr((mfmsr() & ~(MSR_SIBRC | MSR_SIBRCA)) - | 0xe0000000); //MASK SIBRC == 1 | SIBRC == 2 + // mask off SIB errors as machine checks, return rc instead + mtmsr((mfmsr() & ~(MSR_SIBRC | MSR_SIBRCA)) | MSR_SEM); // Get DTS readings PPE_LVD(nest1Select + THERM_DTS_RESULT, value64); @@ -93,4 +92,3 @@ uint32_t get_nest_dts(NestDts_t* o_data) return rc; } - |
