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authorChris Cain <cjcain@us.ibm.com>2019-01-18 08:56:17 -0600
committerChristopher J. Cain <cjcain@us.ibm.com>2019-01-29 13:50:07 -0600
commitd03cb7413705fe805cb41d5bc259d825fc814e3d (patch)
tree5aab47859d0d5fa4b19947c30f253723353f116e /src
parent58e422dede5932f5b8e01a88315001b0525cc478 (diff)
downloadtalos-occ-d03cb7413705fe805cb41d5bc259d825fc814e3d.tar.gz
talos-occ-d03cb7413705fe805cb41d5bc259d825fc814e3d.zip
Update to PGPE elog structure
Change-Id: I2a9a45d239842603fda5ab097813bdc7c8c3f3bf Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/70632 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Diffstat (limited to 'src')
-rw-r--r--src/include/pstate_pgpe_occ_api.h4
-rwxr-xr-xsrc/occ_405/errl/errl.h4
2 files changed, 4 insertions, 4 deletions
diff --git a/src/include/pstate_pgpe_occ_api.h b/src/include/pstate_pgpe_occ_api.h
index 28cd47d..0593b62 100644
--- a/src/include/pstate_pgpe_occ_api.h
+++ b/src/include/pstate_pgpe_occ_api.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2016,2018 */
+/* Contributors Listed Below - COPYRIGHT 2016,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -259,7 +259,7 @@ typedef union requested_active_quads
// -----------------------------------------------------------------------------
// Start Error Log Table
-#define MAX_HCODE_ELOG_ENTRIES 16
+#define MAX_HCODE_ELOG_ENTRIES 28
typedef union hcode_elog_entry
{
diff --git a/src/occ_405/errl/errl.h b/src/occ_405/errl/errl.h
index e249ef0..57da76f 100755
--- a/src/occ_405/errl/errl.h
+++ b/src/occ_405/errl/errl.h
@@ -5,7 +5,7 @@
/* */
/* OpenPOWER OnChipController Project */
/* */
-/* Contributors Listed Below - COPYRIGHT 2011,2018 */
+/* Contributors Listed Below - COPYRIGHT 2011,2019 */
/* [+] International Business Machines Corp. */
/* */
/* */
@@ -286,7 +286,7 @@ extern uint8_t G_occErrIdCounter;
extern errlHndl_t G_occErrSlots[ERRL_MAX_SLOTS];
// Shared SRAM offset to access the HCODE Error Log Table
-#define HCODE_ELOG_TABLE_SRAM_OFFSET 0x40
+#define HCODE_ELOG_TABLE_SRAM_OFFSET 0x48
#define HCODE_ELOG_TABLE_MAGIC_NUMBER 0x454C5443 // "ELTC"
extern hcode_elog_entry_t *G_hcode_elog_table;
extern uint32_t G_hcode_elog_table_slots;
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