Initial support to handle no APSS

Change-Id: Ia14aebaf44e9a0a3d2e14a4ff3803793350986b4
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/40521
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>

6 files changed, 57 insertions, 21 deletions

diff --git a/src/occ_405/amec/amec_pcap.c b/src/occ_405/amec/amec_pcap.c
index 24557d4..b5cad52 100755
--- a/src/occ_405/amec/amec_pcap.c
+++ b/src/occ_405/amec/amec_pcap.c
@@ -50,6 +50,7 @@
 //*************************************************************************/
 // Globals
 //*************************************************************************/
+extern bool G_apss_present;
 
 //Number of ticks to wait before dropping below nominal frequency
 #define PWR_SETTLED_TICKS   4
@@ -373,18 +374,28 @@ void amec_power_control(void)
     /*  Code                                                                  */
     /*------------------------------------------------------------------------*/
 
-    // Calculate the pcap for the proc, memory and the power capping limit
-    // for nominal cores.
-    amec_pcap_calc();
-
-    // skip processor changes until memory is un-capped
-    if(!g_amec->pcap.active_mem_level)
+    if(G_apss_present)
     {
-       // Calculate voting box input freq for staying with the current pcap
-       amec_pcap_controller();
-
-       // Calculate the performance preserving bounds voting box input freq
-       amec_ppb_fmax_calc();
+       // Calculate the pcap for the proc, memory and the power capping limit
+       // for nominal cores.
+       amec_pcap_calc();
+
+       // skip processor changes until memory is un-capped
+       if(!g_amec->pcap.active_mem_level)
+       {
+          // Calculate voting box input freq for staying with the current pcap
+          amec_pcap_controller();
+
+          // Calculate the performance preserving bounds voting box input freq
+          amec_ppb_fmax_calc();
+       }
+    }
+    else
+    {
+        // No system power reading for power capping set pcap frequency votes to max
+        g_amec->proc[0].pwr_votes.proc_pcap_nom_vote = G_proc_fmax_mhz;
+        g_amec->proc[0].pwr_votes.proc_pcap_vote = G_proc_fmax_mhz;
+        g_amec->proc[0].pwr_votes.ppb_fmax = G_proc_fmax_mhz;
     }
 }
 
diff --git a/src/occ_405/amec/amec_sensors_power.c b/src/occ_405/amec/amec_sensors_power.c
index 543a917..b8704ae 100755
--- a/src/occ_405/amec/amec_sensors_power.c
+++ b/src/occ_405/amec/amec_sensors_power.c
@@ -61,6 +61,7 @@ uint32_t G_lastValidAdcValue[MAX_APSS_ADC_CHANNELS] = {0};
 
 extern uint8_t G_occ_interrupt_type;
 extern bool    G_vrm_thermal_monitoring;
+extern bool    G_apss_present;
 
 //*************************************************************************
 // Code
@@ -183,7 +184,7 @@ void amec_update_apss_sensors(void)
 {
     // Need to check to make sure APSS data has been received
     // via slave inbox first
-    if (G_slv_inbox_received)
+    if (G_slv_inbox_received && G_apss_present)
     {
         uint8_t l_proc   = G_pbax_id.chip_id;
         uint32_t temp32  = 0;
@@ -475,6 +476,7 @@ void update_avsbus_power_sensors(const avsbus_type_e i_type)
     uint32_t l_voltageSensor = VOLTVDD;
     uint32_t l_voltageChip = VOLTVDDSENSE;
     uint32_t l_powerSensor = PWRVDD;
+    uint32_t l_powerSensor2 = PWRVDN;
     if (AVSBUS_VDN == i_type)
     {
         L_throttle = &L_throttle_vdn;
@@ -484,6 +486,7 @@ void update_avsbus_power_sensors(const avsbus_type_e i_type)
         l_voltageSensor = VOLTVDN;
         l_voltageChip = VOLTVDNSENSE;
         l_powerSensor = PWRVDN;
+        l_powerSensor2 = PWRVDD;
     }
 
     // Read latest voltage/current sensors
@@ -552,6 +555,14 @@ void update_avsbus_power_sensors(const avsbus_type_e i_type)
             //                    = v(100uV) * i(10mA) / 1,000,000
             const uint32_t l_power = l_chip_voltage_100uv * l_current_10ma / 1000000;
             sensor_update(AMECSENSOR_PTR(l_powerSensor), (uint16_t)l_power);
+            if(!G_apss_present)
+            {
+               // no APSS, update the processor power sensor with total processor power
+               // TODO RTC 160889 add in processor power for parts not measured (i.e. Vddr, Vcs, Vio etc)
+               sensor_t *l_sensor2 = getSensorByGsid(l_powerSensor2);
+               const uint16_t l_proc_power = (uint16_t)l_power + l_sensor2->sample;
+               sensor_update(AMECSENSOR_PTR(PWRPROC), l_proc_power);
+            }
         }
 
 #ifdef AVSDEBUG
diff --git a/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c b/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
index 7d24785..91a27cb 100755
--- a/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
+++ b/src/occ_405/cmdh/cmdh_fsp_cmds_datacnfg.c
@@ -104,6 +104,9 @@ bool G_mem_monitoring_allowed = FALSE;
 // Flag will get enabled when OCC receives Thermal Threshold data
 bool G_vrm_thermal_monitoring = FALSE;
 
+// Will get set to true when receiving APSS config data 
+bool G_apss_present = FALSE;
+
 // Function Specification
 //
 // Name:  DATA_get_present_cnfgdata
@@ -924,12 +927,12 @@ errlHndl_t data_store_apss_config_v20(const cmdh_apss_config_v20_t * i_cmd_ptr,
                                             cmdh_fsp_rsp_t * o_rsp_ptr)
 {
     errlHndl_t              l_err = NULL;
-
     uint16_t l_channel = 0, l_port = 0, l_pin = 0;
 
     // Set to default value
     memset(&G_sysConfigData.apss_adc_map, SYSCFG_INVALID_ADC_CHAN, sizeof(G_sysConfigData.apss_adc_map));
     memset(&G_sysConfigData.apss_gpio_map, SYSCFG_INVALID_PIN, sizeof(G_sysConfigData.apss_gpio_map));
+    G_apss_present = FALSE;
 
     // ADC channels info
     for(l_channel=0;(l_channel < MAX_APSS_ADC_CHANNELS) && (NULL == l_err);l_channel++)
@@ -944,6 +947,10 @@ errlHndl_t data_store_apss_config_v20(const cmdh_apss_config_v20_t * i_cmd_ptr,
         {
             //Write sensor IDs to the appropriate powr sensors.
             apss_store_ipmi_sensor_id(l_channel, &(i_cmd_ptr->adc[l_channel]));
+
+            // APSS is present if there is at least one channel with a valid assignment
+            if(i_cmd_ptr->adc[l_channel].assignment != ADC_RESERVED)
+              G_apss_present = TRUE;
         }
         CNFG_DBG("data_store_apss_config_v20: Channel %d: FuncID[0x%02X] SID[0x%08X]",
                  l_channel, i_cmd_ptr->adc[l_channel].assignment, i_cmd_ptr->adc[l_channel].ipmisensorId);
@@ -975,7 +982,7 @@ errlHndl_t data_store_apss_config_v20(const cmdh_apss_config_v20_t * i_cmd_ptr,
         {
             // Change Data Request Mask to indicate we got this data
             G_data_cnfg->data_mask |= DATA_MASK_APSS_CONFIG;
-            CMDH_TRAC_IMP("Got valid APSS Config data via TMGT");
+            CMDH_TRAC_IMP("Got valid APSS Config data via TMGT; APSS present = %d", G_apss_present);
         }
     }
 
@@ -1190,8 +1197,9 @@ errlHndl_t data_store_role(const cmdh_fsp_cmd_t * i_cmd_ptr,
             rtl_clr_run_mask_deferred(RTL_FLAG_NOTMSTR);
             rtl_set_run_mask_deferred(RTL_FLAG_MSTR);
 
-            // Allow APSS tasks to run on OCC master
-            rtl_clr_run_mask_deferred(RTL_FLAG_APSS_NOT_INITD);
+            // Allow APSS tasks to run on OCC master if APSS is present
+            if(G_apss_present)
+               rtl_clr_run_mask_deferred(RTL_FLAG_APSS_NOT_INITD);
 
             CMDH_TRAC_IMP("data_store_role: OCC Role set to Master via TMGT");
 
@@ -1230,7 +1238,8 @@ errlHndl_t data_store_role(const cmdh_fsp_cmd_t * i_cmd_ptr,
                 }
 
                 // Allow APSS tasks to run on OCC backup
-                rtl_clr_run_mask_deferred(RTL_FLAG_APSS_NOT_INITD);
+                if(G_apss_present)
+                   rtl_clr_run_mask_deferred(RTL_FLAG_APSS_NOT_INITD);
                 CMDH_TRAC_IMP("data_store_role: OCC Role set to Backup Master via TMGT");
             }
             else
diff --git a/src/occ_405/dcom/dcomMasterTx.c b/src/occ_405/dcom/dcomMasterTx.c
index 44205a5..3285442 100644
--- a/src/occ_405/dcom/dcomMasterTx.c
+++ b/src/occ_405/dcom/dcomMasterTx.c
@@ -39,6 +39,7 @@
 #include <amec_master_smh.h>
 
 extern UINT8 g_amec_tb_record; // From amec_amester.c for syncronized traces
+extern bool G_apss_present;
 
 // SSX Block Copy Request for the Slave Inbox Transmit Queue
 BceRequest G_slv_inbox_tx_pba_request;
@@ -238,9 +239,9 @@ void task_dcom_tx_slv_inbox( task_t *i_self)
 
     do
     {
-        // If we are in standby, we need to fake out
+        // If we are in standby or no APSS present, we need to fake out
         // the APSS data since we aren't talking to APSS.
-        if( OCC_STATE_STANDBY == CURRENT_STATE() )
+        if( (OCC_STATE_STANDBY == CURRENT_STATE()) || !G_apss_present )
         {
            G_ApssPwrMeasCompleted = TRUE;
         }
diff --git a/src/occ_405/main.c b/src/occ_405/main.c
index c51af73..808d61d 100755
--- a/src/occ_405/main.c
+++ b/src/occ_405/main.c
@@ -86,6 +86,8 @@ extern uint32_t G_khz_per_pstate;
 extern uint8_t G_proc_pmin;
 extern uint8_t G_proc_pmax;
 
+extern bool    G_apss_present;
+
 IMAGE_HEADER (G_mainAppImageHdr,__ssx_boot,MAIN_APP_ID,ID_NUM_INVALID);
 
 ppmr_header_t G_ppmr_header;       // PPMR Header layout format
@@ -1377,7 +1379,9 @@ void master_occ_init()
 
     errlHndl_t l_err = NULL;
 
-    l_err = initialize_apss();
+    // Only do APSS initialization if APSS is present
+    if(G_apss_present)
+       l_err = initialize_apss();
 
     if( (NULL != l_err))
     {
diff --git a/src/occ_405/occbuildname.c b/src/occ_405/occbuildname.c
index b41a88f..9e8c0d1 100755
--- a/src/occ_405/occbuildname.c
+++ b/src/occ_405/occbuildname.c
@@ -34,6 +34,6 @@ volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) =
 
 #else
 
-volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/  "op_occ_170510a\0"  /*</BuildName>*/ ;
+volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/  "op_occ_170515a\0"  /*</BuildName>*/ ;
 
 #endif