Support for MMU-less systems

Change-Id: I33c0b56ce599f512fa686275ba483092897cc5af
RTC:165351
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33743
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>

4 files changed, 92 insertions, 13 deletions

diff --git a/src/occ_405/cmdh/cmdh_fsp.c b/src/occ_405/cmdh/cmdh_fsp.c
index 6896165..aa5b00d 100755
--- a/src/occ_405/cmdh/cmdh_fsp.c
+++ b/src/occ_405/cmdh/cmdh_fsp.c
@@ -69,10 +69,21 @@ LINEAR_WINDOW_RD_BUFFER(fsp_rsp_t G_fsp_rsp);
 
 // This holds the pointers to the command & response buffers, and to the
 // doorbell placeholder data.
+
+// Since the entirety of our SRAM is marked as cacheable, we need to use
+// the non-cacheable address alias of our command and response buffers when
+// not using the MMU.
+#if PPC405_MMU_SUPPORT
 fsp_msg_t G_fsp_msg = {
     .cmd = (fsp_cmd_t *) CMDH_LINEAR_WINDOW_BASE_ADDRESS,
     .rsp = (fsp_rsp_t *) CMDH_OCC_RESPONSE_BASE_ADDRESS,
 };
+#else
+fsp_msg_t G_fsp_msg = {
+    .cmd = (fsp_cmd_t *) (CMDH_LINEAR_WINDOW_BASE_ADDRESS - 0x08000000),
+    .rsp = (fsp_rsp_t *) (CMDH_OCC_RESPONSE_BASE_ADDRESS  - 0x10000000),
+};
+#endif
 
 // Temporary storage used by our SSX_PANIC macro
 uint32_t __occ_panic_save_r3;
@@ -780,6 +791,34 @@ errlHndl_t cmdh_fsp_cmd_hndler(void)
 
             // Verify Command Checksum
             l_cksm = checksum16(&G_fsp_msg.cmd->byte[0],(l_cmd_len));
+
+#ifdef CMDH_DEBUG
+            CMDH_DBG("CMD Address: 0x%08X, RSP Address: 0x%08X", (uint32_t) G_fsp_msg.cmd, (uint32_t) G_fsp_msg.rsp);
+
+            uint16_t l_idx = 0;
+            uint16_t l_word = 0;
+            uint32_t l_words[4] = {0};
+
+            for(l_idx=0; l_idx < l_cmd_len; l_idx++)
+            {
+                if( (0 == (l_idx % 16)) && (l_idx != 0) )
+                {
+                    CMDH_DBG("0x%08X: 0x%08X 0x%08X 0x%08X 0x%08X", ((uint32_t) G_fsp_msg.cmd) + (l_idx-16), l_words[0], l_words[1], l_words[2], l_words[3]);
+                    l_words[0] = 0;
+                    l_words[1] = 0;
+                    l_words[2] = 0;
+                    l_words[3] = 0;
+                }
+                l_word = (l_idx % 16) / 4;
+                l_words[l_word] |= (G_fsp_msg.cmd->byte[l_idx] << (24 - (8*((l_idx % 16) % 4))));
+            }
+
+            if( 0 != (l_idx % 16) )
+            {
+                CMDH_DBG("0x%08X: 0x%08X 0x%08X 0x%08X 0x%08X", (l_idx-(l_idx % 16)), l_words[0], l_words[1], l_words[2], l_words[3]);
+            }
+            CMDH_DBG("Checksum: 0x%04X", l_cksm);
+#endif
             if(l_cksm != CONVERT_UINT8_ARRAY_UINT16(G_fsp_msg.cmd->byte[l_cmd_len],
                                                     G_fsp_msg.cmd->byte[l_cmd_len+1]))
             {
diff --git a/src/occ_405/img_defs.mk b/src/occ_405/img_defs.mk
index 0fcbb44..529bdf2 100644
--- a/src/occ_405/img_defs.mk
+++ b/src/occ_405/img_defs.mk
@@ -167,7 +167,7 @@ SSX_THREAD_SUPPORT = 1
 endif
 
 ifeq "$(PPC405_MMU_SUPPORT)" ""
-PPC405_MMU_SUPPORT = 1
+PPC405_MMU_SUPPORT = 0
 endif
 
 ifeq "$(OCCHW_ASYNC_SUPPORT)" ""
diff --git a/src/occ_405/linkocc.cmd b/src/occ_405/linkocc.cmd
index f78fbba..e15a4f3 100755
--- a/src/occ_405/linkocc.cmd
+++ b/src/occ_405/linkocc.cmd
@@ -78,7 +78,10 @@ OUTPUT_FORMAT(elf32-powerpc);
 // The SRAM controller aliases the SRAM at 8 x 128MB boundaries to support
 // real-mode memory attributes using DCCR, ICCR etc.  Noncacheable access is
 // the next-to-last 128MB PPC405 region. Write-though access is the
-// next-to-next-to-last 128MB PPC405 region
+// next-to-next-to-last 128MB PPC405 region. For our purposes, this means that:
+// -- 0xF7F00000 - 0xF7FC0000 is our noncacheable SRAM address space
+// -- 0xEFF00000 - 0xEFFC0000 is our writethrough SRAM address space
+// -- 0xFFF00000 - 0xFFFC0000 is cached for both reads and writes
 
 #define noncacheable_offset 0x08000000
 #define noncacheable_origin (origin - 0x08000000)
@@ -378,17 +381,6 @@ SECTIONS
     . = . + writethrough_offset;
 #endif
 
-    // To enable non-cacheable sections w/o the MMU will require setting up
-    // the linker script to use aliased addresses of the SRAM.
-
-#if PPC405_MMU_SUPPORT == 0
-    ASSERT(((_NONCACHEABLE_RO_SECTION_SIZE == 0) &&
-            (_NONCACHEABLE_SECTION_SIZE == 0) &&
-            (_WRITETHROUGH_SECTION_SIZE == 0)),
-           " Non-cacheable and writethrough sections are currently only supported for MMU-enabled configurations.  Enabling these capabilities for untranslated addresses will require some modifications of the linker script.  ")
-#endif
-
-
     ////////////////////////////////
     // Read-only Data
     ////////////////////////////////
@@ -566,9 +558,20 @@ SECTIONS
     _IMP_TRACE_BUFFER_BASE = 0xfffb8000;
     _IMP_TRACE_BUFFER_SIZE = 0x2000;
     . = _ERR_TRACE_BUFFER_BASE;
+#if !PPC405_MMU_SUPPORT
+    . = . - writethrough_offset;
+    _LMA = . + writethrough_offset;
+    .err_trac . : AT (_LMA) {*(err_trac) . = ALIGN(_ERR_TRACE_BUFFER_SIZE);}
+    _LMA = . + writethrough_offset;
+    .inf_trac . : AT (_LMA) {*(inf_trac) . = ALIGN(_INF_TRACE_BUFFER_SIZE);}
+    _LMA = . + writethrough_offset;
+    .imp_trac . : AT (_LMA) {*(imp_trac) . = ALIGN(_IMP_TRACE_BUFFER_SIZE);}
+    . = . + writethrough_offset;
+#else
     .err_trac . : {*(err_trac) . = ALIGN(_ERR_TRACE_BUFFER_SIZE);} > sram
     .inf_trac . : {*(inf_trac) . = ALIGN(_INF_TRACE_BUFFER_SIZE);} > sram
     .imp_trac . : {*(imp_trac) . = ALIGN(_IMP_TRACE_BUFFER_SIZE);} > sram
+#endif
     . = __CUR_COUNTER__;
 
     ////////////////////////////////
@@ -578,7 +581,16 @@ SECTIONS
     _FIR_HEAP_SECTION_BASE = 0xfffba000;
     _FIR_HEAP_SECTION_SIZE = 0x3000;
     . = _FIR_HEAP_SECTION_BASE;
+
+#if !PPC405_MMU_SUPPORT
+    . = . - writethrough_offset;
+    _LMA = . + writethrough_offset;
+    .firHeap . : AT (_LMA) {*(firHeap) . = ALIGN(1024);}
+    . = . + writethrough_offset;
+#else
     .firHeap . : {*(firHeap) . = ALIGN(1024);} > sram
+#endif
+
     . = __CUR_COUNTER__;
 
     ////////////////////////////////
@@ -588,7 +600,16 @@ SECTIONS
     _FIR_PARMS_SECTION_BASE = 0xfffbd000;
     _FIR_PARMS_SECTION_SIZE = 0x1000;
     . = _FIR_PARMS_SECTION_BASE;
+
+#if !PPC405_MMU_SUPPORT
+    . = . - noncacheable_offset;
+    _LMA = . + noncacheable_offset;
+    .firParms . : AT (_LMA) {*(firParms) . = ALIGN(1024);}
+    . = . + noncacheable_offset;
+#else
     .firParms . : {*(firParms) . = ALIGN(1024);} > sram
+#endif
+
     . = __CUR_COUNTER__;
 
     ////////////////////////////////
@@ -601,8 +622,25 @@ SECTIONS
     _LINEAR_RD_WINDOW_SECTION_BASE = 0xfffbf000;     // Update FFDC_BUFFER_ADDR if changed
     _LINEAR_RD_WINDOW_SECTION_SIZE = 0x1000;
     . = _LINEAR_WR_WINDOW_SECTION_BASE;
+#if !PPC405_MMU_SUPPORT
+    . = . - noncacheable_offset;
+    _LMA = . + noncacheable_offset;
+    .linear_wr . : AT (_LMA) {*(linear_wr) . = ALIGN(_LINEAR_WR_WINDOW_SECTION_SIZE);}
+#else
     .linear_wr . : {*(linear_wr) . = ALIGN(_LINEAR_WR_WINDOW_SECTION_SIZE);} > sram
+#endif
+
+#if !PPC405_MMU_SUPPORT
+    . = . + noncacheable_offset - writethrough_offset;
+    _LMA = . + writethrough_offset;
+    .linear_rd . : AT (_LMA) {*(linear_rd) . = ALIGN(_LINEAR_RD_WINDOW_SECTION_SIZE);}
+#else
     .linear_rd . : {*(linear_rd) . = ALIGN(_LINEAR_RD_WINDOW_SECTION_SIZE);} > sram
+#endif
+
+#if !PPC405_MMU_SUPPORT
+    . = . + writethrough_offset;
+#endif
 
     . = __CUR_COUNTER__;
 
diff --git a/src/occ_405/main.c b/src/occ_405/main.c
index 85571a6..7023233 100755
--- a/src/occ_405/main.c
+++ b/src/occ_405/main.c
@@ -401,6 +401,7 @@ void create_tlb_entry(uint32_t address, uint32_t size)
         tlb_entry_size = PAGE_ALIGNED_SIZE(size);
     }
 
+#if PPC405_MMU_SUPPORT
     // define DTLB for PGPE image header
     l_rc = ppc405_mmu_map(
         tlb_entry_address,
@@ -410,6 +411,7 @@ void create_tlb_entry(uint32_t address, uint32_t size)
         TLBLO_I,         //Read-only, Cache-inhibited
         NULL
         );
+#endif
 
     if(l_rc != SSX_OK)
     {