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| author | Chris Cain <cjcain@us.ibm.com> | 2016-12-09 14:07:04 -0600 |
|---|---|---|
| committer | Christopher J. Cain <cjcain@us.ibm.com> | 2016-12-12 11:08:05 -0500 |
| commit | e29c6746a230904209290fa6d2a940898c581639 (patch) | |
| tree | 2826543a50ef8c363cadc6c2fa217d262eebd7fd /src/occ_gpe1 | |
| parent | bbacf6b912cb813b6a19804d3bb8bbe0d93dbece (diff) | |
| download | talos-occ-e29c6746a230904209290fa6d2a940898c581639.tar.gz talos-occ-e29c6746a230904209290fa6d2a940898c581639.zip | |
Update DIMM i2c divisor to increase clock rate
In legacy mode, a divisor of 0x0049 will give approx freq of 391kHZ
This value will allow margin for clock variation.
For reference:
0x0177 is approx 77kHz
0x0048 is approx 396kHz
0x0049 is approx 391kHz
Change-Id: I7ff68f414f5afff8ca6d96f51c0b2f25eeb0841f
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/33694
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Diffstat (limited to 'src/occ_gpe1')
| -rw-r--r-- | src/occ_gpe1/gpe1_dimm_read.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/occ_gpe1/gpe1_dimm_read.c b/src/occ_gpe1/gpe1_dimm_read.c index 8f542d6..e0ee84c 100644 --- a/src/occ_gpe1/gpe1_dimm_read.c +++ b/src/occ_gpe1/gpe1_dimm_read.c @@ -245,7 +245,10 @@ void dimm_write_mode(ipc_msg_t* cmd, void* arg) // MODE_REGISTER scomAddr = I2C_MODE_REG | SCOM_ENGINE_OFFSET(args->i2cEngine); - regValue = 0x0177000000000000; + // 0-15: Bit Rate Divisor - 0x0049 gives approx 391kHz (and allows margin for clock variation) + // 16-21: Port Number (0-5) + // 22-26: reserved (0s) + regValue = 0x0049000000000000; if ((args->i2cPort > 0) && (args->i2cPort < 6)) { regValue |= ((uint64_t)args->i2cPort << 42); |
