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| author | William Bryan <wilbryan@us.ibm.com> | 2017-08-03 14:01:43 -0500 |
|---|---|---|
| committer | William A. Bryan <wilbryan@us.ibm.com> | 2017-08-03 16:55:47 -0400 |
| commit | 98a36c5dc201034f62fac0e72b1c4cf29af5b117 (patch) | |
| tree | 539931af44d5e479704225f33e6cf3a37b9b3caf /src/occ_gpe1 | |
| parent | 4459c1bef687bd465d4b3084ca0de4290ef622fc (diff) | |
| download | talos-occ-98a36c5dc201034f62fac0e72b1c4cf29af5b117.tar.gz talos-occ-98a36c5dc201034f62fac0e72b1c4cf29af5b117.zip | |
Set MSR before DIMM temp task to avoid machine check
Change-Id: I95ce4cccae9fe315570cd2bd7347c370781dc745
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44178
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Douglas R. Gilbert <dgilbert@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_gpe1')
| -rw-r--r-- | src/occ_gpe1/gpe1_dimm_read.c | 22 |
1 files changed, 21 insertions, 1 deletions
diff --git a/src/occ_gpe1/gpe1_dimm_read.c b/src/occ_gpe1/gpe1_dimm_read.c index 86d80b6..133ad9f 100644 --- a/src/occ_gpe1/gpe1_dimm_read.c +++ b/src/occ_gpe1/gpe1_dimm_read.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER OnChipController Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2015 */ +/* Contributors Listed Below - COPYRIGHT 2015,2017 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -93,6 +93,23 @@ void gpe_dimm_sm(ipc_msg_t* cmd, void* arg) args->error.error = 0; args->error.ffdc = 0; + // Need to mask machine checks for I2C master: + // + // Turn off MCR bit will prevent machine check on error on scom readings (MSR bits 1:7) + // rc == 1 resource occupied (see ppe42_scom.h) Action: return with rc + // rc == 2 Core is fenced, offline Action: return with rc + // rc == 3 partial good + // rc == 4 address error + // rc == 5 clock error + // rc == 6 packet error + // rc == 7 timeout + // + // Clear: last SIB rc (SIBRC) and rc accumulator (SIMBRCA) + // Set: SIB Error Mask to prevent machine checks for any rcs + const uint32_t orig_msr = mfmsr(); + const uint32_t msr = (orig_msr & ~(MSR_SIBRC | MSR_SIBRCA)) | MSR_SEM; + mtmsr(msr); + switch(args->state) { case DIMM_STATE_INIT: @@ -151,6 +168,9 @@ void gpe_dimm_sm(ipc_msg_t* cmd, void* arg) pk_halt(); } + // Restore original MSR and clear SIBRC and SIBRCA + mtmsr(orig_msr & ~(MSR_SIBRC | MSR_SIBRCA)); + } // end gpe_dimm_sm() |
