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| author | mbroyles <mbroyles@us.ibm.com> | 2017-08-06 19:08:00 -0500 |
|---|---|---|
| committer | William A. Bryan <wilbryan@us.ibm.com> | 2017-08-14 15:18:26 -0400 |
| commit | 8a335d83ed938f05f95ca1cfdbbb5292053ed51f (patch) | |
| tree | bd2b38c6df596f3d3bf9f70f8a54a8a205e4e2e1 /src/occ_gpe1 | |
| parent | 71b5f68da8b725f9c5251261b41fd824e652e491 (diff) | |
| download | talos-occ-8a335d83ed938f05f95ca1cfdbbb5292053ed51f.tar.gz talos-occ-8a335d83ed938f05f95ca1cfdbbb5292053ed51f.zip | |
Initial 405 GPU support
Change-Id: I6e957ca1aa643d257274e99957df5b15ac8c889b
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44254
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_gpe1')
| -rw-r--r-- | src/occ_gpe1/ipc_func_tables.c | 26 |
1 files changed, 25 insertions, 1 deletions
diff --git a/src/occ_gpe1/ipc_func_tables.c b/src/occ_gpe1/ipc_func_tables.c index 0e43fad..d694e3e 100644 --- a/src/occ_gpe1/ipc_func_tables.c +++ b/src/occ_gpe1/ipc_func_tables.c @@ -23,14 +23,38 @@ /* */ /* IBM_PROLOG_END_TAG */ #include "ipc_api.h" +#include "ipc_async_cmd.h" #include "gpe1_dimm.h" +#include "gpu_structs.h" void gpe_dimm_control(ipc_msg_t* cmd, void* arg); void gpe1_nop(ipc_msg_t* cmd, void* arg); void gpe_reset_mem_deadman(ipc_msg_t* cmd, void* arg); void gpe_24x7(ipc_msg_t* cmd, void* arg); void gpe_mem_power_control(ipc_msg_t* cmd, void* arg); +void gpe_gpu_sm(ipc_msg_t* cmd, void* arg) +{ + // No GPU support. The 405 should only be calling this on OCC GPU supported + // systems. Those systems require a different OCC GPE1 image with GPU support. + // This is indication of an OCC image build issue. + // Return error so the 405 can log an error and disable GPU monitoring. + int rc; + ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd; + gpu_sm_args_t *args = (gpu_sm_args_t*)async_cmd->cmd_data; + // set error return code for no GPU support + args->error.rc = GPE_RC_NO_GPU_SUPPORT; + PK_TRACE("E>gpu_sm: No GPU support!"); + + // Send back IPC response of success (IPC operation itself succeeded) + // 405 will handle no support set in error + rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS); + if(rc) + { + PK_TRACE("E>gpu_sm: Failed to send response back. Halting GPE1", rc); + pk_halt(); + } +} // Function table for multi target (common) functions IPC_MT_FUNC_TABLE_START @@ -52,7 +76,7 @@ IPC_HANDLER(gpe1_nop, 0) // 2 - IPC_ST_GPE1_NOP IPC_HANDLER(gpe_reset_mem_deadman, 0) // 3 - IPC_ST_RESET_MEM_DEADMAN IPC_HANDLER(gpe_24x7, 0) // 4 - IPC_ST_24_X_7_FUNCID IPC_HANDLER(gpe_mem_power_control, 0) // 5 - IPC_ST_MEM_POWER_CONTROL_FUNCID -IPC_HANDLER_DEFAULT // 6 +IPC_HANDLER(gpe_gpu_sm, 0) // 6 - IPC_ST_GPU_SM_FUNCID IPC_HANDLER_DEFAULT // 7 IPC_HANDLER_DEFAULT // 8 IPC_HANDLER_DEFAULT // 9 |
