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author | Chris Cain <cjcain@us.ibm.com> | 2017-02-06 10:04:54 -0600 |
---|---|---|
committer | Christopher J. Cain <cjcain@us.ibm.com> | 2017-02-14 12:32:31 -0500 |
commit | 1747f6fbb5ad8e61e31c4c320bbff01e5636da62 (patch) | |
tree | 25191de8d8aa007ad32a65cee1370b82d0c09899 /src/occ_gpe1 | |
parent | 9405a91ef65ac39eb27cda9c5db52c20cc4cc30b (diff) | |
download | talos-occ-1747f6fbb5ad8e61e31c4c320bbff01e5636da62.tar.gz talos-occ-1747f6fbb5ad8e61e31c4c320bbff01e5636da62.zip |
Fix DIMM temperature reads
FIFO4 register requires a 4 byte read or will hang.
OCC will request 4 byte read, but only look at first 2 for temperature.
FIFO register can only read one byte per request which is less efficient.
Change-Id: Ia0bbbc70f5b7de76f1bea64279b2ff7dd5b5a861
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35974
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Diffstat (limited to 'src/occ_gpe1')
-rwxr-xr-x | src/occ_gpe1/gpe1.h | 8 | ||||
-rwxr-xr-x | src/occ_gpe1/gpe1_dimm.h | 6 | ||||
-rw-r--r-- | src/occ_gpe1/gpe1_dimm_control.c | 8 | ||||
-rw-r--r-- | src/occ_gpe1/gpe1_dimm_read.c | 15 |
4 files changed, 14 insertions, 23 deletions
diff --git a/src/occ_gpe1/gpe1.h b/src/occ_gpe1/gpe1.h index af26829..4ce0823 100755 --- a/src/occ_gpe1/gpe1.h +++ b/src/occ_gpe1/gpe1.h @@ -48,14 +48,6 @@ #define I2C_FIFO4_REG_READ 0x000A0012 -// I2C Status Reigster masks -#define STATUS_ERROR_MASK 0xFE80330000000000 -#define STATUS_ERROR_OR_COMPLETE_MASK 0xFF80330000000000 -#define STATUS_COMPLETE_MASK 0x0100000000000000 -#define PEEK_ERROR_MASK 0x00000000FC000000 -#define PEEK_MORE_DATA 0x0000000002000000 - - // Debug trace #ifdef GPE1_DEBUG #define GPE1_DIMM_DBG(frmt,args...) \ diff --git a/src/occ_gpe1/gpe1_dimm.h b/src/occ_gpe1/gpe1_dimm.h index c3249c6..b151f87 100755 --- a/src/occ_gpe1/gpe1_dimm.h +++ b/src/occ_gpe1/gpe1_dimm.h @@ -44,9 +44,9 @@ #define SCOM_ENGINE_OFFSET(engine) (engine << 12) -// I2C Status Reigster masks -#define STATUS_ERROR_MASK 0xFE80330000000000 -#define STATUS_ERROR_OR_COMPLETE_MASK 0xFF80330000000000 +// I2C Status Register masks +#define STATUS_ERROR_MASK 0xFC80000000000000 +#define STATUS_ERROR_OR_COMPLETE_MASK 0xFF80000000000000 #define STATUS_COMPLETE_MASK 0x0100000000000000 #define PEEK_ERROR_MASK 0x00000000FC000000 #define PEEK_MORE_DATA 0x0000000002000000 diff --git a/src/occ_gpe1/gpe1_dimm_control.c b/src/occ_gpe1/gpe1_dimm_control.c index 65ca4b6..a87a464 100644 --- a/src/occ_gpe1/gpe1_dimm_control.c +++ b/src/occ_gpe1/gpe1_dimm_control.c @@ -146,15 +146,16 @@ void gpe_reset_mem_deadman(ipc_msg_t* cmd, void* arg) ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd; reset_mem_deadman_args_t *args = (reset_mem_deadman_args_t*)async_cmd->cmd_data; - int mca = args->mca; // Nimbus MCA; mc_pair = mca >>2 and port = mca & 3 - args->error.error = 0; args->error.ffdc = 0; do { // read Deadman timer's SCOM Register for specified MCA (MC pair and port numbers) // @TODO: uncomment when deadman timer scom registers are definied in simics. RTC: 163713, RTC: 163934 - //rc = getscom_abs(DEADMAN_TIMER_MCA(mca), ®Value); +#if 0 + int mca = args->mca; // Nimbus MCA; mc_pair = mca >>2 and port = mca & 3 + + rc = getscom_abs(DEADMAN_TIMER_MCA(mca), ®Value); if(rc) { PK_TRACE("gpe_reset_mem_deadman: Deadman timer read failed" @@ -172,6 +173,7 @@ void gpe_reset_mem_deadman(ipc_msg_t* cmd, void* arg) mca, DEADMAN_TIMER_MCA(mca), regValue); } +#endif } while(0); // send back a response, IPC success even if ffdc/rc are non zeros diff --git a/src/occ_gpe1/gpe1_dimm_read.c b/src/occ_gpe1/gpe1_dimm_read.c index e0ee84c..86d80b6 100644 --- a/src/occ_gpe1/gpe1_dimm_read.c +++ b/src/occ_gpe1/gpe1_dimm_read.c @@ -370,10 +370,12 @@ void dimm_initiate_read(ipc_msg_t* cmd, void* arg) if ((regValue & STATUS_ERROR_OR_COMPLETE_MASK) == STATUS_COMPLETE_MASK) { // Status register indicates no errors and last command completed. - // Write the I2C command register with a 2 byte read request + // Write the I2C command register with a 2 byte read request. + // Since FIFO4 can read 4 bytes in one operation, we will do a read of 4 bytes + // and only look at first 2 bytes. (FIFO4 will hang if only try to read 2 bytes) scomAddr = I2C_COMMAND_REG | SCOM_ENGINE_OFFSET(args->i2cEngine); - // start+address+stop + slave_address, rw=1=read, length=2 - regValue = 0xD001000200000000; + // start+address+stop + slave_address, rw=1=read, length=4 + regValue = 0xD001000400000000; regValue |= ((uint64_t)args->i2cAddr << 48); rc = putscom_abs(scomAddr, regValue); if(rc) @@ -497,12 +499,7 @@ void dimm_read_temp(ipc_msg_t* cmd, void* arg) WORD_HIGH(regValue), WORD_LOW(regValue)); gpe_set_ffdc(&(args->error), scomAddr, GPE_RC_I2C_ERROR, regValue); } - else if (regValue & PEEK_MORE_DATA) - { - // The data_request bit is non-zero, but no more data is needed! - PK_TRACE("dimm_read_temp: Got data, but more data needs access??"); - gpe_set_ffdc(&(args->error), scomAddr, GPE_RC_NOT_COMPLETE, regValue); - } + // PEEK_MORE_DATA will be set because we only read 2 of the 4 bytes (ignore this bit) } } // else, all data not available yet (NOT_COMPLETE) |