GPE0 error and ffdc codes, and remove most pk_halts

modified the wait_spi_completion function to make it args_t independent
eliminated all scom/spi related pk_halts, left only ipc related pk_halt
using new APSS_RC_XXX rc codes
used apss_set_ffdc to set rc,  ffdc, and address fields
cleaned some comments
added four PK traces to mark the start and completion of init routines
removed gpe0 from PK traces, and added register address and scom operation
added description for all functions
deleted all assembly files

Change-Id: I5a265c14b917b7c5d87647dad537725ee7f47001
RTC: 131177
Reviewed-on: http://gfw160.aus.stglabs.ibm.com:8080/gerrit/20277
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Fadi Kassem <fmkassem@us.ibm.com>
Reviewed-by: Wael Elessawy <welessa@us.ibm.com>
Tested-by: Wael Elessawy <welessa@us.ibm.com>

13 files changed, 291 insertions, 1743 deletions

diff --git a/src/occ_gpe0/apss_altitude.pS b/src/occ_gpe0/apss_altitude.pS
deleted file mode 100755
index df72fcc..0000000
--- a/src/occ_gpe0/apss_altitude.pS
+++ /dev/null
@@ -1,159 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/occ/gpe/apss_altitude.pS $
-#
-# OpenPOWER OnChipController Project
-#
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-//////////////////////////////////////////////////////////////////////
-// Includes
-//////////////////////////////////////////////////////////////////////
-.nolist
-#include "pgp.h"
-#include "pgas.h"
-.list
-
-//////////////////////////////////////////////////////////////////////
-// Define Address Space
-//////////////////////////////////////////////////////////////////////
-.oci
-
-//////////////////////////////////////////////////////////////////////
-// Define Symbols
-//////////////////////////////////////////////////////////////////////
-
-#include <pss_constants.h>
-
-#define GPE_PROG_ID 0x0002
-
-//////////////////////////////////////////////////////////////////////
-// Define Structures
-//////////////////////////////////////////////////////////////////////
-
-// Declare the offsets of the struct that will be passed to the
-// GPE program via the ETR register
-//
-// struct G_gpe_apss_read_altitude_args =
-// {
-.struct     0
-ERROR_RC:
-    .struct ERROR_RC + 8
-ERROR_FFDC:
-    .struct ERROR_FFDC + 8
-ALTITUDE:
-// };
-
-//////////////////////////////////////////////////////////////////////
-// Begin Program
-//////////////////////////////////////////////////////////////////////
-
-.text
-
-#include <gpe_macros.h>
-#include <pss_macros.h>
-
-//--------------------------------------------------------------------
-// PORE-GPE Routine Specification:
-//
-// Name: GPE_apss_read_altitude
-//
-// Description:  Read APSS altitude
-//
-// Inputs:       G_gpe_apss_read_altitude_args
-//     struct {
-//         PoreGpeErrorStruct error;
-//         uint16_t altitude;     // This is where the altitude will be stored (output)
-//         uint8_t reserved[6];   // Requried since GPE only does 8 byte writes.
-//     } G_gpe_apss_read_altitude_args
-//     struct {
-//         uint64_t rc;          // This should be read as 63:32=addr, 31:0=rc
-//         uint64_t ffdc;        // Whatever GPE program puts in for FFDC data
-//     } PoreGpeErrorStruct;
-//
-// Outputs:      Altitude (and FFDC on failure)
-//
-// End PORE-GPE Routine Specification
-//--------------------------------------------------------------------
-.global GPE_apss_read_altitude
-GPE_apss_read_altitude:
-
-    // Copy passed Structure Pointer into A1
-    mr      A1, ETR
-
-    // Wait for SPI operations to be complete (10usec timeout)
-    _wait_for_spi_ops_complete 10, error_timeout
-
-    // Setup control regs
-    // frame_size=16, out_count=16, in_delay1=never, in_count2=16
-    _putscom SPIPSS_P2S_CTRL_REG0, 0x410FC00004000000
-    // bridge_enable, clock_divider=7, 2 frames
-    _putscom SPIPSS_P2S_CTRL_REG1, 0x801C400000000000
-    // inter_frame_delay=25 (2.5usec)
-    _putscom SPIPSS_P2S_CTRL_REG2, 0x000C800000000000
-
-    // APSS command to get the altitude (APSS cmd 0x9000)
-    li      D0, 0x9000000000000000
-    _putscom_d0 SPIPSS_P2S_WDATA_REG
-
-    // Start SPI transaction
-    _putscom SPIPSS_P2S_COMMAND_REG, 0x8000000000000000
-
-    // wait 10usec for command to complete
-    waits (10 * MICROSECONDS)
-
-    // Wait for SPI operations to be complete (10usec timeout)
-    _wait_for_spi_ops_complete 10, error_altitude_timeout
-
-    // Read altitude and store in structure
-    _getscom SPIPSS_P2S_RDATA_REG
-    // The scom data for that cmd is in 2nd two bytes of the register (shift left 2 bytes)
-    rols    D0, D0, 16
-    std     D0, ALTITUDE, A1
-
-    halt
-
-
-error_statusreg:
-    // An error/reserved bit was set when reading p2s status register...
-    // D0: P2S_STATUS_REG
-    _saveffdc GPE_PROG_ID, 0x0002
-    halt
-
-
-error_timeout:
-    // p2s_ongoing bit was never cleared after several retries...
-    // D0: P2S_STATUS_REG
-    _saveffdc GPE_PROG_ID, 0x0001
-    halt
-
-
-error_altitude_timeout:
-    // After sending the read altitude command, the p2s_ongoing bit was
-    // never cleared after several retries...
-    // D0: P2S_STATUS_REG
-    _saveffdc GPE_PROG_ID, 0x0003
-    halt
-
-
-//////////////////////////////////////////////////////////////////////
-// End of Program
-//////////////////////////////////////////////////////////////////////
diff --git a/src/occ_gpe0/apss_init.c b/src/occ_gpe0/apss_init.c
index ca58404..ea40cbf 100644
--- a/src/occ_gpe0/apss_init.c
+++ b/src/occ_gpe0/apss_init.c
@@ -36,7 +36,7 @@ uint32_t apss_start_spi_command(initGpioArgs_t * args, uint8_t i_noWait)
 

         if (!i_noWait)

         {

-            rc = wait_spi_completion(args, SPIPSS_P2S_STATUS_REG, 10);

+            rc = wait_spi_completion(&(args->error), SPIPSS_P2S_STATUS_REG, 10);

             if (rc)

             {

                 PK_TRACE("apss_start_spi_command: Timed out waiting for ops to complete. rc = 0x%08x",

@@ -63,14 +63,17 @@ void apss_init_gpio(ipc_msg_t* cmd, void* arg)
     //Note: arg was set to 0 in ipc func table (ipc_func_tables.c), so don't use it

 

     uint32_t            rc;

+    uint32_t            ipc_send_rc;

     ipc_async_cmd_t     *async_cmd = (ipc_async_cmd_t*)cmd;

     initGpioArgs_t      *args = (initGpioArgs_t*)async_cmd->cmd_data;

     uint64_t            regValue = 0;

 

+    PK_TRACE("apss_init_gpio: started.");

+

     do

     {

         // Wait for SPI operations to be complete (up to 10usec timeout)

-        rc = wait_spi_completion(args, SPIPSS_P2S_STATUS_REG, 10);

+        rc = wait_spi_completion(&(args->error), SPIPSS_P2S_STATUS_REG, 10);

         if (rc)

         {

             PK_TRACE("apss_init_gpio: Timed out waiting for ops to complete. rc = 0x%08x", rc);

@@ -197,14 +200,21 @@ void apss_init_gpio(ipc_msg_t* cmd, void* arg)
     }while(0);

 

     // send back a successful response.  OCC will check rc and ffdc

-    rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);

+    ipc_send_rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);

 

-    if(rc)

+    if(ipc_send_rc)

     {

-        PK_TRACE("apss_init_gpio: Failed to send response back. Halting GPE0", rc);

-        apss_set_ffdc(&(args->error), 0x00, rc, regValue);

+        PK_TRACE("apss_init_gpio: Failed to send response back. rc = 0x%08x. Halting GPE0",

+                 ipc_send_rc);

+        apss_set_ffdc(&(args->error), 0x00, ipc_send_rc, regValue);

         pk_halt();

     }

+

+    if(rc == 0) // if ipc_send_rc is 0, wont reach this instruction (pk_halt)

+    {

+        PK_TRACE("apss_init_gpio: completed successfully.");

+    }

+

 }

 

 /*

@@ -222,14 +232,17 @@ void apss_init_mode(ipc_msg_t* cmd, void* arg)
 

     uint32_t                rc = APSS_RC_SUCCESS;

     uint32_t                ipc_rc = IPC_RC_SUCCESS;

+    uint32_t                ipc_send_rc;

     ipc_async_cmd_t         *async_cmd = (ipc_async_cmd_t*)cmd;

     setApssModeArgs_t       *args = (setApssModeArgs_t*)async_cmd->cmd_data;

     uint64_t                regValue = 0;

 

+    PK_TRACE("apss_init_mode: started.");

+

     do

     {

         // Wait for SPI operations to be complete (up to 10usec timeout)

-        rc = wait_spi_completion(args, SPIPSS_P2S_STATUS_REG, 10);

+        rc = wait_spi_completion(&(args->error), SPIPSS_P2S_STATUS_REG, 10);

         if (rc)

         {

             PK_TRACE("apss_init_mode: Timed out waiting for ops to complete. rc = 0x%08x", rc);

@@ -318,16 +331,22 @@ void apss_init_mode(ipc_msg_t* cmd, void* arg)
     }while(0);

 

     // send back a response

-    PK_TRACE("apss_init_mode: Sending APSS response ReturnCode:0x%X. APSSrc:0x%X (0 = Success)", 

+    PK_TRACE("apss_init_mode: Sending APSS response ReturnCode:0x%X. APSSrc:0x%X (0 = Success)",

              ipc_rc, rc);

-    rc = ipc_send_rsp(cmd, ipc_rc);

+    ipc_send_rc = ipc_send_rsp(cmd, ipc_rc);

 

     //If we fail to send ipc response, then this error takes prescedence over any other error.

     //TODO: See if there's another space to write the error out to.

-    if(rc)

+    if(ipc_send_rc)

     {

-        PK_TRACE("apss_init_mode: Failed to send response back to mode initialization. Halting GPE0", ipc_rc);

-        apss_set_ffdc(&(args->error), 0x00, ipc_rc, regValue);

+        PK_TRACE("apss_init_mode: Failed to send response back to mode initialization. Halting GPE0",

+                 ipc_send_rc);

+        apss_set_ffdc(&(args->error), 0x00, ipc_send_rc, regValue);

         pk_halt();

     }

+

+    if(rc == 0 && ipc_rc == IPC_RC_SUCCESS) // if ipc_send_rc, wont reach this instruction (pk_halt)

+    {

+        PK_TRACE("apss_init_mode: completed successfully.");

+    }

 }

diff --git a/src/occ_gpe0/apss_meas_read_complete.pS b/src/occ_gpe0/apss_meas_read_complete.pS
deleted file mode 100755
index 3967034..0000000
--- a/src/occ_gpe0/apss_meas_read_complete.pS
+++ /dev/null
@@ -1,130 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/occ/gpe/apss_meas_read_complete.pS $
-#
-# OpenPOWER OnChipController Project
-#
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-//////////////////////////////////////////////////////////////////////
-// Includes
-//////////////////////////////////////////////////////////////////////
-.nolist
-#include "pgp.h"
-#include "pgas.h"
-.list
-
-//////////////////////////////////////////////////////////////////////
-// Define Address Space
-//////////////////////////////////////////////////////////////////////
-.oci
-
-//////////////////////////////////////////////////////////////////////
-// Define Symbols
-//////////////////////////////////////////////////////////////////////
-
-#include <pss_constants.h>
-
-#define GPE_PROG_ID 0x0006
-
-//////////////////////////////////////////////////////////////////////
-// Define Structures
-//////////////////////////////////////////////////////////////////////
-
-// Declare the offsets of the struct that will be passed to the
-// GPE program via the ETR register
-//
-// struct G_gpe_apss_continue_pwr_meas_read_args =
-// {
-.struct     0
-ERROR_RC:
-    .struct ERROR_RC + 8
-ERROR_FFDC:
-    .struct ERROR_FFDC + 8
-MEASUREMENTS:
-    .struct MEASUREMENTS + 24
-MEASUREMENTS_TOD:
-// };
-
-//////////////////////////////////////////////////////////////////////
-// Begin Program
-//////////////////////////////////////////////////////////////////////
-
-.text
-
-#include <gpe_macros.h>
-#include <pss_macros.h>
-
-//--------------------------------------------------------------------
-// PORE-GPE Routine Specification:
-//
-// Name: GPE_apss_complete_pwr_meas_read
-//
-// Description:  Complete a read of the power measurement from APSS
-//
-// Inputs:       G_gpe_complete_pwr_meas_read_args
-//     struct {
-//         PoreGpeErrorStruct error;
-//         ApssPwrMeas_t meas;
-//         uint64_t meas_data[4]; // G_apss_pwr_meas (2nd block of data) (output from APSS)
-//     } G_gpe_complete_pwr_meas_read_args
-//     struct {
-//         uint64_t rc;          // This should be read as 63:32=addr, 31:0=rc
-//         uint64_t ffdc;        // Whatever GPE program puts in for FFDC data
-//     } PoreGpeErrorStruct;
-//
-// Outputs:      ApssPwrMeas (measurement data)
-//               GPE_complete_pwr_meas_read (error on failure)
-//
-// End PORE-GPE Routine Specification
-//--------------------------------------------------------------------
-.global GPE_apss_complete_pwr_meas_read
-GPE_apss_complete_pwr_meas_read:
-
-    // Copy passed Structure Pointer into A1
-    mr      A1, ETR
-
-    // Wait for up to 5us for spi op complete, else branch to error_timeout
-    _wait_for_adc_ops_complete 100, error_timeout
-
-    // Read/save Time of Day
-    _getscom TOD_VALUE_REG
-    std D0, MEASUREMENTS_TOD, A1
-
-    halt
-
-
-error_statusreg:
-    // An error/reserved bit was set when reading adc status register...
-    // D0: ADC_STATUS_REG
-    _saveffdc GPE_PROG_ID, 0x0002
-    halt
-
-
-error_timeout:
-    // adc_ongoing bit was never cleared after several retries...
-    // D0: ADC_STATUS_REG
-    _saveffdc GPE_PROG_ID, 0x0001
-    halt
-
-//////////////////////////////////////////////////////////////////////
-// End of Program
-//////////////////////////////////////////////////////////////////////
diff --git a/src/occ_gpe0/apss_meas_read_cont.pS b/src/occ_gpe0/apss_meas_read_cont.pS
deleted file mode 100755
index 0bd44b5..0000000
--- a/src/occ_gpe0/apss_meas_read_cont.pS
+++ /dev/null
@@ -1,136 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/occ/gpe/apss_meas_read_cont.pS $
-#
-# OpenPOWER OnChipController Project
-#
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-//////////////////////////////////////////////////////////////////////
-// Includes
-//////////////////////////////////////////////////////////////////////
-.nolist
-#include "pgp.h"
-#include "pgas.h"
-.list
-
-//////////////////////////////////////////////////////////////////////
-// Define Address Space
-//////////////////////////////////////////////////////////////////////
-.oci
-
-//////////////////////////////////////////////////////////////////////
-// Define Symbols
-//////////////////////////////////////////////////////////////////////
-
-#include <pss_constants.h>
-
-#define GPE_PROG_ID 0x0005
-
-//////////////////////////////////////////////////////////////////////
-// Define Structures
-//////////////////////////////////////////////////////////////////////
-
-// Declare the offsets of the struct that will be passed to the
-// GPE program via the ETR register
-//
-// struct G_gpe_apss_continue_pwr_meas_read_args =
-// {
-.struct     0
-ERROR_RC:
-    .struct ERROR_RC + 8
-ERROR_FFDC:
-    .struct ERROR_FFDC + 8
-MEASUREMENTS:
-// };
-
-//////////////////////////////////////////////////////////////////////
-// Begin Program
-//////////////////////////////////////////////////////////////////////
-
-.text
-
-#include <gpe_macros.h>
-#include <pss_macros.h>
-
-//--------------------------------------------------------------------
-// PORE-GPE Routine Specification:
-//
-// Name: GPE_apss_continue_pwr_meas_read
-//
-// Description:  Continue the read of the power measurement from APSS
-//
-// Inputs:       G_gpe_continue_pwr_meas_read_args
-//     struct {
-//         PoreGpeErrorStruct error;
-//         uint64_t meas_data[4]; // G_apss_pwr_meas (1st block of data) (output from APSS)
-//     } G_gpe_continue_pwr_meas_read_args
-//     struct {
-//         uint64_t rc;          // This should be read as 63:32=addr, 31:0=rc
-//         uint64_t ffdc;        // Whatever GPE program puts in for FFDC data
-//     } PoreGpeErrorStruct;
-//
-// Outputs:      GPE_continue_pwr_meas_read (error on failure)
-//
-// End PORE-GPE Routine Specification
-//--------------------------------------------------------------------
-.global GPE_apss_continue_pwr_meas_read
-GPE_apss_continue_pwr_meas_read:
-
-    // Copy passed Structure Pointer into A1
-    mr      A1, ETR
-
-    // Wait for up to 5us for spi op complete, else branch to error_timeout
-    _wait_for_adc_ops_complete 100, error_timeout
-
-    // Read/save first 32 bytes of data
-    _getscom SPIPSS_ADC_RDATA_REG0
-    std D0, MEASUREMENTS, A1
-
-    _getscom SPIPSS_ADC_RDATA_REG1
-    std D0, (MEASUREMENTS + 8), A1
-
-    _getscom SPIPSS_ADC_RDATA_REG2
-    std D0, (MEASUREMENTS + 16), A1
-
-    _getscom SPIPSS_ADC_RDATA_REG3
-    std D0, (MEASUREMENTS + 24), A1
-
-    halt
-
-
-error_statusreg:
-    // An error/reserved bit was set when reading adc status register...
-    // D0: ADC_STATUS_REG
-    _saveffdc GPE_PROG_ID, 0x0002
-    halt
-
-
-error_timeout:
-    // adc_ongoing bit was never cleared after several retries...
-    // D0: ADC_STATUS_REG
-    _saveffdc GPE_PROG_ID, 0x0001
-    halt
-
-
-//////////////////////////////////////////////////////////////////////
-// End of Program
-//////////////////////////////////////////////////////////////////////
diff --git a/src/occ_gpe0/apss_meas_read_start.pS b/src/occ_gpe0/apss_meas_read_start.pS
deleted file mode 100755
index c0b2393..0000000
--- a/src/occ_gpe0/apss_meas_read_start.pS
+++ /dev/null
@@ -1,135 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/occ/gpe/apss_meas_read_start.pS $
-#
-# OpenPOWER OnChipController Project
-#
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-//////////////////////////////////////////////////////////////////////
-// Includes
-//////////////////////////////////////////////////////////////////////
-.nolist
-#include "pgp.h"
-#include "pgas.h"
-.list
-
-//////////////////////////////////////////////////////////////////////
-// Define Address Space
-//////////////////////////////////////////////////////////////////////
-.oci
-
-//////////////////////////////////////////////////////////////////////
-// Define Symbols
-//////////////////////////////////////////////////////////////////////
-
-#include <pss_constants.h>
-
-#define GPE_PROG_ID 0x0004
-
-//////////////////////////////////////////////////////////////////////
-// Define Structures
-//////////////////////////////////////////////////////////////////////
-
-// Declare the offsets of the struct that will be passed to the
-// GPE program via the ETR register
-//
-// struct G_gpe_apss_start_pwr_meas_read_args =
-// {
-.struct     0
-ERROR_RC:
-    .struct ERROR_RC + 8
-ERROR_FFDC:
-    .struct ERROR_FFDC + 8
-// };
-
-
-//////////////////////////////////////////////////////////////////////
-// Begin Program
-//////////////////////////////////////////////////////////////////////
-
-.text
-
-#include <gpe_macros.h>
-#include <pss_macros.h>
-
-//--------------------------------------------------------------------
-// PORE-GPE Routine Specification:
-//
-// Name: GPE_apss_start_pwr_meas_read
-//
-// Description:  Start a read of the power measurement from APSS
-//
-// Inputs:       G_gpe_apss_start_pwr_meas_read_args
-//     struct {
-//         PoreGpeErrorStruct error;
-//     } G_gpe_apss_start_pwr_meas_read_args
-//     struct {
-//         uint64_t rc;          // This should be read as 63:32=addr, 31:0=rc
-//         uint64_t ffdc;        // Whatever GPE program puts in for FFDC data
-//     } PoreGpeErrorStruct;
-//
-// Outputs:      GPE_start_pwr_meas_read (error on failure)
-//
-// End PORE-GPE Routine Specification
-//--------------------------------------------------------------------
-.global GPE_apss_start_pwr_meas_read
-GPE_apss_start_pwr_meas_read:
-
-    // Copy passed Structure Pointer into A1
-    mr      A1, ETR
-
-    // Wait for up to 5us for spi op complete, else branch to error_timeout
-    _wait_for_adc_ops_complete 5, error_timeout
-
-    // Setup control regs
-    // frame_size=16, out_count=16, in_count=16
-    _putscom SPIPSS_ADC_CTRL_REG0, 0x4000100000000000
-    // ADC FSM, clock_divider=7, frames=16
-    _putscom SPIPSS_ADC_CTRL_REG1, 0x8093c00000000000
-    // ADC interframe delay (5usec)
-    _putscom SPIPSS_ADC_CTRL_REG2, 0x0019000000000000
-
-    // APSS command to continue previous command
-    _putscom SPIPSS_ADC_WDATA_REG, 0x0000000000000000
-
-    // Start SPI transaction
-    _putscom SPIPSS_ADC_COMMAND_REG, 0x8000000000000000
-
-    halt
-
-
-error_statusreg:
-    // An error/reserved bit was set when reading adc status register...
-    // D0: ADC_STATUS_REG
-    _saveffdc GPE_PROG_ID, 0x0002
-    halt
-
-
-error_timeout:
-    // adc_ongoing bit was never cleared after several retries...
-    // D0: ADC_STATUS_REG
-    _saveffdc GPE_PROG_ID, 0x0001
-    halt
-
-//////////////////////////////////////////////////////////////////////
-// End of Program
-//////////////////////////////////////////////////////////////////////
diff --git a/src/occ_gpe0/apss_read.c b/src/occ_gpe0/apss_read.c
index 87863c6..6c09717 100644
--- a/src/occ_gpe0/apss_read.c
+++ b/src/occ_gpe0/apss_read.c
@@ -32,6 +32,21 @@
 #include <apss_structs.h>
 #include "apss_util.h"
 
+/*
+ * Function Specifications:
+ *
+ * Name: apss_start_pwr_meas_read
+ *
+ * Description:  Start a read of the power measurement from APSS
+ *
+ * Inputs:       cmd is a pointer to IPC msg's cmd and cmd_data struct
+ *
+ * Outputs:      error: sets rc, address, and ffdc in the cmd_data's
+ *                      GpeErrorStruct
+ *
+ * End Function Specification
+ */
+
 void apss_start_pwr_meas_read(ipc_msg_t* cmd, void* arg)
 {
     // Note: arg was set to 0 in ipc func table (ipc_func_tables.c), so don't use it.
@@ -39,10 +54,9 @@ void apss_start_pwr_meas_read(ipc_msg_t* cmd, void* arg)
     // to the G_gpe_start_pwr_meas_read_args struct.
 
     int      rc;
-    uint64_t value; // a pointer to hold the putscom_abs register value
+    uint64_t regValue; // a pointer to hold the putscom_abs register value
     ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
     apss_start_args_t *args = (apss_start_args_t*)async_cmd->cmd_data;
- 
 
     // clear error, ffdc, and rc (feedback to 405)
     // These may be overwritten by error codes if errors occur
@@ -51,94 +65,118 @@ void apss_start_pwr_meas_read(ipc_msg_t* cmd, void* arg)
     args->error.rc = 0;
     args->error.ffdc = 0;
 
+    do{
+
+        // wait for ADC completion, or timeout after 5 micro seconds.
+        // scom register SPIPSS_ADC_STATUS_REG's bit 0 (HWCTRL_ONGOING)
+        // indicates when completion occurs.
+        rc = wait_spi_completion(&(args->error), SPIPSS_ADC_STATUS_REG, 5);
+        if(rc) // Timeout Reached, and SPI transaction didn't complete, copy over rc
+        {
+            PK_TRACE("apss_start_pwr_meas_read:wait_spi_completion Timed out, rc = 0x%08x",
+                     rc);
+            // FFDC set in wait_spi_completion
+            break;
+        }
+
+        // Setup control regs:
+
+        // SPIPSS_ADC_CTRL_REG0:
+        // frame_size=16, out_count=16, in_count=16
+        //    rc = putscom(0, SPIPSS_ADC_CTRL_REG0, uint64_t 0x4000100000000000);
+        regValue = 0x4000100000000000;
+        rc = putscom_abs(SPIPSS_ADC_CTRL_REG0, &regValue);
+        if(rc)
+        {
+            PK_TRACE("apss_start_pwr_meas_read: SPIPSS_ADC_CTRL_REG0 putscom failed. rc = 0x%08x",
+                     rc);
+            apss_set_ffdc(&(args->error), SPIPSS_ADC_CTRL_REG0, APSS_RC_SCOM_PUT_FAILED, rc);
+            break;
+        }
+
+        // SPIPSS_ADC_CTRL_REG1: ADC FSM
+        // clock_divider=7, frames=16
+        // rc = putscom_abs(SPIPSS_ADC_CTRL_REG1, 0x8093c00000000000);
+        regValue = 0x8093c00000000000;
+        rc = putscom_abs(SPIPSS_ADC_CTRL_REG1, &regValue);
+        if(rc)
+        {
+            PK_TRACE("apss_start_pwr_meas_read: SPIPSS_ADC_CTRL_REG1 putscom failed. rc = 0x%08x",
+                     rc);
+            apss_set_ffdc(&(args->error), SPIPSS_ADC_CTRL_REG1, APSS_RC_SCOM_PUT_FAILED, rc);
+            break;
+        }
+
+        // SPIPSS_ADC_CTRL_REG2: ADC interframe delay
+        // 5 usec
+        // rc = putscom_abs(SPIPSS_ADC_CTRL_REG2, 0x0019000000000000);
+        regValue = 0x0019000000000000;
+        rc = putscom_abs(SPIPSS_ADC_CTRL_REG2, &regValue);
+        if(rc)
+        {
+            PK_TRACE("apss_start_pwr_meas_read: SPIPSS_ADC_CTRL_REG2 putscom failed. rc = 0x%08x",
+                     rc);
+            apss_set_ffdc(&(args->error), SPIPSS_ADC_CTRL_REG2, APSS_RC_SCOM_PUT_FAILED, rc);
+            break;
+        }
+
+        // SPIPSS_ADC_WDATA_REG:
+        // APSS command to continue previous command
+        // rc = putscom_abs(SPIPSS_ADC_WDATA_REG, 0x0000000000000000);
+        regValue = 0x0000000000000000;
+        rc = putscom_abs(SPIPSS_ADC_WDATA_REG, &regValue);
+        if(rc)
+        {
+            PK_TRACE("apss_start_pwr_meas_read: SPIPSS_ADC_WDATA_REG putscom failed. rc = 0x%08x",
+                     rc);
+            apss_set_ffdc(&(args->error), SPIPSS_ADC_WDATA_REG, APSS_RC_SCOM_PUT_FAILED, rc);
+            break;
+        }
+
+        // SPIPSS_ADC_COMMAND_REG:
+        // Start SPI Transaction
+        // rc = putscom_abs(SPIPSS_ADC_COMMAND_REG, 0x8000000000000000);
+        regValue = 0x8000000000000000;
+        rc = putscom_abs(SPIPSS_ADC_COMMAND_REG, &regValue);
+
+        if(rc)
+        {
+            PK_TRACE("apss_start_pwr_meas_read: SPIPSS_ADC_COMMAND_REG putscom failed. rc = 0x%08x",
+                     rc);
+            apss_set_ffdc(&(args->error), SPIPSS_ADC_COMMAND_REG, APSS_RC_SCOM_PUT_FAILED, rc);
+            break;
+        }
+
+    } while(0);
 
-    // wait for ADC completion, or timeout after 5 micro seconds. 
-    // scom register SPIPSS_ADC_STATUS_REG's bit 0 (HWCTRL_ONGOING) 
-    // indicates when completion occurs.
-    rc = wait_spi_completion(args, SPIPSS_ADC_STATUS_REG, 5);
-    if(rc) // Timeout Reached, and SPI transaction didn't complete, copy over rc
-    {
-        PK_TRACE("gpe0:apss_start_pwr_meas_read:wait_spi_completion failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
-        pk_halt();
-    }
-
-    // Setup control regs: 
-
-    // SPIPSS_ADC_CTRL_REG0:
-    // frame_size=16, out_count=16, in_count=16
-    //    rc = putscom(0, SPIPSS_ADC_CTRL_REG0, uint64_t 0x4000100000000000);
-    value = 0x4000100000000000;
-    rc = putscom_abs(SPIPSS_ADC_CTRL_REG0, &value);
-
-    if(rc)
-    {
-        PK_TRACE("apss_start_pwr_meas_read on gpe0 failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
-        pk_halt();
-    }
-    
-    // SPIPSS_ADC_CTRL_REG1: ADC FSM
-    // clock_divider=7, frames=16
-    // rc = putscom_abs(SPIPSS_ADC_CTRL_REG1, 0x8093c00000000000);
-    value = 0x8093c00000000000;
-    rc = putscom_abs(SPIPSS_ADC_CTRL_REG1, &value);
-
-    if(rc)
-    {
-        PK_TRACE("apss_start_pwr_meas_read on gpe0 failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
-        pk_halt();
-    }
-
-    // SPIPSS_ADC_CTRL_REG2: ADC interframe delay
-    // 5 usec
-    // rc = putscom_abs(SPIPSS_ADC_CTRL_REG2, 0x0019000000000000);
-    value = 0x0019000000000000;
-    rc = putscom_abs(SPIPSS_ADC_CTRL_REG2, &value);
-
-    if(rc)
-    {
-        PK_TRACE("apss_start_pwr_meas_read on gpe0 failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
-        pk_halt();
-    }
-
-    // SPIPSS_ADC_WDATA_REG: 
-    // APSS command to continue previous command 
-    // rc = putscom_abs(SPIPSS_ADC_WDATA_REG, 0x0000000000000000);
-    value = 0x0000000000000000;
-    rc = putscom_abs(SPIPSS_ADC_WDATA_REG, &value);
-
-    if(rc)
-    {
-        PK_TRACE("apss_start_pwr_meas_read on gpe0 failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
-        pk_halt();
-    }
-
-    // SPIPSS_ADC_COMMAND_REG:
-    // Start SPI Transaction
-    // rc = putscom_abs(SPIPSS_ADC_COMMAND_REG, 0x8000000000000000);
-    value = 0x8000000000000000;
-    rc = putscom_abs(SPIPSS_ADC_COMMAND_REG, &value);
-
+    // send back a response, IPC success even if ffdc/rc are non zeros
+    rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);
     if(rc)
     {
-        PK_TRACE("apss_start_pwr_meas_read on gpe0 failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
+        PK_TRACE("apss_start_pwr_meas_read: Failed to send response back. Halting GPE0", rc);
+        apss_set_ffdc(&(args->error), 0x00, APSS_RC_IPC_SEND_FAILED, rc);
         pk_halt();
     }
-
-
-    // send back a response, IPC success even if ffdc/rc are non zeros
-    rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);
-
-    // return value is void
-    return;
-    //pk_halt;
 }
 
+/*
+ * Function Specifications:
+ *
+ * Name: apss_continue_pwr_meas_read
+ *
+ * Description:  Continue the read of the power measurement from APSS
+ *               Read the 16 12-bit channels
+ *
+ * Inputs:       cmd is a pointer to IPC msg's cmd and cmd_data struct
+ *
+ * Outputs:      cmd->cmd_data->meas_data[]: contains 16 channels data,
+ *                                           formated as 4*64 bits array.
+ *               error:                      sets rc, address, and ffdc
+ *                                           in the cmd_data's GpeErrorStruct
+ *
+ * End Function Specification
+ */
+
 void apss_continue_pwr_meas_read(ipc_msg_t* cmd, void* arg)
 {
     // the ipc arguments are passed through the ipc_msg_t structure, has a pointer
@@ -147,7 +185,7 @@ void apss_continue_pwr_meas_read(ipc_msg_t* cmd, void* arg)
     int          rc;
     ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
     apss_continue_args_t *args = (apss_continue_args_t*)async_cmd->cmd_data;
- 
+
 
     // Clear error, ffdc, and rc (feedback to 405)
     // These may be overwritten by error codes if errors occur
@@ -157,62 +195,91 @@ void apss_continue_pwr_meas_read(ipc_msg_t* cmd, void* arg)
     args->error.ffdc = 0;
 
 
-    // wait for ADC completion, or timeout after 100 micro seconds. 
-    // scom register SPIPSS_ADC_STATUS_REG's bit 0 (HWCTRL_ONGOING) 
-    // indicates when completion occurs.
-    rc = wait_spi_completion(args, SPIPSS_ADC_STATUS_REG, 100);
-    if(rc) // Timeout Reached, and SPI transaction didn't complete, copy returned status into rc
-           // REVIEW: Should we also copy something into the ffdc as well?
-    {
-        PK_TRACE("gpe0:apss_continue_pwr_meas_read:wait_spi_completion failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
-        pk_halt();
-    }
-
-    // REVIEW: ADC readings are done for 32 bytes = 4 * 64 bit reads 
-    // they are saved in the common OCC-GPE0 area: verify using SIMICS
-    // Check every scom read, store rc in the error.rc if it fails.
-
-    rc = getscom_abs(SPIPSS_ADC_RDATA_REG0, (uint64_t*) args->meas_data);
-    if(rc)
-    {
-        PK_TRACE("gpe0:apss_continue_pwr_meas_read:getscom_reg0 failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
-        pk_halt();
-    }
-    
-    rc = getscom_abs(SPIPSS_ADC_RDATA_REG1, (uint64_t*) &args->meas_data[1]);
-    if(rc)
-    {
-        PK_TRACE("gpe0:apss_continue_pwr_meas_read:getscom_reg1 failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
-        pk_halt();
-    }
-    
-    rc = getscom_abs(SPIPSS_ADC_RDATA_REG2, (uint64_t*) &args->meas_data[2]);
-    if(rc)
-    {
-        PK_TRACE("gpe0:apss_continue_pwr_meas_read:getscom_reg2 failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
-        pk_halt();
-    }
-    
-    rc = getscom_abs(SPIPSS_ADC_RDATA_REG3, (uint64_t*) &args->meas_data[3]);
+    do{
+        // wait for ADC completion, or timeout after 100 micro seconds.
+        // scom register SPIPSS_ADC_STATUS_REG's bit 0 (HWCTRL_ONGOING)
+        // indicates when completion occurs.
+        rc = wait_spi_completion(&(args->error), SPIPSS_ADC_STATUS_REG, 100);
+        if(rc) // Timeout Reached, and SPI transaction didn't complete
+        {
+            PK_TRACE("apss_continue_pwr_meas_read:wait_spi_completion Timed out, rc = 0x%08x",
+                     rc);
+            // FFDC already set inside wait_spi_completion
+            break;
+        }
+
+        // SIMICS VERIFY: ADC readings are done for 32 bytes = 4 * 64 bit reads
+        // they are saved in the common OCC-GPE0 area: verify using SIMICS
+        // Check every scom read, store rc in the error.rc if it fails.
+
+        // read four channels - adc[0-3] - from APSS into meas_data[0]
+        rc = getscom_abs(SPIPSS_ADC_RDATA_REG0, (uint64_t*) args->meas_data);
+        if(rc)
+        {
+            PK_TRACE("apss_continue_pwr_meas_read: SPIPSS_ADC_RDATA_REG0 getscom failed with rc = 0x%08x",
+                     rc);
+            apss_set_ffdc(&(args->error), SPIPSS_ADC_RDATA_REG0, APSS_RC_SCOM_GET_FAILED, rc);
+            break;
+        }
+
+        // read four channels - adc[4-7] - from APSS into meas_data[1]
+        rc = getscom_abs(SPIPSS_ADC_RDATA_REG1, (uint64_t*) &args->meas_data[1]);
+        if(rc)
+        {
+            PK_TRACE("apss_continue_pwr_meas_read: SPIPSS_ADC_RDATA_REG1 getscom failed with rc = 0x%08x",
+                     rc);
+            apss_set_ffdc(&(args->error), SPIPSS_ADC_RDATA_REG1, APSS_RC_SCOM_GET_FAILED, rc);
+            break;
+        }
+
+        // read four channels - adc[8-11] - from APSS into meas_data[2]
+        rc = getscom_abs(SPIPSS_ADC_RDATA_REG2, (uint64_t*) &args->meas_data[2]);
+        if(rc)
+        {
+            PK_TRACE("apss_continue_pwr_meas_read: SPIPSS_ADC_RDATA_REG2 getscom failed with rc = 0x%08x",
+                     rc);
+            apss_set_ffdc(&(args->error), SPIPSS_ADC_RDATA_REG2, APSS_RC_SCOM_GET_FAILED, rc);
+            break;
+        }
+
+        // read four channels - adc[12-15] - from APSS into meas_data[3]
+        rc = getscom_abs(SPIPSS_ADC_RDATA_REG3, (uint64_t*) &args->meas_data[3]);
+        if(rc)
+        {
+            PK_TRACE("apss_continue_pwr_meas_read: SPIPSS_ADC_RDATA_REG3 getscom failed with rc = 0x%08x",
+                     rc);
+            apss_set_ffdc(&(args->error), SPIPSS_ADC_RDATA_REG3, APSS_RC_SCOM_GET_FAILED, rc);
+            break;
+        }
+    } while(0);
+
+    // send back a response, IPC success (even if ffdc/rc are non zeros)
+    rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);
     if(rc)
     {
-        PK_TRACE("gpe0:apss_continue_pwr_meas_read:getscom_reg3 failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
+        PK_TRACE("apss_continue_pwr_meas_read: Failed to send response back. Halting GPE0", rc);
+        apss_set_ffdc(&(args->error), 0x00, APSS_RC_IPC_SEND_FAILED, rc);
         pk_halt();
     }
-        
-    // send back a response, IPC success even if ffdc/rc are non zeros
-    rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);
-
-    return;
-    // halt;   // is it supposed to be treated as nop in the PPE?
-
 }
 
+/*
+ * Function Specifications:
+ *
+ * Name: apss_complete_pwr_meas_read
+ *
+ * Description:  Complete the reading of the power measurement from APSS
+ *               Read the TOD (and GPIOs)
+ *
+ * Inputs:       cmd is a pointer to IPC msg's cmd and cmd_data struct
+ *
+ * Outputs:      cmd->cmd_data->meas_data[3]:TOD
+ *               error:                      sets rc, address, and ffdc
+ *                                           in the cmd_data's GpeErrorStruct
+ *
+ * End Function Specification
+ */
+
 void apss_complete_pwr_meas_read(ipc_msg_t* cmd, void* arg)
 {
     // the ipc arguments are passed through the ipc_msg_t structure, has a pointer
@@ -221,7 +288,7 @@ void apss_complete_pwr_meas_read(ipc_msg_t* cmd, void* arg)
     int          rc;
     ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd;
     apss_complete_args_t *args = (apss_complete_args_t*)async_cmd->cmd_data;
-    
+
 
     // clear error, ffdc, and rc (feedback to 405)
     // These may be overwritten by error codes if errors occur
@@ -230,29 +297,36 @@ void apss_complete_pwr_meas_read(ipc_msg_t* cmd, void* arg)
     args->error.rc = 0;
     args->error.ffdc = 0;
 
-    // wait for ADC completion, or timeout after 100 micro seconds. 
-    // scom register SPIPSS_ADC_STATUS_REG's bit 0 (HWCTRL_ONGOING) 
-    // indicates when completion occurs.
-    rc = wait_spi_completion(args, SPIPSS_ADC_STATUS_REG, 100);
-    if(rc) // Timeout Reached, and SPI transaction didn't complete, copy returned status into rc
-           // REVIEW: Should we also copy something into the ffdc as well? whether in wait_spi_completion or here?
-    {
-        PK_TRACE("gpe0:apss_complete_pwr_meas_read:wait_spi_completion failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
-        pk_halt();
-    }
-    
-
-    rc = getscom_abs(TOD_VALUE_REG, &args->meas_data[3]);    // REVIEW: Check proper transfer to the OCC under simics
+    do {
+        // wait for ADC completion, or timeout after 100 micro seconds.
+        // scom register SPIPSS_ADC_STATUS_REG's bit 0 (HWCTRL_ONGOING)
+        // indicates when completion occurs.
+        rc = wait_spi_completion(&(args->error), SPIPSS_ADC_STATUS_REG, 100);
+        if(rc) // Timeout Reached, and SPI transaction didn't complete
+        {
+            PK_TRACE("apss_complete_pwr_meas_read:wait_spi_completion Timed out, rc = 0x%08x",
+                     rc);
+            // FFDC already set inside wait_spi_completion
+            break;
+        }
+
+        // SIMICS Verify: Check proper transfer to the OCC under simics
+        rc = getscom_abs(TOD_VALUE_REG, &args->meas_data[3]);
+        if(rc)
+        {
+            PK_TRACE("apss_complete_pwr_meas_read: TOD_VALUE_REG getscom failed. rc = 0x%08x",
+                     rc);
+            apss_set_ffdc(&(args->error), TOD_VALUE_REG, APSS_RC_SCOM_GET_FAILED, rc);
+            break;
+        }
+    } while(0);
+
+    // send back a response, IPC success (even if ffdc/rc are non zeros)
+    rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);
     if(rc)
     {
-        PK_TRACE("apss_complete_pwr_meas_read on gpe0 failed with rc = 0x%08x", rc);
-        args->error.rc = rc;
+        PK_TRACE("apss_complete_pwr_meas_read: Failed to send response back. Halting GPE0", rc);
+        apss_set_ffdc(&(args->error), 0x00, APSS_RC_IPC_SEND_FAILED, rc);
         pk_halt();
     }
-    
-    // send back a response, IPC success even if ffdc/rc are non zeros
-    rc = ipc_send_rsp(cmd, IPC_RC_SUCCESS);
-
-    return;
 }
diff --git a/src/occ_gpe0/apss_util.c b/src/occ_gpe0/apss_util.c
index 4fa586a..cf210fc 100644
--- a/src/occ_gpe0/apss_util.c
+++ b/src/occ_gpe0/apss_util.c
@@ -24,26 +24,32 @@ void apss_set_ffdc(GpeErrorStruct *o_error, uint32_t i_addr, uint32_t i_rc, uint
 
 }
 
-//--------------------------------------------------------------------
-// Name: wait_spi
-//
-// Description:  Read the specified register (SPIPSS_P2S_STATUS_REG
-//               or SPIPSS_ADC_STATUS_REG), and check if it's p2s_ongoing
-//               bit is 0 (operations done).  If not, wait
-//               up to the timeout usec (~1usec per retry).
-//               If still not clear, continue looping,
-//               If error/reserved bits are set, a return code will be sent back
-//
-// Inputs:       timeout - # usec to wait for ongoing bit to clear
-//               Register: SPIPSS_P2S_STATUS_REG or SPIPSS_ADC_STATUS_REG
-//
-// return:       0 -> Success: spi transaction completed within timeout limit
-//               not 0 -> timeout: spi transaction did not complete within timeout
-//               bits 0:7 are masked, and returned back for potential analysis
-//                   of the reason that the transaction timed out
-//--------------------------------------------------------------------
+/*
+ * Function Specification:
+ *
+ * Name: wait_spi_completion
+ *
+ * Description:  Read the specified register (SPIPSS_P2S_STATUS_REG
+ *               or SPIPSS_ADC_STATUS_REG), and check if it's p2s_ongoing
+ *               bit is 0 (operations done).  If not, wait
+ *               up to the timeout usec (~1usec per retry).
+ *               If still not clear, continue looping,
+ *               If error/reserved bits are set, a return code will be sent back
+ *
+ * Inputs:       error:    a pointer to a GpeErrorStruct, to populate rc, ffdc,
+ *                         and address, in case a scom get error happens
+ *               timeout:  # usec to wait for ongoing bit to clear
+ *               Register: SPIPSS_P2S_STATUS_REG or SPIPSS_ADC_STATUS_REG
+ *
+ * return:       0 -> Success: spi transaction completed within timeout limit
+ *               not 0 -> timeout: spi transaction did not complete within timeout
+ *                        bits 0:31 are masked, and returned back for potential
+ *                        analysis of the reason that the transaction timed out
+ *
+ * End Function Specification
+ */
 
-int wait_spi_completion(initGpioArgs_t *args, uint32_t reg, uint8_t timeout)
+int wait_spi_completion(GpeErrorStruct *error, uint32_t reg, uint8_t timeout)
 {
     int         i;
     int         rc;
@@ -53,7 +59,7 @@ int wait_spi_completion(initGpioArgs_t *args, uint32_t reg, uint8_t timeout)
     {
         PK_TRACE("gpe0:wait_spi_completion failed: Invalid Register 0x%08x", reg);
         rc = APSS_RC_INVALID_REG;
-        apss_set_ffdc((&(args->error)),reg,rc, 0x00);
+        apss_set_ffdc(error, reg, rc, 0x00);
     }
     else
     {
@@ -64,7 +70,7 @@ int wait_spi_completion(initGpioArgs_t *args, uint32_t reg, uint8_t timeout)
             if(rc)
             {
                 PK_TRACE("gpe0:wait_spi_completion failed with rc = 0x%08x", rc);
-                apss_set_ffdc(&(args->error),reg,APSS_RC_SCOM_GET_FAILED, rc);
+                apss_set_ffdc(error, reg, APSS_RC_SCOM_GET_FAILED, rc);
                 rc = APSS_RC_SCOM_GET_FAILED;
                 break;
             }
@@ -84,11 +90,11 @@ int wait_spi_completion(initGpioArgs_t *args, uint32_t reg, uint8_t timeout)
         }
     }
 
-    //Timed out waiting on P2S_ONGOING bit.
+    //Timed out waiting on P2S_ONGOING / HWCTRL_ONGOING bit.
     if (i >= timeout)
     {
         PK_TRACE("gpe0:wait_spi_completion Timed out waiting for p2s_ongoing to clear.");
-        apss_set_ffdc(&(args->error),reg,APSS_RC_SPI_TIMEOUT, rc);
+        apss_set_ffdc(error, reg, APSS_RC_SPI_TIMEOUT, rc);
         rc = APSS_RC_SPI_TIMEOUT;
     }
 
diff --git a/src/occ_gpe0/apss_util.h b/src/occ_gpe0/apss_util.h
index a3a2f26..1f7a76c 100644
--- a/src/occ_gpe0/apss_util.h
+++ b/src/occ_gpe0/apss_util.h
@@ -6,6 +6,6 @@
 
 void apss_set_ffdc(GpeErrorStruct *o_error, uint32_t i_addr, uint32_t i_rc, uint64_t i_ffdc);
 
-int wait_spi_completion(initGpioArgs_t *args, uint32_t reg, uint8_t timeout);
+int wait_spi_completion(GpeErrorStruct *error, uint32_t reg, uint8_t timeout);
 
 #endif //_APSS_UTIL_H
diff --git a/src/occ_gpe0/pore_nop.pS b/src/occ_gpe0/pore_nop.pS
deleted file mode 100755
index bbe5e25..0000000
--- a/src/occ_gpe0/pore_nop.pS
+++ /dev/null
@@ -1,61 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/occ/gpe/pore_nop.pS $
-#
-# OpenPOWER OnChipController Project
-#
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-// A No-Op Program for PORE Model Timing
-//
-// Used to generate the worst case timings for the AMEC
-// sensors.
-
-.nolist
-#include "pgp.h"
-#include "pgas.h"
-.list
-
-.oci
-
-.data
-
-.text
-
-.global GPE_pore_nop
-
-/// Run a nop instruction and then halt GPE
-GPE_pore_nop:
-    nop
-
-    // Only compile this in to test delaying PORE-GPE engine
-    .ifdef DELAY_PORE_NOP
-    li CTR, 120
-delay_loop:
-    waits    600
-    nop
-    loop    delay_loop
-done:
-    .endif
-
-    halt
-
-.epilogue GPE_pore_nop
diff --git a/src/occ_gpe0/pore_test.pS b/src/occ_gpe0/pore_test.pS
deleted file mode 100755
index 2534d4b..0000000
--- a/src/occ_gpe0/pore_test.pS
+++ /dev/null
@@ -1,84 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/occ/gpe/pore_test.pS $
-#
-# OpenPOWER OnChipController Project
-#
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-// Test Program for PORE Model
-// Delays for X (passed in) uS before halting PORE-GPE program.
-
-.nolist
-#include "pgp.h"
-#include "pgas.h"
-.list
-
-.oci
-
-// Parameter offsets
-
-.data
-
-.global jmptable
-.align     3
-jmptable:   // Error Handlers are replaced with Halts
-    .quad   0x0200000000000000    // Halt on Error 0
-    .quad   0x0000000002000000    // Halt on Error 1
-    .quad   0x0000000000000000
-    .quad   0x0200000000000000    // Halt on error 2
-    .quad   0x0000000002000000    // Halt on error 3
-    .quad   0x0000000000000000
-    .quad   0x0200000000000000    // Halt on Error 4
-    .quad   0x0000000002000000    // Halt on error 5
-    .quad   0x0000000000000000
-    .quad   0x0200000000000000    // Halt on Error 6
-    .quad   0x0000000002000000    // Halt on error 7
-    .quad   0x0000000000000000
-    .quad   0xA200000000003fff    // BRAI pore_test
-    .quad   0xc146000000000000    // second word is not used
-
-    .global scratchspace
-    .align  3
-scratchspace:
-    .quad   0x0000000000000010    // Data scratch space
-    .quad   0x0000000000000020
-    .quad   0x0000000000000030
-    .quad   0x0000000000000040
-
-.text
-
-.global pore_test
-
-pore_test:
-
-    // Read parameter into CTR
-    mr      CTR, ETR
-delay_loop:
-    waits    600
-    nop
-    loop    delay_loop
-done:
-    halt
-
-//////////////////////////////////////////////////////////////////////
-// End of Program
-//////////////////////////////////////////////////////////////////////
diff --git a/src/occ_gpe0/pore_test_error.pS b/src/occ_gpe0/pore_test_error.pS
deleted file mode 100755
index 58d7135..0000000
--- a/src/occ_gpe0/pore_test_error.pS
+++ /dev/null
@@ -1,247 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/occ/gpe/pore_test_error.pS $
-#
-# OpenPOWER OnChipController Project
-#
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-// A Test Program for PORE Modeling
-// Delays for X (passed in) uS before halting PORE-GPE
-// program.  Always sets an error.
-//
-// Input:
-//     struct {
-//         uint64_t rc;          // This should be read as 63:32=addr, 31:0=rc
-//         uint64_t ffdc;        // Whatever GPE program puts in for FFDC data
-//     } PoreGpeErrorStruct;
-//
-//     struct {
-//         PoreGpeErrorStruct error;
-//         uint32_t pore_delay;
-//     } PoreSimpleArgs;
-//
-
-//////////////////////////////////////////////////////////////////////
-// Includes
-//////////////////////////////////////////////////////////////////////
-.nolist
-#include "pgp.h"
-#include "pgas.h"
-.list
-
-//////////////////////////////////////////////////////////////////////
-// Define Address Space
-//////////////////////////////////////////////////////////////////////
-.oci
-
-//////////////////////////////////////////////////////////////////////
-// Define Symbols
-//////////////////////////////////////////////////////////////////////
-#define TOD_VALUE_REG                 0x00040020
-#define SPIPSS_REGISTER_BASE          0x00020000
-#define SPIPSS_ADC_CTRL_REG0          (SPIPSS_REGISTER_BASE + 0x00)
-#define SPIPSS_ADC_CTRL_REG1          (SPIPSS_REGISTER_BASE + 0x01)
-#define SPIPSS_ADC_CTRL_REG2          (SPIPSS_REGISTER_BASE + 0x02)
-#define SPIPSS_ADC_STATUS_REG         (SPIPSS_REGISTER_BASE + 0x03)
-#define SPIPSS_ADC_COMMAND_REG        (SPIPSS_REGISTER_BASE + 0x04)
-#define SPIPSS_ADC_WDATA_REG          (SPIPSS_REGISTER_BASE + 0x10)
-#define SPIPSS_ADC_RDATA_REG0         (SPIPSS_REGISTER_BASE + 0x20)
-#define SPIPSS_ADC_RDATA_REG1         (SPIPSS_REGISTER_BASE + 0x21)
-#define SPIPSS_ADC_RDATA_REG2         (SPIPSS_REGISTER_BASE + 0x22)
-#define SPIPSS_ADC_RDATA_REG3         (SPIPSS_REGISTER_BASE + 0x23)
-#define SPIPSS_P2S_CTRL_REG0          (SPIPSS_REGISTER_BASE + 0x40)
-#define SPIPSS_P2S_CTRL_REG1          (SPIPSS_REGISTER_BASE + 0x41)
-#define SPIPSS_P2S_CTRL_REG2          (SPIPSS_REGISTER_BASE + 0x42)
-#define SPIPSS_P2S_STATUS_REG         (SPIPSS_REGISTER_BASE + 0x43)
-#define SPIPSS_P2S_COMMAND_REG        (SPIPSS_REGISTER_BASE + 0x44)
-#define SPIPSS_P2S_WDATA_REG          (SPIPSS_REGISTER_BASE + 0x50)
-#define SPIPSS_P2S_RDATA_REG          (SPIPSS_REGISTER_BASE + 0x60)
-
-.set GPE_PROG_ID, 100
-.set GPE_ERROR_CODE, 0xAA55AA55
-.set GPE_ERROR_RC, 0xBEEFCAFE
-
-//////////////////////////////////////////////////////////////////////
-// Define Structures
-//////////////////////////////////////////////////////////////////////
-
-// Declare the offsets of the struct that will be passed to the
-// GPE program via the ETR register
-//
-// struct PoreSimpleArgs =
-// {
-.struct     0
-RETURN_CODE:
-    .struct RETURN_CODE + 8
-FFDC:
-    .struct FFDC + 8
-PORE_DELAY:
-// };
-
-//////////////////////////////////////////////////////////////////////
-// Begin Program
-//////////////////////////////////////////////////////////////////////
-
-.text
-
-//--------------------------------------------------------------------
-// Macro Specification:
-//
-// Name: _saveffdc
-//
-// Description:  Save off RC, FFDC & Address when there is an error
-//               in a GPE program.
-//
-//               - Copy D0 into PoreGpeErrorStruct->ffdc
-//               - Copy D1[63:32] into PoreGpeErrorStruct->rc[63:32]
-//               - Copy \error_code into PoreGpeErrorStruct->rc[31:0]
-//
-// Inputs:       \error_code - Unique GPE error code that will
-//                             indicate the failure mode of the GPE
-//                             program.
-//               D0          - Set to FFDC data that will be copied to
-//                             PoreGpeErrorStruct->ffdc
-//               D1          - Bits[63:32] set to address that will be
-//                             copied to PoreGpeErrorStruct->rc[63:32]
-//               ETR         - Assumed to be set to base address of
-//                             passed argument structure
-//
-// End Macro Specification
-//--------------------------------------------------------------------
-.macro _saveffdc, error_code
-
-    // Make sure passed Structure Pointer is loaded into A1
-    mr      A1, ETR
-
-    // First save off D0 into FFDC
-    std     D0, FFDC, A1
-
-    // Then save off SPRG0 into the lower 32 bits of D0
-    // TODO:  SPRG0 doesn't work in Simics....switching to D1 for now
-    mr      D0, D1
-
-    // Save off the address of the start of the GPE program into the
-    // upper 32 bits of D0
-    li      D1, \error_code
-    sldi    D1, D1, 32
-    or      D0, D0, D1
-
-    // Save register off into code_addr
-    std     D0, RETURN_CODE, A1
-
-.endm
-
-
-//--------------------------------------------------------------------
-// Macro Specification:
-//
-// Name: _getscom
-//
-// Description:  Get a SCOM based on passed in Address, put it in D0
-//
-// Inputs:       SCOM Address
-//
-// Outputs:      D0 - Result of SCOM
-//
-// End Macro Specification
-//--------------------------------------------------------------------
-.macro _getscom, address
-
-    lpcs    P0, \address
-    ld      D0, \address, P0
-
-.endm
-
-
-//--------------------------------------------------------------------
-// Macro Specification:
-//
-// Name: _putscom
-//
-// Description:  Get a SCOM based on passed in Address, put it in D0
-//
-// Inputs:       SCOM Address, Data
-//
-// Outputs:      None
-//
-// End Macro Specification
-//--------------------------------------------------------------------
-.macro _putscom, address, data
-
-    lpcs    P0, \address
-    li      D0, \data
-    std     D0, \address, P0
-
-.endm
-
-
-//--------------------------------------------------------------------
-// PORE-GPE Routine Specification:
-//
-// Name: pore_test_error
-//
-// Description:  Delays for X (passed in) uS before halting PORE-GPE
-//               routine.  Always sets the ffdc to indicate an error
-//               with a RC of 0xDEADBEEF
-//
-// Inputs:       PoreSimpleArgs - FFDC & uS to delay.
-//
-// Outputs:      None (except FFDC on failure)
-//
-// End PORE-GPE Routine Specification
-//--------------------------------------------------------------------
-.global pore_test_error
-pore_test_error:
-    // Copy passed Structure Pointer into A1
-    mr      A1, ETR
-
-    // Read pore_delay parameter into D0
-    ld      D0, PORE_DELAY, A1
-
-    // Shift Right so that we only use the upper 32 bits
-    // (not passed in as 64 bit value)
-    srdi    D0, D0, 32
-
-    // Copy pore_delay into CTR so that we can loop
-    mr      CTR, D0
-
-    // Set D0 to a value for some fake operation we are testing out
-    li      D0, GPE_ERROR_CODE
-    li      D1, GPE_ERROR_CODE
-
-    trap
-delay_loop:
-    waits    600
-    nop
-    loop    delay_loop
-    trap
-
-error:
-    _getscom TOD_VALUE_REG
-    _saveffdc 0xDEADBEEF
-
-done:
-    halt
-
-//////////////////////////////////////////////////////////////////////
-// End of Program
-//////////////////////////////////////////////////////////////////////
diff --git a/src/occ_gpe0/pore_test_pss.pS b/src/occ_gpe0/pore_test_pss.pS
deleted file mode 100755
index f49bdac..0000000
--- a/src/occ_gpe0/pore_test_pss.pS
+++ /dev/null
@@ -1,437 +0,0 @@
-# IBM_PROLOG_BEGIN_TAG
-# This is an automatically generated prolog.
-#
-# $Source: src/occ/gpe/pore_test_pss.pS $
-#
-# OpenPOWER OnChipController Project
-#
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
-# [+] International Business Machines Corp.
-#
-#
-# Licensed under the Apache License, Version 2.0 (the "License");
-# you may not use this file except in compliance with the License.
-# You may obtain a copy of the License at
-#
-# http://www.apache.org/licenses/LICENSE-2.0
-#
-# Unless required by applicable law or agreed to in writing, software
-# distributed under the License is distributed on an "AS IS" BASIS,
-# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or
-# implied. See the License for the specific language governing
-# permissions and limitations under the License.
-#
-# IBM_PROLOG_END_TAG
-
-// Input:
-//     struct {
-//         uint64_t rc;          // This should be read as 63:32=addr, 31:0=rc
-//         uint64_t ffdc;        // Whatever GPE program puts in for FFDC data
-//     } PoreGpeErrorStruct;
-//
-//     struct {
-//         PoreGpeErrorStruct error;
-//         uint64_t adc[4];
-//         uint64_t tod;
-//     } PoreSimpleArgs;
-//
-
-//////////////////////////////////////////////////////////////////////
-// Includes
-//////////////////////////////////////////////////////////////////////
-.nolist
-#include "pgp.h"
-#include "pgas.h"
-.list
-
-//////////////////////////////////////////////////////////////////////
-// Define Address Space
-//////////////////////////////////////////////////////////////////////
-.oci
-
-//////////////////////////////////////////////////////////////////////
-// Define Symbols
-//////////////////////////////////////////////////////////////////////
-#define TOD_VALUE_REG                 0x00040020
-#define SPIPSS_REGISTER_BASE          0x00020000
-#define SPIPSS_ADC_CTRL_REG0          (SPIPSS_REGISTER_BASE + 0x00)
-#define SPIPSS_ADC_CTRL_REG1          (SPIPSS_REGISTER_BASE + 0x01)
-#define SPIPSS_ADC_CTRL_REG2          (SPIPSS_REGISTER_BASE + 0x02)
-#define SPIPSS_ADC_STATUS_REG         (SPIPSS_REGISTER_BASE + 0x03)
-#define SPIPSS_ADC_COMMAND_REG        (SPIPSS_REGISTER_BASE + 0x04)
-#define SPIPSS_ADC_WDATA_REG          (SPIPSS_REGISTER_BASE + 0x10)
-#define SPIPSS_ADC_RDATA_REG0         (SPIPSS_REGISTER_BASE + 0x20)
-#define SPIPSS_ADC_RDATA_REG1         (SPIPSS_REGISTER_BASE + 0x21)
-#define SPIPSS_ADC_RDATA_REG2         (SPIPSS_REGISTER_BASE + 0x22)
-#define SPIPSS_ADC_RDATA_REG3         (SPIPSS_REGISTER_BASE + 0x23)
-#define SPIPSS_P2S_CTRL_REG0          (SPIPSS_REGISTER_BASE + 0x40)
-#define SPIPSS_P2S_CTRL_REG1          (SPIPSS_REGISTER_BASE + 0x41)
-#define SPIPSS_P2S_CTRL_REG2          (SPIPSS_REGISTER_BASE + 0x42)
-#define SPIPSS_P2S_STATUS_REG         (SPIPSS_REGISTER_BASE + 0x43)
-#define SPIPSS_P2S_COMMAND_REG        (SPIPSS_REGISTER_BASE + 0x44)
-#define SPIPSS_P2S_WDATA_REG          (SPIPSS_REGISTER_BASE + 0x50)
-#define SPIPSS_P2S_RDATA_REG          (SPIPSS_REGISTER_BASE + 0x60)
-
-#define GPE_PROG_ID 0xDEAD
-
-#define GPE_ERROR_P2S_ONGOING_TIMEOUT 0x0001
-#define GPE_ERROR_PIB_TIMEOUT         0xFF00
-
-.set GPE_ERROR_CODE, 0xAA55AA55
-.set GPE_ERROR_RC, 0xBEEFCAFE
-
-//////////////////////////////////////////////////////////////////////
-// Define Structures
-//////////////////////////////////////////////////////////////////////
-
-// Declare the offsets of the struct that will be passed to the
-// GPE program via the ETR register
-//
-// struct PoreSimpleArgs =
-// {
-.struct     0
-RETURN_CODE:
-    .struct RETURN_CODE + 8
-FFDC:
-    .struct FFDC + 8
-ADC0:
-    .struct ADC0 + 8
-ADC1:
-    .struct ADC1 + 8
-ADC2:
-    .struct ADC2 + 8
-ADC3:
-    .struct ADC3 + 8
-TOD:
-// };
-
-//////////////////////////////////////////////////////////////////////
-// Begin Program
-//////////////////////////////////////////////////////////////////////
-
-.text
-
-//--------------------------------------------------------------------
-// Macro Specification:
-//
-// Name: _saveffdc
-//
-// Description:  Save off RC, FFDC & Address when there is an error
-//               in a GPE program.
-//
-//               - Copy D0 into PoreGpeErrorStruct->ffdc
-//               - Copy D1[63:32] into PoreGpeErrorStruct->rc[63:32]
-//               - Copy \error_code into PoreGpeErrorStruct->rc[31:0]
-//
-// Inputs:       \error_code - Unique GPE error code that will
-//                             indicate the failure mode of the GPE
-//                             program.
-//               D0          - Set to FFDC data that will be copied to
-//                             PoreGpeErrorStruct->ffdc
-//               D1          - Bits[63:32] set to address that will be
-//                             copied to PoreGpeErrorStruct->rc[63:32]
-//               ETR         - Assumed to be set to base address of
-//                             passed argument structure
-//
-// End Macro Specification
-//--------------------------------------------------------------------
-.macro _saveffdc, error_code
-    // Make sure passed Structure Pointer is loaded into A1
-    mr      A1, ETR
-
-// TODO Follow up on Simics SPRG0 support
-//.ifdef  SIMICS_SPRG0_WORKING
-// Copy D1[32:63] into SPRG0
-    mr      D1, SPRG0
-
-    // Now Read RETURN_CODE into D1, check to see if it is 0
-    ld      D1, RETURN_CODE, A1
-
-    // If it is not 0, then don't save off any FFDC
-    branz   D1, 1f
-//.endif
-
-    // Copy SPRG0 into D1[32:63]
-    mr      SPRG0, D1
-
-    // First save off D0 into FFDC
-    std     D0, FFDC, A1
-
-    // Then save off D1[32:63] into the lower 32 bits [32:63] of D0
-    mr      D0, D1
-
-    // Save off the passed \error_code into the upper 32 bits of D0
-    li      D1, \error_code
-    sldi    D1, D1, 32
-    or      D0, D0, D1
-
-    // Save register off into code_addr
-    std     D0, RETURN_CODE, A1
-1:
-.endm
-
-//--------------------------------------------------------------------
-// Macro Specification:
-//
-// Name: _saveffdc3
-//
-// Description:  Get a SCOM based on passed in Address, put it in D0
-//
-// Inputs:       SCOM Address
-//
-// Outputs:      D0 - Result of SCOM
-//
-// End Macro Specification
-//--------------------------------------------------------------------
-.macro _saveffdc3, gpe_id, error_code
-
-    // This will cause an "Invalid Instruction Code" Error in the PORE-GPE
-    // which will cause an "error event 2" interrupt to the PPC405
-    .long 0xAABBCCDD
-
-    // The PPC405 will then be able to read the "Invalid Instruction Code"
-    // out of the IBUF_01 Register, which will contain the AABBCCDD opcode
-    // as well as the \gpe_id and \error_code.
-    .short \gpe_id
-    .short \error_code
-
-    // The PPC405 ISR will then grab & place into PoreRequestStruct:
-    // IBUF_01[32:63] (32b)
-    // DBG0           (64b)
-    // DBG1           (64b)
-    // D0             (64b)
-    // D1[32:63]      (32b)
-    // A0 & A1        (64b)
-    // --------       -----
-    // Total          40 Bytes
-.endm
-
-
-
-//--------------------------------------------------------------------
-// Macro Specification:
-//
-// Name: _getscom
-//
-// Description:  Get a SCOM based on passed in Address, put it in D0
-//
-// Inputs:       SCOM Address
-//
-// Outputs:      D0 - Result of SCOM
-//
-// End Macro Specification
-//--------------------------------------------------------------------
-.macro _getscom, address
-
-    lpcs    P0, \address
-    ld      D0, \address, P0
-
-.endm
-
-//--------------------------------------------------------------------
-// Macro Specification:
-//
-// Name: _putscom
-//
-// Description:  Put Data in a SCOM address
-//
-// Inputs:       SCOM Address, Data
-//
-// Outputs:      None
-//
-// End Macro Specification
-//--------------------------------------------------------------------
-.macro _putscom, address, data
-
-    lpcs    P0, \address
-    li      D0, \data
-    std     D0, \address, P0
-
-.endm
-
-//--------------------------------------------------------------------
-// Macro Specification:
-//
-// Name: _spin_on_bitclear_scom
-//
-// Description:  Wait for Bit to get cleared in scom register
-//
-// Inputs:       SCOM Address, Mask
-//
-// Outputs:      None
-//
-// End Macro Specification
-//--------------------------------------------------------------------
-.macro _spin_on_bitclear_scom, address, mask
-1:
-    _getscom  \address
-    andi      D0, D0, \mask
-    branz     D0, 1b
-
-.endm
-
-//--------------------------------------------------------------------
-// PORE-GPE Routine Specification:
-//
-// Name: pore_test_pss
-//
-// Description:  Delays for X (passed in) uS before halting PORE-GPE
-//               routine.  Always sets the ffdc to indicate an error
-//               with a RC of 0xDEADBEEF
-//
-// Inputs:       PoreSimpleArgs - FFDC & uS to delay.
-//
-// Outputs:      None (except FFDC on failure)
-//
-// End PORE-GPE Routine Specification
-//--------------------------------------------------------------------
-.global pore_test_pss
-pore_test_pss:
-    // Copy passed Structure Pointer into A1
-    mr      A1, ETR
-
-    trap
-
-.ifdef APSS_MODEL_INCLUDED
-    _spin_on_bitclear_scom SPIPSS_P2S_STATUS_REG 0x8000000000000000
-    _spin_on_bitclear_scom SPIPSS_P2S_STATUS_REG 0x8000000000000000
-.endif
-
-    trap
-    _getscom 0x01000000
-
-.ifdef APSS_MODEL_INCLUDED
-    //////////////////////////////////////////////////
-    // Test out a Auto-2 Mode Setup
-    //////////////////////////////////////////////////
-    _putscom SPIPSS_P2S_CTRL_REG0,    0x410FC00004000000
-    _putscom SPIPSS_P2S_CTRL_REG1,    0x001C000000000000
-    _putscom SPIPSS_P2S_CTRL_REG2,    0x000C800000000000
-    _putscom SPIPSS_P2S_WDATA_REG,    0x3FC0000000000000
-    _putscom SPIPSS_P2S_COMMAND_REG,  0x8000000000000000
-    waits 4000
-    _getscom SPIPSS_P2S_RDATA_REG
-    trap
-.endif
-
-.ifdef APSS_MODEL_INCLUDED
-    //////////////////////////////////////////////////
-    // Test out a GPIO Mode Setup - all High-Z
-    //////////////////////////////////////////////////
-    _putscom SPIPSS_P2S_CTRL_REG0,    0x410FC00004000000
-    _putscom SPIPSS_P2S_CTRL_REG2,    0x000C800000000000
-    _putscom SPIPSS_P2S_WDATA_REG,    0x50FF000000000000
-    _putscom SPIPSS_P2S_COMMAND_REG,  0x8000000000000000
-    waits 4000
-    _getscom SPIPSS_P2S_RDATA_REG
-    trap
-.endif
-
-.ifdef APSS_MODEL_INCLUDED
-    //////////////////////////////////////////////////
-    // Test out ADC FSM
-    //////////////////////////////////////////////////
-    _putscom SPIPSS_ADC_CTRL_REG0,    0x4100100000000000
-    _putscom SPIPSS_ADC_CTRL_REG1,    0x801FC00000000000
-    _putscom SPIPSS_ADC_CTRL_REG2,    0x0019000000000000
-    _putscom SPIPSS_ADC_WDATA_REG,    0x0000000000000000
-    _putscom SPIPSS_ADC_COMMAND_REG,  0x8000000000000000
-    waits 30000
-    _getscom SPIPSS_ADC_RDATA_REG0
-    std     D0, ADC0, A1
-    _getscom SPIPSS_ADC_RDATA_REG1
-    std     D0, ADC1, A1
-    _getscom SPIPSS_ADC_RDATA_REG2
-    std     D0, ADC2, A1
-    _getscom SPIPSS_ADC_RDATA_REG3
-    std     D0, ADC3, A1
-    _getscom TOD_VALUE_REG
-    std     D0, TOD, A1
-    trap
-.endif
-
-.ifdef APSS_MODEL_INCLUDED
-    //////////////////////////////////////////////////
-    // Test out a GPIO Port 0 Read from APSS
-    //////////////////////////////////////////////////
-    _putscom SPIPSS_P2S_CTRL_REG0,    0x410FC00004000000
-    _putscom SPIPSS_P2S_CTRL_REG1,    0x001C400000000000
-    _putscom SPIPSS_P2S_CTRL_REG2,    0x000C800000000000
-    _putscom SPIPSS_P2S_WDATA_REG,    0x7000000000000000
-    _putscom SPIPSS_P2S_COMMAND_REG,  0x8000000000000000
-    waits 4000
-    _getscom SPIPSS_P2S_RDATA_REG
-    trap
-.endif
-
-.ifdef DPSS_MODEL_INCLUDED
-    //////////////////////////////////////////////////
-    // Test out a Fan RPM 7 Read from DPSS
-    //////////////////////////////////////////////////
-    _putscom SPIPSS_P2S_CTRL_REG0,    0x410FC00004000000
-    _putscom SPIPSS_P2S_CTRL_REG1,    0x401C400000000000
-    _putscom SPIPSS_P2S_CTRL_REG2,    0x000C800000000000
-    _putscom SPIPSS_P2S_WDATA_REG,    0x3200000000000000
-    _putscom SPIPSS_P2S_COMMAND_REG,  0x8000000000000000
-    waits 4000
-    _getscom SPIPSS_P2S_RDATA_REG
-    trap
-.endif
-
-.ifdef DPSS_MODEL_INCLUDED
-.print "Building in DPSS Support"
-    //////////////////////////////////////////////////
-    // Test out a Stream of commands to the DPSS
-    //////////////////////////////////////////////////
-
-    // Send First(32) & Second(33) command
-    // Get Response to First command
-    _putscom SPIPSS_P2S_CTRL_REG0,    0x4104004004000000
-    _putscom SPIPSS_P2S_CTRL_REG1,    0xC01C400000000000
-    _putscom SPIPSS_P2S_CTRL_REG2,    0x000C800000000000
-    _putscom SPIPSS_P2S_WDATA_REG,    0x2B002C0000000000
-    _putscom SPIPSS_P2S_COMMAND_REG,  0x8000000000000000
-    waits 4000
-    _spin_on_bitclear_scom SPIPSS_P2S_STATUS_REG 0x8000000000000000
-    _getscom SPIPSS_P2S_RDATA_REG
-    trap
-
-    // Send Third (34)& Forth (35) Command
-    // Get Response to Second & third
-    _putscom SPIPSS_P2S_CTRL_REG0,    0x4100104004000000
-    _putscom SPIPSS_P2S_CTRL_REG1,    0xC01C400000000000
-    _putscom SPIPSS_P2S_CTRL_REG2,    0x000C800000000000
-    _putscom SPIPSS_P2S_WDATA_REG,    0x2D002E0000000000
-    _putscom SPIPSS_P2S_COMMAND_REG,  0x8000000000000000
-    waits 4000
-    _getscom SPIPSS_P2S_RDATA_REG
-    trap
-    _spin_on_bitclear_scom SPIPSS_P2S_STATUS_REG 0x8000000000000000
-
-    // Send Fifth (36)& Last (00) Command
-    // Get Response to Forth & Fifth
-    _putscom SPIPSS_P2S_CTRL_REG0,    0x4100104004000000
-    _putscom SPIPSS_P2S_CTRL_REG1,    0xC01C400000000000
-    _putscom SPIPSS_P2S_CTRL_REG2,    0x000C800000000000
-    _putscom SPIPSS_P2S_WDATA_REG,    0x2F00000000000000
-    _putscom SPIPSS_P2S_COMMAND_REG,  0x8000000000000000
-    waits 4000
-    _getscom SPIPSS_P2S_RDATA_REG
-    trap
-    _spin_on_bitclear_scom SPIPSS_P2S_STATUS_REG 0x8000000000000000
-    trap
-
-    _saveffdc3 GPE_PROG_ID GPE_ERROR_P2S_ONGOING_TIMEOUT
-.endif
-    bra done
-
-error:
-    _saveffdc 0xDEADBEEF
-
-done:
-    halt
-
-//////////////////////////////////////////////////////////////////////
-// End of Program
-//////////////////////////////////////////////////////////////////////
diff --git a/src/occ_gpe0/pss_macros.h b/src/occ_gpe0/pss_macros.h
deleted file mode 100755
index 8cbcf0b..0000000
--- a/src/occ_gpe0/pss_macros.h
+++ /dev/null
@@ -1,162 +0,0 @@
-/* IBM_PROLOG_BEGIN_TAG                                                   */
-/* This is an automatically generated prolog.                             */
-/*                                                                        */
-/* $Source: src/occ_405/gpe/pss_macros.h $                                */
-/*                                                                        */
-/* OpenPOWER OnChipController Project                                     */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2011,2015                        */
-/* [+] International Business Machines Corp.                              */
-/*                                                                        */
-/*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
-/*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
-/*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
-/*                                                                        */
-/* IBM_PROLOG_END_TAG                                                     */
-
-#ifndef _PSS_MACROS_H
-#define _PSS_MACROS_H
-
-//--------------------------------------------------------------------
-// Name: _wait_for_spi_ops_complete (MACRO)
-//
-// Description:  Read SPIPSS_P2S_STATUS_REG and check if p2s_ongoing
-//               bit is 0 (operations done).  If not, wait
-//               up to timeout usec (~1usec per retry).
-//               If still not clear, branch to timeout_label
-//               If error/reserved bits are set, a branch will be
-//               done to label: "error_status_reg"
-//
-// Inputs:       timeout - # usec to wait for ongoing bit to clear
-//               timeout_label - label to branch to after timeout
-//
-// Outputs:      None (on error, D0 will contain status register)
-//
-// Modifies:     CTR, D0, D1
-//--------------------------------------------------------------------
-.macro _wait_for_spi_ops_complete, timeout, timeout_label
-    _wait_for_ops_complete SPIPSS_P2S_STATUS_REG, \timeout, \timeout_label
-.endm
-
-
-//--------------------------------------------------------------------
-// Name: _wait_for_adc_ops_complete (MACRO)
-//
-// Description:  Read SPIPSS_ADC_STATUS_REG and check if adc_ongoing
-//               bit is 0 (operations done).  If not, wait
-//               up to timeout usec (~1usec per retry).
-//               If still not clear, branch to timeout_label
-//               If error/reserved bits are set, a branch will be
-//               done to label: "error_status_reg"
-//
-// Inputs:       timeout - # usec to wait for ongoing bit to clear
-//               timeout_label - label to branch to after timeout
-//
-// Outputs:      None (on error, D0 will contain status register)
-//
-// Modifies:     CTR, D0, D1
-//--------------------------------------------------------------------
-.macro _wait_for_adc_ops_complete, timeout, timeout_label
-    _wait_for_ops_complete SPIPSS_ADC_STATUS_REG, \timeout, \timeout_label
-.endm
-
-
-//--------------------------------------------------------------------
-// Name: _wait_for_ops_complete (MACRO)
-//
-// Description:  Read specified register and check if ongoing bit (MSB)
-//               is 0 (operations done).  If not, wait
-//               up to timeout usec (~1usec per retry).
-//               If still not clear, branch to timeout_label
-//               If error/reserved bits are set, a branch will be
-//               done to label: "error_status_reg"
-//
-// Inputs:       register - SCOM register to read for ongong bit
-//               timeout - # usec to wait for ongoing bit to clear
-//               timeout_label - label to branch to after timeout
-//
-// Outputs:      None (on error, D0 will contain status register)
-//
-// Modifies:     CTR, D0, D1
-//--------------------------------------------------------------------
-.macro _wait_for_ops_complete, register, timeout, timeout_label
-    // Load CTR with approximate timeout value (1usec delay per retry)
-    li CTR, (\timeout - 1)
-1:
-    // Read spiadc_p2s_ongoing bit into D0
-    _getscom \register
-
-    // Don't fail on these status bits being set.  Only fail if we get back invalid power data
-    // Verify other error bits are not set
-    // andi    D1, D0, 0x7FFFFFFFFFFFFFFF
-    // branz   D1, error_statusreg
-
-    // Operation finished? (spiadc_p2s_ongoing = 0)
-    andi    D1, D0, 0x8000000000000000
-    braz    D1, 2f
-
-    // no, wait 1usec and retry
-    waits (1 * MICROSECONDS)
-    loop     1b
-
-    // Timeout waiting for spiadc_p2s_ongoing
-    bra     \timeout_label
-2:
-.endm
-
-
-// TODO Clean this up if it isn't required
-#if 0
-//--------------------------------------------------------------------
-// Name: sub_wait_for_spi_ops_complete (SUBROUTINE)
-//
-// Description:  Read SPIPSS_P2S_STATUS_REG and check if p2s_ongoing
-//               bit is 0 (operations done).  If not it will wait
-//               for 9 additional retries (~10usec).  If still not
-//               done, a branch will be done to timeout code.
-//               If error/reserved bits are set, a branch will be
-//               done to error_status_reg.
-//
-// Inputs:       None
-//
-// Outputs:      None (on error, D0 will contain status register)
-//
-// Modifies:     CTR, D0, D1
-//--------------------------------------------------------------------
-sub_wait_for_spi_ops_complete:
-    // Wait up to 10usec
-    li CTR, 10
-
-read_status:
-         // Read spiadc_p2s_ongoing bit into D0
-    _getscom SPIPSS_P2S_STATUS_REG
-
-    // Verify other error bits are not set
-    andi    D1, D0, 0x7FFFFFFFFFFFFFFF
-    branz   D1, error_statusreg
-
-    // Ready to send command? (spiadc_p2s_ongoing = 0)
-    andi    D1, D0, 0x8000000000000000
-    braz    D1, ops_are_complete
-
-    // no, wait 1usec and retry
-    waits (1 * MICROSECONDS)
-    loop     read_status
-
-    // Timeout waiting for spiadc_p2s_ongoing
-    bra     error_timeout
-ops_are_complete:
-    ret
-#endif
-
-#endif  //_PSS_MACROS_H
-