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authorDoug Gilbert <dgilbert@us.ibm.com>2017-09-20 14:56:59 -0500
committerWilliam A. Bryan <wilbryan@us.ibm.com>2017-10-10 13:02:41 -0400
commit9c63762e00a20f22fc8a4509071d90786513e16a (patch)
tree5e2484abcfeae088d6b20f562535881978800d5e /src/occ_405
parentba4e81e804275ced6c1793f818e5fc1fd8d1ecae (diff)
downloadtalos-occ-9c63762e00a20f22fc8a4509071d90786513e16a.tar.gz
talos-occ-9c63762e00a20f22fc8a4509071d90786513e16a.zip
Enable hardware GPU power brake
Change-Id: I39ae6205cef6ae06cacc0eb2c8a0a4288b8081c8 RTC: 179617 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/46800 Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com> Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_405')
-rwxr-xr-xsrc/occ_405/gpu/gpu.c66
-rwxr-xr-xsrc/occ_405/gpu/gpu_service_codes.h1
2 files changed, 67 insertions, 0 deletions
diff --git a/src/occ_405/gpu/gpu.c b/src/occ_405/gpu/gpu.c
index 1a27565..0be5c9f 100755
--- a/src/occ_405/gpu/gpu.c
+++ b/src/occ_405/gpu/gpu.c
@@ -81,9 +81,11 @@ uint32_t G_gpu_reset_cause = 0;
// GPE Requests
GpeRequest G_gpu_op_request;
+GpeRequest G_gpu_init_request;
// GPE arguments
GPE_BUFFER(gpu_sm_args_t G_gpu_op_req_args);
+GPE_BUFFER(gpu_init_args_t G_gpu_init_args);
gpu_sm_args_t G_new_gpu_req_args = {{{{0}}}};
@@ -444,6 +446,49 @@ void disable_all_gpus(void)
}
}
+
+// schedule request to init gpu info on gpe1
+void schedule_gpe_gpu_init_req()
+{
+ errlHndl_t err = NULL;
+ int rc = 0;
+
+ memset(&G_gpu_init_args, 0, sizeof(G_gpu_init_args));
+ // Need to add gpu i2c info
+ // G_gpu_init_args.gpu_i2c
+
+
+ rc = gpe_request_schedule(&G_gpu_init_request);
+ if (rc)
+ {
+ INTR_TRAC_ERR
+ ("schedule_gpe_gpu_init_req: gpe gpu init schedule failed w/rc=0x%08X", rc);
+ /*
+ * @errortype
+ * @moduleid GPU_MID_GPE_GPU_INIT_SCHED_REQ
+ * @reasoncode SSX_GENERIC_FAILURE
+ * @userdata1 GPE schedule returned code
+ * @userdata4 ERC_GPU_SCHEDULE_FAILURE
+ * @devdesc Failed to schedule GPE GPU initial request
+ */
+ err = createErrl(GPU_MID_GPE_GPU_INIT_SCHED_REQ,
+ SSX_GENERIC_FAILURE,
+ ERC_GPU_SCHEDULE_FAILURE,
+ ERRL_SEV_PREDICTIVE,
+ NULL,
+ DEFAULT_TRACE_SIZE,
+ rc,
+ 0);
+ commitErrl(&err);
+
+ // release I2C lock to the host for this engine and stop monitoring
+ occ_i2c_lock_release(GPU_I2C_ENGINE);
+ G_gpu_monitoring_allowed = FALSE;
+ }
+
+}
+
+
// Create GPU IPC requests
void gpu_ipc_init()
{
@@ -467,6 +512,22 @@ void gpu_ipc_init()
TRAC_ERR("gpu_ipc_init: Failed to create GPE1 IPC request for GPU op req (rc=%d)", rc);
break;
}
+
+ // Initialize GPU support on GPE1
+ GPU_DBG("gpu_ipc_init: Creating GPE1 IPC request for GPU initialization");
+ rc = gpe_request_create(&G_gpu_init_request,
+ &G_async_gpe_queue1,
+ IPC_ST_GPE_GPU_INIT_FUNCID,
+ &G_gpu_init_args,
+ SSX_WAIT_FOREVER,
+ NULL, // no callback
+ NULL, // no args
+ ASYNC_CALLBACK_IMMEDIATE);
+ if (rc)
+ {
+ TRAC_ERR("gpu_ipc_init: Failed to create GPE1 GPU init request. (rc=%d)", rc);
+ break;
+ }
}
while(0);
@@ -495,6 +556,11 @@ void gpu_ipc_init()
occ_i2c_lock_release(GPU_I2C_ENGINE);
G_gpu_monitoring_allowed = FALSE;
}
+ else
+ {
+ // gpe gpu init only needs to be done once, so do it here.
+ schedule_gpe_gpu_init_req();
+ }
}
// Called after a failure reading core temp for a specified GPU. The error will
diff --git a/src/occ_405/gpu/gpu_service_codes.h b/src/occ_405/gpu/gpu_service_codes.h
index 4ea7c6f..bf69cff 100755
--- a/src/occ_405/gpu/gpu_service_codes.h
+++ b/src/occ_405/gpu/gpu_service_codes.h
@@ -42,6 +42,7 @@ enum gpuModuleId
GPU_MID_GPU_CHECK_DRIVER_LOADED = GPU_COMP_ID | 0x09,
GPU_MID_GPU_READ_PWR_LIMIT = GPU_COMP_ID | 0x0A,
GPU_MID_GPU_SET_PWR_LIMIT = GPU_COMP_ID | 0x0B,
+ GPU_MID_GPE_GPU_INIT_SCHED_REQ = GPU_COMP_ID | 0x0C,
};
#endif /* #ifndef _GPU_SERVICE_CODES_H_ */
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