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| author | William Bryan <wilbryan@us.ibm.com> | 2018-01-03 12:30:29 -0600 |
|---|---|---|
| committer | William A. Bryan <wilbryan@us.ibm.com> | 2018-03-27 11:57:42 -0400 |
| commit | bd605ba0a030b3490f0edebd8fb704722b6eab0d (patch) | |
| tree | 34fc7b10f06fef7baf9d101f78b816a6129753d8 /src/occ_405/rtls | |
| parent | c8538f3c894d5f28f688f7a081507c3ef14d6c24 (diff) | |
| download | talos-occ-bd605ba0a030b3490f0edebd8fb704722b6eab0d.tar.gz talos-occ-bd605ba0a030b3490f0edebd8fb704722b6eab0d.zip | |
Memory Throttle Sensors
RTC:131184
Change-Id: I2582a1eb9d599f700182f17047cc95accad03725
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51407
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_405/rtls')
| -rwxr-xr-x | src/occ_405/rtls/rtls_tables.c | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/src/occ_405/rtls/rtls_tables.c b/src/occ_405/rtls/rtls_tables.c index 9d1f18e..5c880e9 100755 --- a/src/occ_405/rtls/rtls_tables.c +++ b/src/occ_405/rtls/rtls_tables.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER OnChipController Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2017 */ +/* Contributors Listed Below - COPYRIGHT 2011,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -143,6 +143,7 @@ const uint8_t G_tick0_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_POKE_WDT, TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -190,6 +191,7 @@ const uint8_t G_tick2_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_POKE_WDT, TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -213,6 +215,7 @@ const uint8_t G_tick3_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_POKE_WDT, TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -237,6 +240,7 @@ const uint8_t G_tick4_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_POKE_WDT, TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -284,6 +288,7 @@ const uint8_t G_tick6_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_POKE_WDT, TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -306,6 +311,7 @@ const uint8_t G_tick7_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_POKE_WDT, TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -330,6 +336,7 @@ const uint8_t G_tick8_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_POKE_WDT, TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -377,6 +384,7 @@ const uint8_t G_tick10_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_POKE_WDT, TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -399,6 +407,7 @@ const uint8_t G_tick11_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_POKE_WDT, TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -423,6 +432,7 @@ const uint8_t G_tick12_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_POKE_WDT, TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -470,6 +480,7 @@ const uint8_t G_tick14_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_POKE_WDT, TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, @@ -492,6 +503,7 @@ const uint8_t G_tick15_seq[] = { TASK_ID_MEMORY_CONTROL, TASK_ID_CORE_DATA_CONTROL, TASK_ID_24X7, + TASK_ID_POKE_WDT, TASK_ID_GPE_TIMINGS, TASK_ID_DCOM_WAIT_4_MSTR, TASK_ID_DCOM_RX_INBX, |
