Support for PGPE error handling

Change-Id: I979f699eb9f72c0a4087e5f5af533ee3d221a4c5
RTC: 197062
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/68569
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: AMIT J. TENDOLKAR <amit.tendolkar@in.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>

2 files changed, 13 insertions, 2 deletions

diff --git a/src/occ_405/errl/errl.c b/src/occ_405/errl/errl.c
index 9f659d1..e40a9c6 100755
--- a/src/occ_405/errl/errl.c
+++ b/src/occ_405/errl/errl.c
@@ -64,6 +64,9 @@ errlHndl_t  G_occErrSlots[ERRL_MAX_SLOTS] = {
                 (errlHndl_t) G_callslot
                 };
 
+hcode_elog_entry_t *G_hcode_elog_table = NULL;
+uint32_t            G_hcode_elog_table_slots = 0;
+
 // Array of error counters that are only cleared on OCC reset
 uint8_t G_error_history[ERR_HISTORY_SIZE] = {0};
 
@@ -749,9 +752,9 @@ void reportErrorLog( errlHndl_t i_err, uint16_t i_entrySize )
     // Defer the interrupt if FIR collection is required
     if (!G_fir_collection_required)
     {
-        // If this system is using PSIHB complex, send an interrupt to Host so that
+        // If this system is not FSP, send an interrupt to Host so that
         // Host can inform HTMGT to collect the error log
-        if (G_occ_interrupt_type == PSIHB_INTERRUPT)
+        if (G_occ_interrupt_type != FSP_SUPPORTED_OCC)
         {
             notify_host(INTR_REASON_HTMGT_SERVICE_REQUIRED);
         }
diff --git a/src/occ_405/errl/errl.h b/src/occ_405/errl/errl.h
index 183b35d..e249ef0 100755
--- a/src/occ_405/errl/errl.h
+++ b/src/occ_405/errl/errl.h
@@ -28,6 +28,7 @@
 
 #include <occ_common.h>
 #include <trac_interface.h>
+#include <pstate_pgpe_occ_api.h>
 
 // Used as default for invalid slot number
 static const uint8_t  ERRL_INVALID_SLOT = 0xFF;
@@ -127,6 +128,7 @@ typedef enum
     ERRL_USR_DTL_HISTORY_DATA   = 0x04,
     ERRL_USR_DTL_WOF_DATA       = 0x05,
     ERRL_USR_DTL_PGPE_PK_TRACE  = 0x06,
+    ERRL_USR_DTL_PGPE_DATA      = 0x07,
 } ERRL_USR_DETAIL_TYPE;
 
 // These are the possible OCC States.
@@ -283,6 +285,12 @@ extern uint8_t      G_occErrIdCounter;
 
 extern errlHndl_t   G_occErrSlots[ERRL_MAX_SLOTS];
 
+// Shared SRAM offset to access the HCODE Error Log Table
+#define HCODE_ELOG_TABLE_SRAM_OFFSET     0x40
+#define HCODE_ELOG_TABLE_MAGIC_NUMBER    0x454C5443   // "ELTC"
+extern hcode_elog_entry_t *G_hcode_elog_table;
+extern uint32_t            G_hcode_elog_table_slots;
+
 typedef enum {
     ERRH_AVSBUS_VDD_CURRENT          =  0x01,
     ERRH_AVSBUS_VDD_VOLTAGE          =  0x02,