Handle PGPE timeouts as workaround for prolonged droop events

Add "CLIP" information to poll response

Fix incorrectly throttling due to power when all cores are in stop 2 or greater

Change-Id: I502cc65ad8c4cffd7f9a1442fd4de185f3cac6e2
RTC: 183700
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51741
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>

1 files changed, 28 insertions, 0 deletions

diff --git a/src/occ_405/common.c b/src/occ_405/common.c
index fd031e2..e7eb6d7 100755
--- a/src/occ_405/common.c
+++ b/src/occ_405/common.c
@@ -246,4 +246,32 @@ bool notify_host(const ext_intr_reason_t i_reason)
     return notify_success;
 }
 
+// Called prior to logging any error related to the PGPE or Pstate control
+// i.e. PGPE communication, maintaining power cap...
+// During prolonged droop events the PGPE can be non-responsive and don't have frequency control so doing a pm reset will
+// not help.  The PGPE will set a bit in the OCC FLAGS register to indicate when in this condition for the OCC to ignore errors
+// Returns true if the error should be ignored
+bool ignore_pgpe_error(void)
+{
+    static bool  L_last_ignore_error = false;
+           bool  l_ignore_error      = false;
+           ocb_occflg_t occ_flags    = {0};
+
+    // Check if the bit to ignore errors is set in the OCC Flags register
+    occ_flags.value = in32(OCB_OCCFLG);
+
+    if (occ_flags.fields.pm_reset_suppress == 1)
+    {
+        l_ignore_error = true;
+    }
+
+    // Trace if this is a change from the last time this was called
+    if (L_last_ignore_error != l_ignore_error)
+    {
+        TRAC_ERR("ignore_pgpe_error: OCCFLG pm_reset_suppress was %d and is now %d", L_last_ignore_error, l_ignore_error);
+        L_last_ignore_error = l_ignore_error;
+    }
+
+    return l_ignore_error;
+}