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authorWael El-Essawy <welessa@us.ibm.com>2016-05-02 22:20:14 -0500
committerWael El-Essawy <welessa@us.ibm.com>2016-05-25 16:19:23 -0400
commit6d29cab23da5bacaf0772bb8dd6265c4b442760c (patch)
treed7dee4b726108c87734bd1508abccf47d1a230e4 /src/occ_405/cent
parent6f82299cb1e306dabef5bbae1a9d4e5817dbcea9 (diff)
downloadtalos-occ-6d29cab23da5bacaf0772bb8dd6265c4b442760c.tar.gz
talos-occ-6d29cab23da5bacaf0772bb8dd6265c4b442760c.zip
Pstate Infrastructure & Support config data required for active state
- Support all config data required for active state. - Set 'active ready' bit in poll response when all config data has been received. - Rewrite & rename proc_gpsm_pstate_initialize() - Delete GPSM, doesn't exist. - Put in TODO call PGPE to enable pstates this will also be telling PGPE how to set PMCR mode register (OCC control pstates or OPAL). - Initialize globals for fmax, fmin, pmax and mhz_per_pstate with temporary hard codes until PGPE is available. - Call to "proc_pstate_initialize()" moved to state transition to observation - Cleanup proc_freq2pstate() - rewrite amec_slv_freq_smh() - the calls to proc_set_core_bounds() and proc_set_core_pstate() will be replaced with 1 IPC call to the PGPE to set pmin/pmax given all cores or set pstate for all given cores. - Remove all DCM related code. Change-Id: I449d188b2cffc345afca19717dcbea037f159114 RTC:130224 RTC:150935 Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/23977 Tested-by: FSP CI Jenkins Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Diffstat (limited to 'src/occ_405/cent')
-rwxr-xr-xsrc/occ_405/cent/centaur_control.c10
1 files changed, 4 insertions, 6 deletions
diff --git a/src/occ_405/cent/centaur_control.c b/src/occ_405/cent/centaur_control.c
index 801bd04..82fddc9 100755
--- a/src/occ_405/cent/centaur_control.c
+++ b/src/occ_405/cent/centaur_control.c
@@ -179,8 +179,8 @@ void cent_update_nlimits(uint32_t i_cent)
&G_sysConfigData.mem_throt_limits[i_cent][1];
//Minimum N value is not state dependent
- l_active_limits01->min_n_per_mba = l_state_limits01->min_ot_n_per_mba;
- l_active_limits23->min_n_per_mba = l_state_limits23->min_ot_n_per_mba;
+ l_active_limits01->min_n_per_mba = l_state_limits01->min_n_per_mba;
+ l_active_limits23->min_n_per_mba = l_state_limits23->min_n_per_mba;
//oversubscription?
if(AMEC_INTF_GET_OVERSUBSCRIPTION())
@@ -199,10 +199,8 @@ void cent_update_nlimits(uint32_t i_cent)
}
else //DPS, TURBO, FFO, and SPS modes will use these settings
{
- l_mba01_mba_maxn = l_state_limits01->turbo_n_per_mba;
- l_mba01_chip_maxn = l_state_limits01->turbo_n_per_chip;
- l_mba23_mba_maxn = l_state_limits23->turbo_n_per_mba;
- l_mba23_chip_maxn = l_state_limits23->turbo_n_per_chip;
+ l_mba01_mba_maxn = l_state_limits01->pcap1_n_per_mba;
+ l_mba23_mba_maxn = l_state_limits23->pcap1_n_per_mba;
}
l_active_limits01->max_n_per_chip = l_mba01_chip_maxn;
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