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| author | Wael El-Essawy <welessa@us.ibm.com> | 2017-03-22 10:30:48 -0500 |
|---|---|---|
| committer | Wael El-Essawy <welessa@us.ibm.com> | 2017-05-10 13:53:16 -0400 |
| commit | cf2258322bb72a2cd868f8eaef25e9a665077f4f (patch) | |
| tree | f7a9b13ef36943246377ff623ed917fa4fd08ada /src/occ_405/amec/amec_sys.h | |
| parent | ff3b5a1c08389bf766de21adcd033e3c7b86af87 (diff) | |
| download | talos-occ-cf2258322bb72a2cd868f8eaef25e9a665077f4f.tar.gz talos-occ-cf2258322bb72a2cd868f8eaef25e9a665077f4f.zip | |
Memory Power Control when entering and exiting IPS (Idle Power Save)
memory power control settings for IPS/default modes - as defined by
memory config data packet version 0x21 - are applied to memory
power control registers of all configured ports whenever the OCC
enters/exits IPS, respectively.
Change-Id: I56514bb8cbab80c6d4877edc74db96f3b011e523
RTC: 165546
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38294
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Diffstat (limited to 'src/occ_405/amec/amec_sys.h')
| -rwxr-xr-x | src/occ_405/amec/amec_sys.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/occ_405/amec/amec_sys.h b/src/occ_405/amec/amec_sys.h index 5759f11..66d1b84 100755 --- a/src/occ_405/amec/amec_sys.h +++ b/src/occ_405/amec/amec_sys.h @@ -389,6 +389,9 @@ typedef struct // Memory Throttle Sent Last time to DIMM Throttle Register dimm_n_value_t current_dimm_n_values[NUM_NIMBUS_MC_PAIRS][MAX_NUM_MCU_PORTS]; + + // Current Memory Power Control values (applied last through GPE1) + uint8_t current_mem_pwr_ctl; } amec_systemwide_t; |
