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| author | William Bryan <wilbryan@us.ibm.com> | 2016-04-26 21:20:00 -0500 |
|---|---|---|
| committer | William A. Bryan <wilbryan@us.ibm.com> | 2016-08-26 16:44:47 -0400 |
| commit | c184079818cd001b5fd7664ca974ee721c576522 (patch) | |
| tree | ac70f716a10c24d6ef63b7d9b4a46af8b1fe74cc /src/occ_405/amec/amec_sensors_core.h | |
| parent | 9600645dd82bfde4f5bc71ddc578bdab914efa14 (diff) | |
| download | talos-occ-c184079818cd001b5fd7664ca974ee721c576522.tar.gz talos-occ-c184079818cd001b5fd7664ca974ee721c576522.zip | |
EMPATH Sensor Counters
RTC:148388
Change-Id: Iae66cd0a73032fa908eb96a149d4163397c2e275
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/27781
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Diffstat (limited to 'src/occ_405/amec/amec_sensors_core.h')
| -rwxr-xr-x | src/occ_405/amec/amec_sensors_core.h | 18 |
1 files changed, 10 insertions, 8 deletions
diff --git a/src/occ_405/amec/amec_sensors_core.h b/src/occ_405/amec/amec_sensors_core.h index 90d6aef..4a58a89 100755 --- a/src/occ_405/amec/amec_sensors_core.h +++ b/src/occ_405/amec/amec_sensors_core.h @@ -5,7 +5,7 @@ /* */ /* OpenPOWER OnChipController Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2015 */ +/* Contributors Listed Below - COPYRIGHT 2011,2016 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -38,13 +38,15 @@ /*----------------------------------------------------------------------------*/ /* Defines/Constants */ /*----------------------------------------------------------------------------*/ -// See bit definition of PM State History Register for OCC -#define OCC_PM_STATE_MASK 0x1F000000 //Mask bits 0:2 of the register -#define OCC_PAST_FAST_SLEEP 0x18000000 //Core has been in fast sleep -#define OCC_PAST_DEEP_SLEEP 0x1C000000 //Core has been in deep sleep -#define OCC_PAST_FAST_WINKLE 0x1E000000 //Core has been in fast winkle -#define OCC_PAST_DEEP_WINKLE 0x1F000000 //Core has been in deep winkle -#define OCC_PAST_CORE_CLK_STOP 0x08000000 //Core has been in an idle state with core clocks stopped +// See bit definition of OCC Stop State History Register +#define OCC_CORE_STOP_GATED 0x80000000 // Set upon entry stop entry transition (or initial power on) + // Not cleared until core is fully accessible +#define OCC_CORE_SWUP_DONE 0x40000000 // Special wake-up done +#define OCC_CORE_ACT_STOP_LVL 0x00F00000 // Actual stop level (probably changes too fast to be useful) +// The following clear upon reading +#define OCC_DEEPEST_REQ_STOP_LVL 0x000F0000 // Deepest requestest stop level +#define OCC_DEEPEST_ACT_STOP_LVL 0x0000F000 // Deepest stop state fully entered +#define OCC_IVRM_ENABLED_HIST 0x00000800 // Bit indicating if IVRM has been enabled /*----------------------------------------------------------------------------*/ /* Structures */ |
