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| author | William Bryan <wilbryan@us.ibm.com> | 2018-01-03 12:30:29 -0600 |
|---|---|---|
| committer | William A. Bryan <wilbryan@us.ibm.com> | 2018-03-27 11:57:42 -0400 |
| commit | bd605ba0a030b3490f0edebd8fb704722b6eab0d (patch) | |
| tree | 34fc7b10f06fef7baf9d101f78b816a6129753d8 /src/occ_405/amec/amec_analytics.c | |
| parent | c8538f3c894d5f28f688f7a081507c3ef14d6c24 (diff) | |
| download | talos-occ-bd605ba0a030b3490f0edebd8fb704722b6eab0d.tar.gz talos-occ-bd605ba0a030b3490f0edebd8fb704722b6eab0d.zip | |
Memory Throttle Sensors
RTC:131184
Change-Id: I2582a1eb9d599f700182f17047cc95accad03725
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/51407
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/occ_405/amec/amec_analytics.c')
| -rwxr-xr-x | src/occ_405/amec/amec_analytics.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/occ_405/amec/amec_analytics.c b/src/occ_405/amec/amec_analytics.c index 9cca40d..d715a72 100755 --- a/src/occ_405/amec/amec_analytics.c +++ b/src/occ_405/amec/amec_analytics.c @@ -5,7 +5,7 @@ /* */ /* OpenPOWER OnChipController Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2011,2016 */ +/* Contributors Listed Below - COPYRIGHT 2011,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -307,13 +307,13 @@ void amec_analytics_main(void) for (j=0; j<8; j++) // Group 45 supports all 8 Centaurs per OCC { g_amec->g44_avg[(i*MSA)+l] = g_amec->g44_avg[(i*MSA)+l] + - (UINT32)(g_amec->proc[i].memctl[j].mrd2ms.sample/78); // memory read bandwidth + (UINT32)(g_amec->proc[i].memctl[j].mrd.sample/78); // memory read bandwidth l=l+1; } for (j=0; j<8; j++) // Group 45 supports all 8 Centaurs per OCC { g_amec->g44_avg[(i*MSA)+l] = g_amec->g44_avg[(i*MSA)+l] + - (UINT32)(g_amec->proc[i].memctl[j].mwr2ms.sample/78); // memory write bandwidth + (UINT32)(g_amec->proc[i].memctl[j].mwr.sample/78); // memory write bandwidth l=l+1; } |
