Changes For P9 Enablement

Change-Id: I37e8174bcc6e99f602a66cff077ef41ad889b19c
RTC:165351
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/34949
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>

3 files changed, 24 insertions, 17 deletions

diff --git a/src/occBootLoader/bootInit.S b/src/occBootLoader/bootInit.S
index d7fe632..9b90143 100755
--- a/src/occBootLoader/bootInit.S
+++ b/src/occBootLoader/bootInit.S
@@ -5,8 +5,7 @@
 #
 # OpenPOWER OnChipController Project
 #
-# Contributors Listed Below - COPYRIGHT 2011,2014
-# [+] Google Inc.
+# Contributors Listed Below - COPYRIGHT 2011,2017
 # [+] International Business Machines Corp.
 #
 #
@@ -14,7 +13,7 @@
 # you may not use this file except in compliance with the License.
 # You may obtain a copy of the License at
 #
-# http://www.apache.org/licenses/LICENSE-2.0
+#     http://www.apache.org/licenses/LICENSE-2.0
 #
 # Unless required by applicable law or agreed to in writing, software
 # distributed under the License is distributed on an "AS IS" BASIS,
@@ -47,9 +46,9 @@
 __boot_low_level_init:
 
 # enable machine check exception
-# initialize exception vector prefix to zero
+# initialize exception vector prefix to 0x80000000
 # enable machine check (19th bit)
-li      %r3, 0
+addis   %r3, 0, 0x8000
 mtevpr  %r3
 _liwa   %r4, MACHINE_CHECK_ENABLE
 mtmsr   %r4
diff --git a/src/occBootLoader/bootMain.c b/src/occBootLoader/bootMain.c
index 15d12fa..a50f5ea 100755
--- a/src/occBootLoader/bootMain.c
+++ b/src/occBootLoader/bootMain.c
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -61,7 +61,7 @@ IMAGE_HEADER(G_bootImageHdr,__boot_low_level_init,BOOT_LOADER_ID,
 // Function Prototypes
 //*************************************************************************
 //Forward declaration
-uint32_t boot_test_sram();
+uint32_t boot_test_sram(uint32_t i_start, uint32_t i_end);
 uint32_t boot_load_405(const imageHdr_t *i_hdrAddr);
 uint32_t boot_load_gpe0(uint32_t i_startAddr, uint32_t i_size, uint8_t * i_srcPtr);
 uint32_t boot_load_gpe1(uint32_t i_startAddr, uint32_t i_size, uint8_t * i_srcPtr);
@@ -93,15 +93,23 @@ void main()
 
 #ifndef VPO
     // This is ifdef'd out b/c it takes too long to run in VPO
-    // Test SRAM
-    l_rc = boot_test_sram();
-#endif
+
+    // Only test GPE0/GPE1/405 SRAM because SGPE and PGPE are
+    // loaded before us.
 
     // If failed to test SRAM, write failed return code to SPRG1 and halt
+    l_rc = boot_test_sram(SRAM_START_ADDRESS_GPE0, SRAM_END_ADDRESS_GPE1);
+    if(0 != l_rc)
+    {
+        WRITE_TO_SPRG1_AND_HALT(l_rc);
+    }
+
+    l_rc = boot_test_sram(SRAM_START_ADDRESS_405, SRAM_END_ADDRESS_405);
     if(0 != l_rc)
     {
         WRITE_TO_SPRG1_AND_HALT(l_rc);
     }
+#endif
 
     // set imageHdr_t pointer to point to boot image header to get to boot
     // image size. This way we can get to main application image header.
@@ -410,26 +418,26 @@ uint32_t boot_load_gpe1(uint32_t i_startAddr, uint32_t i_size, uint8_t * i_srcPt
 //
 // End Function Specification
 
-uint32_t boot_test_sram()
+uint32_t boot_test_sram(uint32_t i_start, uint32_t i_end)
 {
     uint32_t l_rc = 0;
 
     // Point start to SRAM start address
-    uint32_t *l_startPtr = (uint32_t *)SRAM_TEST_START_ADDRESS;
+    uint32_t *l_startPtr = (uint32_t *) i_start;
 
     // Copy bit pattern from start until SRAM end address
-    while((uint32_t)l_startPtr < SRAM_TEST_END_ADDRESS)
+    while((uint32_t)l_startPtr < i_end)
     {
         *l_startPtr = SRAM_TEST_BIT_PATTERN;
         l_startPtr++;
     }
 
     // Reset start pointer to point to SRAM start Address
-    l_startPtr = (uint32_t *)SRAM_TEST_START_ADDRESS;
+    l_startPtr = (uint32_t *) i_start;
 
     //Read and verify bit pattern that was written. If pattern does not match,
     // return address that failed to match the pattern.
-    while((uint32_t)l_startPtr < SRAM_TEST_END_ADDRESS)
+    while((uint32_t)l_startPtr < i_end)
     {
         if((*l_startPtr) != SRAM_TEST_BIT_PATTERN)
         {
diff --git a/src/occBootLoader/bootMain.h b/src/occBootLoader/bootMain.h
index f56aa8f..78862b2 100755
--- a/src/occBootLoader/bootMain.h
+++ b/src/occBootLoader/bootMain.h
@@ -5,7 +5,7 @@
 /*                                                                        */
 /* OpenPOWER OnChipController Project                                     */
 /*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2014,2016                        */
+/* Contributors Listed Below - COPYRIGHT 2014,2017                        */
 /* [+] International Business Machines Corp.                              */
 /*                                                                        */
 /*                                                                        */
@@ -45,7 +45,7 @@
 // Defines/Enums
 //*************************************************************************/
 #define MACHINE_CHECK_ENABLE        0x00001000
-#define DATA_CACHE_BLOCK_ENABLE     0x00008000
+#define DATA_CACHE_BLOCK_ENABLE     0x80000000
 #define DATA_CACHE_BLOCK_ADDR       0x00000000
 #define DATA_CACHE_SIZE             (16 * 1024)
 #define CACHE_LINE_SIZE             32