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author | Stephan Broyles <sbroyles@us.ibm.com> | 2014-11-05 19:09:37 -0600 |
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committer | Stephan Broyles <sbroyles@us.ibm.com> | 2014-11-05 19:22:32 -0600 |
commit | 9976c207cdb20871880bd2f4cf123cf4cb6a8b0f (patch) | |
tree | 1cf9ed8f23085e6fe3e0e6046fc30dcb7e02ccf2 /src/occ/occ_sys_config.c | |
parent | 2f8ce357b89d361b5091d88aea91416011b73ccb (diff) | |
download | talos-occ-9976c207cdb20871880bd2f4cf123cf4cb6a8b0f.tar.gz talos-occ-9976c207cdb20871880bd2f4cf123cf4cb6a8b0f.zip |
Added remaining occ files.
Change-Id: I91a748d3dcf3161a6a3eedcb376fcaf1e4dfe655
Diffstat (limited to 'src/occ/occ_sys_config.c')
-rwxr-xr-x | src/occ/occ_sys_config.c | 516 |
1 files changed, 516 insertions, 0 deletions
diff --git a/src/occ/occ_sys_config.c b/src/occ/occ_sys_config.c new file mode 100755 index 0000000..091ebad --- /dev/null +++ b/src/occ/occ_sys_config.c @@ -0,0 +1,516 @@ +/****************************************************************************** +// @file occ_sys_config.c +// @brief OCC System Configuration Variable Declaration & Initialization +*/ +/****************************************************************************** + * + * @page ChangeLogs Change Logs + * @section occ_sys_config.c OCC_SYS_CONFIG.C + * @verbatim + * + * Flag Def/Fea Userid Date Description + * ------- ---------- -------- ---------- ---------------------------------- + * @th000 thallet 09/14/2011 Added SysConfig Initialization + * @rc002 rickylie 02/02/2012 Remove unused DPSS function + * @rc003 rickylie 02/03/2012 Verify & Clean Up OCC Headers & Comments + * @th00b thallet 02/29/2012 Changed APSS ADC config to match spec + * @pb00E pbavari 03/11/2012 Added correct include file + * @th010 thallet 07/11/2012 Pstate Enablement + * @th014 thallet 08/02/2012 Moved default PstateSS occ_sys_config + * @th019 853007 thallet 09/12/2012 Power Sensors + * @th022 thallet 10/03/2012 Dcom State/Mode changes + * @at010 859992 alvinwan 11/07/2012 Added oversubscription feature + * @th034 879027 thallet 04/18/2013 Broadcast critical power over PBAX + * @at013 878755 alvinwan 04/17/2013 OCC power capping implementation + * @th032 thallet 04/26/2013 Tuleta HW Bringup + * @th035 881654 thallet 05/06/2013 Tuleta Bringup Pstate Fixes + * @at014 882077 alvinwan 05/09/2013 Support APSS and System Config data from TMGT + * @ly007 882183 lychen 05/21/2013 Send APSS and System Configuration commands to OCC + * @th040 887069 thallet 06/11/2013 Support Nom & FFO Freq Setting for Mnfg + * @fk001 879727 fmkassem 04/16/2013 OCC powercap support. + * @th041 887658 thallet 06/17/2013 OCC default FFO Freq should be 0 + * @jh004 889884 joshych 07/24/2013 Support CPM param and updated frequency packet + * @ly008 894646 lychen 08/08/2013 Fix bugs in OCC handling of APSS tables for Brazos/Orlena + * @gm012 905097 milesg 10/31/2013 support mem throttle & mem config packets + * @fk002 905632 fmkassem 11/05/2013 Remove CriticalPathMonitor code + * @gs026 915840 gjsilva 02/13/2014 Support for Nvidia GPU power measurement + * + * @endverbatim + * + *///*************************************************************************/ + +//************************************************************************* +// Includes +//************************************************************************* +//@pb00Ec - changed from common.h to occ_common.h for ODE support +#include <occ_common.h> +#include <common_types.h> +#include <occ_sys_config.h> + +//************************************************************************* +// Externs +//************************************************************************* + +//************************************************************************* +// Macros +//************************************************************************* + +//************************************************************************* +// Defines/Enums +//************************************************************************* +// ----------------------------------------------------------- +// SysConfig Section Defines +// ----------------------------------------------------------- +#define SYSCFG_DEFAULT_VERSION 0xff + +// ----------------------------------------------------------- +// APSS Section Defines +// ----------------------------------------------------------- +#define SYSCFG_ADC_1x_MULT 1000 + +// @rc002 - Remove unused DPSS Section Defines + +// ----------------------------------------------------------- +// Master/Slave Section Defines +// ----------------------------------------------------------- +#define SYSCFG_MASTER_CAPABLE_000 0x01 +#define SYSCFG_DEFAULT_MASTER_000 0x00 +#define SYSCFG_ALL_OCCS_PRESENT 0xff +#define SYSCFG_ZERO_OCCS_PRESENT 0x00 + +//************************************************************************* +// Structures +//************************************************************************* + +//************************************************************************* +// Globals +//************************************************************************* +// OCC System Configuration Data +// +// We will initialize everything to default values, so in that case that we +// can't read the data from mainstore, we will still be able to *do something* +// instead of crash. +occSysConfigData_t G_sysConfigData = +{ + .version = SYSCFG_DEFAULT_VERSION, + .debug_reserved = {0}, + + // ----------------------------------------------------------- + // System Configuration Section Initializations + // ----------------------------------------------------------- + .sys_num_proc_present = 4, //TODO: placeholder //fk001a + + // ----------------------------------------------------------- + // System maximum frequencies (in MHz) for each mode + // ----------------------------------------------------------- + .sys_mode_freq.table = { + [OCC_MODE_NOMINAL] 3500, + [OCC_MODE_TURBO] 3700, + [OCC_MODE_PWRSAVE] 3000, + [OCC_MODE_MIN_FREQUENCY] 2575, + [OCC_MODE_FFO] 0, + }, + + // ----------------------------------------------------------- + // APSS Section Initializations + // ----------------------------------------------------------- + .apss_cal = { + [0] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [1] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [2] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [3] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [4] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [5] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [6] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [7] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [8] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [9] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [10] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [11] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [12] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [13] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [14] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + [15] {.gain = SYSCFG_ADC_1x_MULT, .offset = 0 , .gnd_select = 0}, + }, + + .apss_gpio_map = { + .fans_watchdog_error = SYSCFG_INVALID_PIN, + .fans_full_speed = SYSCFG_INVALID_PIN, + .fans_error = SYSCFG_INVALID_PIN, + .fans_reserved = SYSCFG_INVALID_PIN, + .vr_fan[0] = SYSCFG_INVALID_PIN, + .vr_fan[1] = SYSCFG_INVALID_PIN, + .vr_fan[2] = SYSCFG_INVALID_PIN, + .vr_fan[3] = SYSCFG_INVALID_PIN, + // @ly007a - start + .cent_en_vcache[0] = SYSCFG_INVALID_PIN, + .cent_en_vcache[1] = SYSCFG_INVALID_PIN, + .cent_en_vcache[2] = SYSCFG_INVALID_PIN, + .cent_en_vcache[3] = SYSCFG_INVALID_PIN, + .cme_throttle_n = SYSCFG_INVALID_PIN, + .gnd_oc_n = SYSCFG_INVALID_PIN, + .dom_oc_latch[0] = SYSCFG_INVALID_PIN, + .dom_oc_latch[1] = SYSCFG_INVALID_PIN, + .dom_oc_latch[2] = SYSCFG_INVALID_PIN, + .dom_oc_latch[3] = SYSCFG_INVALID_PIN, + // @ly007a - end + }, + + .apss_adc_map = { + .memory[0] = SYSCFG_INVALID_ADC_CHAN, + .memory[1] = SYSCFG_INVALID_ADC_CHAN, + .memory[2] = SYSCFG_INVALID_ADC_CHAN, + .memory[3] = SYSCFG_INVALID_ADC_CHAN, + .vdd[0] = SYSCFG_INVALID_ADC_CHAN, + .vdd[1] = SYSCFG_INVALID_ADC_CHAN, + .vdd[2] = SYSCFG_INVALID_ADC_CHAN, + .vdd[3] = SYSCFG_INVALID_ADC_CHAN, + .io[0] = SYSCFG_INVALID_ADC_CHAN, + .io[1] = SYSCFG_INVALID_ADC_CHAN, + .io[2] = SYSCFG_INVALID_ADC_CHAN, + .fans[0] = SYSCFG_INVALID_ADC_CHAN, + .fans[1] = SYSCFG_INVALID_ADC_CHAN, + .storage_media[0] = SYSCFG_INVALID_ADC_CHAN, + .storage_media[1] = SYSCFG_INVALID_ADC_CHAN, + .vcs_vio_vpcie[0] = SYSCFG_INVALID_ADC_CHAN, + .vcs_vio_vpcie[1] = SYSCFG_INVALID_ADC_CHAN, + .vcs_vio_vpcie[2] = SYSCFG_INVALID_ADC_CHAN, + .vcs_vio_vpcie[3] = SYSCFG_INVALID_ADC_CHAN, + .total_current_12v = SYSCFG_INVALID_ADC_CHAN, + .sense_12v = SYSCFG_INVALID_ADC_CHAN, + .remote_gnd = SYSCFG_INVALID_ADC_CHAN, + .mem_cache = SYSCFG_INVALID_ADC_CHAN, // @ly008a + .gpu = SYSCFG_INVALID_ADC_CHAN, + }, + + .apssGpioPortsMode = {0, 0}, + + // ----------------------------------------------------------- + // Power Cap Initializations + // ----------------------------------------------------------- + .pcap = { + .current_pcap = 0, + .soft_min_pcap = 0, + .hard_min_pcap = 0, + .max_pcap = 0, + .oversub_pcap = 0, + .system_pcap = 0, + .unthrottle = 0, + }, // @th034 + + // ----------------------------------------------------------- + // Master/Slave Section Initializations + // ----------------------------------------------------------- + .pob2pbax_chip = {0,1,2,3,4,5,6,7}, + .pob2pbax_node = {0,1,2,3}, + + .is_occ_present = SYSCFG_ZERO_OCCS_PRESENT, + + .master_config = { + .is_master_capable = SYSCFG_MASTER_CAPABLE_000, + .default_master = SYSCFG_DEFAULT_MASTER_000, + }, + + // ----------------------------------------------------------- + // Oversubscription Initializations + // ----------------------------------------------------------- + .failsafe_enabled = FALSE, // @at010a + + //Master ppb_fmax calculated by Master OCC's slave. + .master_ppb_fmax = 0xFFFF, // @fk001a + + // ----------------------------------------------------------- + // Centaur/Dimm HUID initializations + // ----------------------------------------------------------- + .centaur_huids = {0}, + .dimm_huids = {{0},{0},{0},{0},{0},{0},{0},{0}}, + + // ----------------------------------------------------------- + // Memory Throttle Limits + // ----------------------------------------------------------- + .mem_throt_limits = {{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}},{{0},{0}}}, +}; + + +// OCC Module Configuration Data +// +// We will initialize everything to default values, so in that case that we +// can't read the data from mainstore, we will still be able to *do something* +// instead of crash. +occModuleConfigData_t G_occModuleConfigData = { + 0 // @th010 - Removed un-needed Pstate Table from this structure +}; + + +// OCC Default PstateSuperStructure +// +// Default Pstate table, so that for testing we don't have to have TMGT +// send one to us. Placing this in this file because it is necessary +// configuration data for OCC to go to active state. +// +// This array was created with xxd -i pss.bin +// +// This can be removed or ifdef'd out to save space in the future. +const unsigned char G_defaultOccPstateSuperStructure[] = { + 0x50, 0x53, 0x54, 0x41, 0x54, 0x45, 0x30, 0x31, 0x6e, 0x5e, 0x34, 0x44, + 0x24, 0x34, 0x00, 0xf3, 0x6d, 0x5d, 0x34, 0x44, 0x24, 0x34, 0x00, 0x9f, + 0x6c, 0x5c, 0x35, 0x45, 0x25, 0x35, 0x00, 0x22, 0x6b, 0x5b, 0x36, 0x46, + 0x26, 0x36, 0x00, 0x7b, 0x6a, 0x5a, 0x37, 0x47, 0x27, 0x37, 0x00, 0xc6, + 0x6a, 0x5a, 0x38, 0x48, 0x28, 0x38, 0x00, 0xe4, 0x69, 0x59, 0x38, 0x48, + 0x28, 0x38, 0x00, 0x88, 0x68, 0x58, 0x39, 0x49, 0x29, 0x39, 0x00, 0x35, + 0x67, 0x57, 0x3a, 0x4a, 0x2a, 0x3a, 0x00, 0xe2, 0x66, 0x56, 0x3b, 0x4b, + 0x2b, 0x3b, 0x00, 0x5f, 0x65, 0x56, 0x3c, 0x4c, 0x2c, 0x3c, 0x00, 0x7e, + 0x64, 0x55, 0x3d, 0x4c, 0x2d, 0x3c, 0x00, 0x8c, 0x63, 0x54, 0x3e, 0x4d, + 0x2e, 0x3d, 0x00, 0x89, 0x62, 0x53, 0x3f, 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+// +pcap_config_data_t G_master_pcap_data = +{ + .current_pcap = 0, + .soft_min_pcap = 0, + .hard_min_pcap = 0, + .max_pcap = 0, + .oversub_pcap = 0, + .system_pcap = 0, + .unthrottle = 0, + .pcap_data_count = 0, +}; +// TODO: Move this to a different file +uint16_t G_conn_oc_pins_bitmap = 0x0000; + +//************************************************************************* +// Function Prototypes +//************************************************************************* + +//************************************************************************* +// Functions +//************************************************************************* + +// Function Specification +// +// Name: sysConfigFspLess +// +// Description: Since we can have a OCC Simulation in Simics without +// having a FSP, we need to have a way for OCC to automatically +// set itself up the way FSP would. This is done via default +// config data, and this function. +// +// Flow: --/--/-- FN=sysConfigFspLess +// +// End Function Specification +#ifdef FSPLESS_SIMICS + +#include "cmdh_fsp_cmds_datacnfg.h" +#include "dcom.h" +#include "state.h" +#include "mode.h" + +void sysConfigFspLess(void) +{ + // ---------------------------------------------------- + // Set OCC Role based on Config Data + // ---------------------------------------------------- + if( G_pob_id.chip_id == G_sysConfigData.master_config.default_master ) + { + G_occ_role = OCC_MASTER; + + // Run master initializations if we just became master + extern void master_occ_init(void); + master_occ_init(); + + // Turn off anything slave related since we are a master + rtl_clr_run_mask_deferred(RTL_FLAG_NOTMSTR); + rtl_set_run_mask_deferred(RTL_FLAG_MSTR); + + // Set Final Mode & State. OCC will transition through as + // all requirements for state/mode become available. + G_occ_external_req_state = OCC_STATE_ACTIVE; + G_occ_external_req_mode = OCC_MODE_NOMINAL; + } + else + { + G_occ_role = OCC_SLAVE; + + // Turn off anything master related since we are a slave + rtl_clr_run_mask_deferred(RTL_FLAG_MSTR); + rtl_set_run_mask_deferred(RTL_FLAG_NOTMSTR); + } + + // Trace our current fspless role + if(OCC_MASTER == G_occ_role){ + TRAC_IMP("Our current FspLess role: Master"); + } + else{ + TRAC_IMP("Our current FspLess role: Slave"); + } + + // ---------------------------------------------------- + // Mark available all data we have hardcoded and + // correctly initialized. + // ---------------------------------------------------- + extern data_cnfg_t * G_data_cnfg; + G_data_cnfg->data_mask = ( DATA_MASK_PSTATE_SUPERSTRUCTURE + | DATA_MASK_FREQ_PRESENT + | DATA_MASK_SET_ROLE + | DATA_MASK_APSS_CONFIG + | DATA_MASK_PCAP_PRESENT ); // @at013a + + // Install the Pstate Table + proc_gpsm_pstate_initialize((PstateSuperStructure*) G_defaultOccPstateSuperStructure); + +} + +#endif + |