Characterization state, new state transitions and Active to Observation state

Support for new characterization state changes used by manufacturing.
Observation state and new characterization state.
Details in version 0.10 OCC Interface Specifications.

Change-Id: I2ff0fc9327ad75e54c0a47cf42946e58f387522b
RTC: 163268
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/35517
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Andres A. Lugo-Reyes <aalugore@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>

1 files changed, 26 insertions, 27 deletions

diff --git a/src/include/pstate_pgpe_occ_api.h b/src/include/pstate_pgpe_occ_api.h
index 0b0415e..e1c18f9 100644
--- a/src/include/pstate_pgpe_occ_api.h
+++ b/src/include/pstate_pgpe_occ_api.h
@@ -1,25 +1,19 @@
 /* IBM_PROLOG_BEGIN_TAG                                                   */
 /* This is an automatically generated prolog.                             */
 /*                                                                        */
-/* $Source: src/include/pstate_pgpe_occ_api.h $                           */
+/* $Source: chips/p9/common/pmlib/include/pstate_pgpe_occ_api.h $         */
 /*                                                                        */
-/* OpenPOWER OnChipController Project                                     */
-/*                                                                        */
-/* Contributors Listed Below - COPYRIGHT 2016                             */
-/* [+] International Business Machines Corp.                              */
+/* IBM CONFIDENTIAL                                                       */
 /*                                                                        */
+/* EKB Project                                                            */
 /*                                                                        */
-/* Licensed under the Apache License, Version 2.0 (the "License");        */
-/* you may not use this file except in compliance with the License.       */
-/* You may obtain a copy of the License at                                */
+/* COPYRIGHT 2015,2017                                                    */
+/* [+] International Business Machines Corp.                              */
 /*                                                                        */
-/*     http://www.apache.org/licenses/LICENSE-2.0                         */
 /*                                                                        */
-/* Unless required by applicable law or agreed to in writing, software    */
-/* distributed under the License is distributed on an "AS IS" BASIS,      */
-/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
-/* implied. See the License for the specific language governing           */
-/* permissions and limitations under the License.                         */
+/* The source code for this program is not published or otherwise         */
+/* divested of its trade secrets, irrespective of what has been           */
+/* deposited with the U.S. Copyright Office.                              */
 /*                                                                        */
 /* IBM_PROLOG_END_TAG                                                     */
 /// @file  p9_pstates_pgpe_occ_api.h
@@ -41,9 +35,6 @@
 extern "C" {
 #endif
 
-// Maximum Number of Quads supported
-#define MAX_QUADS 6
-
 
 //---------------
 // IPC from 405
@@ -62,11 +53,19 @@ enum MESSAGE_ID_IPI2HI
 //
 // Return Codes
 //
-#define PGPE_RC_SUCCESS                 0x01
-#define PGPE_WOF_RC_NOT_ENABLED         0x10
+//\todo
+//Get feedback from Martha and Greg on these return codes
+//
+#define PGPE_RC_SUCCESS                         0x01
+#define PGPE_WOF_RC_NOT_ENABLED                 0x10
+#define PGPE_RC_PSTATES_DISABLED                0x11
+#define PGPE_RC_REQ_PSTATE_ALREADY_STARTED      0x12
+#define PGPE_RC_REQ_PSTATE_ALREADY_SUSPENDED    0x13
+#define PGPE_RC_OCC_NOT_PMCR_OWNER              0x14
 // Active quad mismatch with requested active quads.  PGPE did not switch
 // to using the new VFRT.  The original VFRT is still being used.
 #define PGPE_WOF_RC_VFRT_QUAD_MISMATCH  0x20
+#define PGPE_RC_REQ_WHILE_PENDING_ACK   0x21
 
 //
 // PMCR Owner
@@ -74,7 +73,8 @@ enum MESSAGE_ID_IPI2HI
 typedef enum
 {
     PMCR_OWNER_HOST         = 0,
-    PMCR_OWNER_OCC          = 1
+    PMCR_OWNER_OCC          = 1,
+    PMCR_OWNER_CHAR         = 2
 } PMCR_OWNER;
 
 
@@ -88,14 +88,14 @@ typedef struct ipcmsg_base
 // Start Suspend Actions
 //
 #define PGPE_ACTION_PSTATE_START   0
-#define PGPE_ACTION_PSTATE_SUSPEND 1
+#define PGPE_ACTION_PSTATE_STOP    1
 
-typedef struct ipcmsg_start_suspend
+typedef struct ipcmsg_start_stop
 {
     ipcmsg_base_t   msg_cb;
     uint8_t         action;
     PMCR_OWNER      pmcr_owner;
-} ipcmsg_start_suspend_t;
+} ipcmsg_start_stop_t;
 
 
 typedef struct ipcmsg_clip_update
@@ -269,9 +269,9 @@ typedef union quad_state0
         uint64_t quad1_pstate             : 8;  // Pstate of Quad 1; 0xFF indicates EQ is off
         uint64_t quad2_pstate             : 8;  // Pstate of Quad 2; 0xFF indicates EQ is off
         uint64_t quad3_pstate             : 8;  // Pstate of Quad 3; 0xFF indicates EQ is off
+        uint64_t core_poweron_state       : 16; // bit vector: 0:core0, 1:core1, ..., 15:core15
         uint64_t ivrm_state               : 4;  // ivrm state: bit vector 0:quad0, 1:quad1, 2:quad2, 3;quad3
         uint64_t ivrm_state_rsvd          : 4;
-        uint64_t core_poweron_state       : 16; // bit vector: 0:core0, 1:core1, ..., 15:core15
         uint64_t external_vrm_setpoint    : 8;  // set point in mV
     } fields;
 } quad_state0_t;
@@ -288,12 +288,11 @@ typedef union quad_state1
     {
         uint64_t quad4_pstate             : 8;  // Pstate of Quad 4; 0xFF indicates EQ is off
         uint64_t quad5_pstate             : 8;  // Pstate of Quad 5; 0xFF indicates EQ is off
-        uint64_t requested_active_quad    : 6;  // Pstate of Quad 5; 0xFF indicates EQ is off
-        uint64_t quad_pstate_rsvd         : 10;
+        uint64_t reserved                 : 16;
         uint64_t ivrm_state               : 2;  // ivrm state: bit vector 0:quad4, 1:quad5
         uint64_t ivrm_state_rsvd          : 6;
         uint64_t core_poweron_state       : 8;  // bit vector: 0:core16, 1:core17, ..., 7:core23
-        uint64_t core_poweron_state_rsvd  : 8;
+        uint64_t requested_active_quad    : 8;
         uint64_t external_vrm_setpoint    : 8;  // set point in mV
     } fields;
 } quad_state1_t;