Memory Power Control when entering and exiting IPS (Idle Power Save)

memory power control settings for IPS/default modes - as defined by
memory config data packet version 0x21 - are applied to memory
power control registers of all configured ports whenever the OCC
enters/exits IPS, respectively.

Change-Id: I56514bb8cbab80c6d4877edc74db96f3b011e523
RTC: 165546
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/38294
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
Reviewed-by: Wael El-Essawy <welessa@us.ibm.com>

5 files changed, 173 insertions, 38 deletions

diff --git a/src/common/dimm_structs.h b/src/common/dimm_structs.h
index 39ffbad..b6f11f9 100644
--- a/src/common/dimm_structs.h
+++ b/src/common/dimm_structs.h
@@ -93,42 +93,4 @@ typedef struct
     uint8_t mca;
 } reset_mem_deadman_args_t;
 
-// Base Address of NIMBUS MCA.
-#define DIMM_MCA_BASE_ADDRESS     0x07010800
-
-/*
-MC/Port Address MCA Port Address    Control Addr        SCOM Address
-mc01.port0        0x07010800        + 0x00000116        = 0x07010916
-mc01.port1        0x07010840        + 0x00000116        = 0x07010956
-mc01.port2        0x07010880        + 0x00000116        = 0x07010996
-mc01.port3        0x070108C0        + 0x00000116        = 0x070109D6
-mc23.port0        0x08010800        + 0x00000116        = 0x08010916
-mc23.port1        0x08010840        + 0x00000116        = 0x08010956
-mc23.port2        0x08010880        + 0x00000116        = 0x08010996
-mc23.port3        0x080108C0        + 0x00000116        = 0x080109D6
- */
-
-//  N/M DIMM Throttling Control SCOM Register Addresses macro
-#define N_M_DIMM_TCR(mc,port) (DIMM_MCA_BASE_ADDRESS + 0x116 + \
-                               (0x01000000 * (mc)) + ( 0x40 * (port)))
-
-/*
-MC/Port Address MCA Port Address   Deadman Offset       SCOM Address
-mc01.port0        0x07010800        + 0x0000013C        = 0x0701093C
-mc01.port1        0x07010840        + 0x0000013C        = 0x0701097C
-mc01.port2        0x07010880        + 0x0000013C        = 0x070109BC
-mc01.port3        0x070108C0        + 0x0000013C        = 0x070109FC
-mc23.port0        0x08010800        + 0x0000013C        = 0x0801093C
-mc23.port1        0x08010840        + 0x0000013C        = 0x0801097C
-mc23.port2        0x08010880        + 0x0000013C        = 0x080109BC
-mc23.port3        0x080108C0        + 0x0000013C        = 0x080109FC
- */
-
-//  NIMBUS DIMM Deadman SCOM Register Addresses macro
-#define DEADMAN_TIMER_PORT(mc,port) (DIMM_MCA_BASE_ADDRESS + 0x13C +         \
-                               (0x01000000 * (mc)) + ( 0x40 * (port)))
-
-#define DEADMAN_TIMER_MCA(mca) (DIMM_MCA_BASE_ADDRESS + 0x13C +              \
-                               (0x01000000 * (mca>>2)) + ( 0x40 * (mca&3)))
-
 #endif // _DIMM_STRUCTS_H
diff --git a/src/common/gpe_err.h b/src/common/gpe_err.h
index c759993..c4e9371 100644
--- a/src/common/gpe_err.h
+++ b/src/common/gpe_err.h
@@ -40,6 +40,9 @@
 #define GPE_RC_INVALID_STATE         0x07     // Invalid state for requested operation
 #define GPE_RC_NOT_COMPLETE          0x08     // Last operation did not complete
 
+// Memory Power Control Error
+#define GPE_RC_INVALID_MEM_PWR_CTL   0x20     // Invalid value for the memory power control command
+
 // APSS Specific gpe return Codes
 #define GPE_RC_INVALID_APSS_MODE     0x40     // OCC requested undefined APSS mode
 
@@ -47,4 +50,5 @@
 #define GPE_RC_GET_CORE_DATA_FAILED  0x60     // Failed to collect core data
 #define GPE_RC_GET_NEST_DTS_FAILED   0x61     // Failed to collect nest DTS temperatures
 
+
 #endif //_GPE_ERR_H
diff --git a/src/common/ipc_func_ids.h b/src/common/ipc_func_ids.h
index 6d732d8..ef0ae31 100644
--- a/src/common/ipc_func_ids.h
+++ b/src/common/ipc_func_ids.h
@@ -69,6 +69,7 @@ IPC_FUNCIDS_TABLE_START
         IPC_FUNC_ID(IPC_ST_GPE1_NOP)
         IPC_FUNC_ID(IPC_ST_RESET_MEM_DEADMAN)
         IPC_FUNC_ID(IPC_ST_24_X_7_FUNCID)
+        IPC_FUNC_ID(IPC_ST_MEM_POWER_CONTROL_FUNCID)
     IPC_FUNCIDS_ST_END(OCCHW_INST_ID_GPE1)
 
     //Functions that are only supported by GPE2 should be defined here
diff --git a/src/common/mca_addresses.h b/src/common/mca_addresses.h
new file mode 100644
index 0000000..2a2f78a
--- /dev/null
+++ b/src/common/mca_addresses.h
@@ -0,0 +1,113 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/common/mca_addresses.h $                                  */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2015,2017                        */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+#ifndef _MCA_ADDRESSES_H
+#define _MCA_ADDRESSES_H
+
+#define NUM_NIMBUS_MC_PAIRS 2
+#define MAX_NUM_MCU_PORTS   4
+
+// Base Address of NIMBUS MCA.
+#define DIMM_MCA_BASE_ADDRESS     0x07010800
+
+#define MCA_MCPAIR_SPACE          0x01000000
+#define MCA_PORT_SPACE            0x40
+#define MC_PORT_SPACE(mc,port)    ((MCA_MCPAIR_SPACE * (mc)) + ( MCA_PORT_SPACE * (port)))
+
+
+#define POWER_CTRL_REG0_OFFSET    0x0134
+#define POWER_CTRL_REG0_ADDRESS   (DIMM_MCA_BASE_ADDRESS + POWER_CTRL_REG0_OFFSET)
+
+#define STR_REG0_OFFSET           0x0135
+#define STR_REG0_ADDRESS          (DIMM_MCA_BASE_ADDRESS + STR_REG0_OFFSET)
+
+
+#define N_M_TCR_OFFSET            0x0116
+#define N_M_TCR_ADDRESS           (DIMM_MCA_BASE_ADDRESS + N_M_TCR_OFFSET)
+
+
+#define DEADMAN_TIMER_OFFSET      0x013C
+#define DEADMAN_TIMER_ADDRESS     (DIMM_MCA_BASE_ADDRESS + DEADMAN_TIMER_OFFSET)
+
+
+// Memory Power Control
+
+//Power Control Register 0 and STR Register 0 there are 4 each (1 per MCU port)
+//OCC knows present MCU ports from the memory throttle config packet
+
+//Power control reg 0:  MCP.PORT#.SRQ.PC.MBARPC0Q
+//STR reg 0:            MCP.PORT#.SRQ.PC.MBASTR0Q
+
+/*                                 PWR_CTRL/STR REG   Power Ctl reg 0     STR reg 0
+MC/Port Address MCA Port Address    Control Addr       SCOM Address     SCOM Address
+mc01.port0        0x07010800        + 0x00000134/5     = 0x07010934     = 0x07010935
+mc01.port1        0x07010840        + 0x00000134/5     = 0x07010974     = 0x07010975
+mc01.port2        0x07010880        + 0x00000134/5     = 0x070109B4     = 0x070109B5
+mc01.port3        0x070108C0        + 0x00000134/5     = 0x070109F4     = 0x070109F5
+mc23.port0        0x08010800        + 0x00000134/5     = 0x08010934     = 0x08010935
+mc23.port1        0x08010840        + 0x00000134/5     = 0x08010974     = 0x08010975
+mc23.port2        0x08010880        + 0x00000134/5     = 0x080109B4     = 0x080109B5
+mc23.port3        0x080108C0        + 0x00000134/5     = 0x080109F4     = 0x080109F5
+ */
+
+#define POWER_CTRL_REG0(mc,port) (POWER_CTRL_REG0_ADDRESS + MC_PORT_SPACE(mc,port))
+
+#define STR_REG0(mc,port) (STR_REG0_ADDRESS + MC_PORT_SPACE(mc,port))
+
+
+// DIMM Control
+/*
+MC/Port Address MCA Port Address    Control Addr        SCOM Address
+mc01.port0        0x07010800        + 0x00000116        = 0x07010916
+mc01.port1        0x07010840        + 0x00000116        = 0x07010956
+mc01.port2        0x07010880        + 0x00000116        = 0x07010996
+mc01.port3        0x070108C0        + 0x00000116        = 0x070109D6
+mc23.port0        0x08010800        + 0x00000116        = 0x08010916
+mc23.port1        0x08010840        + 0x00000116        = 0x08010956
+mc23.port2        0x08010880        + 0x00000116        = 0x08010996
+mc23.port3        0x080108C0        + 0x00000116        = 0x080109D6
+ */
+
+//  N/M DIMM Throttling Control SCOM Register Addresses macro
+#define N_M_DIMM_TCR(mc,port) (N_M_TCR_ADDRESS + MC_PORT_SPACE(mc,port))
+
+/*
+MC/Port Address MCA Port Address   Deadman Offset       SCOM Address
+mc01.port0        0x07010800        + 0x0000013C        = 0x0701093C
+mc01.port1        0x07010840        + 0x0000013C        = 0x0701097C
+mc01.port2        0x07010880        + 0x0000013C        = 0x070109BC
+mc01.port3        0x070108C0        + 0x0000013C        = 0x070109FC
+mc23.port0        0x08010800        + 0x0000013C        = 0x0801093C
+mc23.port1        0x08010840        + 0x0000013C        = 0x0801097C
+mc23.port2        0x08010880        + 0x0000013C        = 0x080109BC
+mc23.port3        0x080108C0        + 0x0000013C        = 0x080109FC
+ */
+
+//  NIMBUS DIMM Deadman SCOM Register Addresses macro
+#define DEADMAN_TIMER_PORT(mc,port) (DEADMAN_TIMER_ADDRESS +  MC_PORT_SPACE(mc,port))
+
+#define DEADMAN_TIMER_MCA(mca) (DEADMAN_TIMER_ADDRESS + MC_PORT_SPACE((mca>>2),(mca&3)))
+
+#endif // _MCA_ADDRESSES_H
diff --git a/src/common/mem_structs.h b/src/common/mem_structs.h
new file mode 100644
index 0000000..a7d266e
--- /dev/null
+++ b/src/common/mem_structs.h
@@ -0,0 +1,55 @@
+/* IBM_PROLOG_BEGIN_TAG                                                   */
+/* This is an automatically generated prolog.                             */
+/*                                                                        */
+/* $Source: src/dimm_structs.h $                                          */
+/*                                                                        */
+/* OpenPOWER OnChipController Project                                     */
+/*                                                                        */
+/* Contributors Listed Below - COPYRIGHT 2016                             */
+/* [+] International Business Machines Corp.                              */
+/*                                                                        */
+/*                                                                        */
+/* Licensed under the Apache License, Version 2.0 (the "License");        */
+/* you may not use this file except in compliance with the License.       */
+/* You may obtain a copy of the License at                                */
+/*                                                                        */
+/*     http://www.apache.org/licenses/LICENSE-2.0                         */
+/*                                                                        */
+/* Unless required by applicable law or agreed to in writing, software    */
+/* distributed under the License is distributed on an "AS IS" BASIS,      */
+/* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or        */
+/* implied. See the License for the specific language governing           */
+/* permissions and limitations under the License.                         */
+/*                                                                        */
+/* IBM_PROLOG_END_TAG                                                     */
+
+/* This header file is used by both occ_405 and occ_gpe1.                 */
+/* Contains common structures and globals.                                */
+
+#ifndef _MEM_STRUCTS_H
+#define _MEM_STRUCTS_H
+
+#include "occ_util.h"
+#include <gpe_export.h>
+#include "gpe_err.h"
+
+// this enum defines memory power control
+typedef enum
+{
+    MEM_PWR_CTL_OFF                  = 0x00,
+    MEM_PWR_CTL_POWER_DOWN           = 0x01,
+    MEM_PWR_CTL_PD_AND_STR           = 0x02,
+    MEM_PWR_CTL_PD_AND_STR_CLK_STOP  = 0x03,
+    MEM_PWR_CTL_NO_SUPPORT           = 0xFF,
+} eMemoryPowerControlSetting;
+
+// memory power control IPC argument
+typedef struct
+{
+    GpeErrorStruct    error;
+    uint8_t           mem_pwr_ctl;
+    uint8_t           port;
+    uint8_t           mc;
+} mem_power_control_args_t;
+
+#endif  //_MEM_STRUCTS_H