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authorDouglas Gilbert <dgilbert@us.ibm.com>2018-07-31 16:17:19 -0500
committerWilliam A. Bryan <wilbryan@us.ibm.com>2018-08-07 12:00:28 -0500
commit17d77ae94197cc72f11e084d68414eefca7f85d1 (patch)
treeccace90100ac1f875aed652b6703711e18fdf672 /src/common
parentc0210a3fc54db880256e1626aa753e4e9ba07995 (diff)
downloadtalos-occ-17d77ae94197cc72f11e084d68414eefca7f85d1.tar.gz
talos-occ-17d77ae94197cc72f11e084d68414eefca7f85d1.zip
Memory:MPV:STC920:Zeppelin: OCC held in reset after a channel checkstop
Change-Id: I0311ea1a8ba3051ad8e2103deba2cef84f12109b CQ:sw439732 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/63705 Reviewed-by: Martha Broyles <mbroyles@us.ibm.com> Reviewed-by: William A. Bryan <wilbryan@us.ibm.com> Tested-by: William A. Bryan <wilbryan@us.ibm.com>
Diffstat (limited to 'src/common')
-rw-r--r--src/common/centaur_configuration.h2
-rw-r--r--src/common/global_app_cfg.h2
2 files changed, 3 insertions, 1 deletions
diff --git a/src/common/centaur_configuration.h b/src/common/centaur_configuration.h
index 65b556b..46f9521 100644
--- a/src/common/centaur_configuration.h
+++ b/src/common/centaur_configuration.h
@@ -122,6 +122,8 @@ typedef struct
enum
{
// rc 1 - 7 reserved from scom rc
+ CENTAUR_ACCESS_INACTIVE = 98,
+ CENTAUR_ACCESS_IN_PROGRESS = 99,
CENTAUR_INVALID_SCOM = 100,
CENTAUR_GET_MEM_DATA_COLLECT_INVALID = 200,
CENTAUR_GET_MEM_DATA_UPDATE_INVALID = 201,
diff --git a/src/common/global_app_cfg.h b/src/common/global_app_cfg.h
index 97957e7..5dd6008 100644
--- a/src/common/global_app_cfg.h
+++ b/src/common/global_app_cfg.h
@@ -40,7 +40,7 @@
// Redefine the default MSR to mask off SIB errors and avoid data machine checks
// These SIB errors probably occur due to contention on the PIB
#define PK_THREAD_MACHINE_CONTEXT_DEFAULT (MSR_SEM | MSR_UIE | MSR_EE | MSR_ME)
-#define PPE42_MSR_INITIAL (MSR_SEM | MSR_ME)
+#define PPE42_MSR_INITIAL (MSR_SEM | MSR_ME | MSR_UIE )
// Enable GPE IPC Timers
#define GPE_IPC_TIMERS
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