diff options
author | Chris Cain <cjcain@us.ibm.com> | 2018-10-10 15:33:36 -0500 |
---|---|---|
committer | Christopher J. Cain <cjcain@us.ibm.com> | 2018-10-29 17:11:53 -0500 |
commit | 49d91f3310f2b105b19fc0d3ca1de5f1f7a5e2f0 (patch) | |
tree | 0764bd8895c7aee72e9b1b2b38a5dd644a3f7e59 | |
parent | 008cb0bc5f1acc593d73d78c712bd531c3feef00 (diff) | |
download | talos-occ-49d91f3310f2b105b19fc0d3ca1de5f1f7a5e2f0.tar.gz talos-occ-49d91f3310f2b105b19fc0d3ca1de5f1f7a5e2f0.zip |
NVDIMM procedure update
- stop mcbist
- reduce delay times to 0
- disable min power domain reduction
Misc cleanup: skip i2c lock release on non-Nimbus systems
Change-Id: If1789a562df1dca245b1eb63f5355924a042d73d
RTC: 173789
Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/67311
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
Reviewed-by: Christopher J. Cain <cjcain@us.ibm.com>
-rw-r--r-- | src/common/mca_addresses.h | 4 | ||||
-rwxr-xr-x | src/occ_405/cmdh/cmdh_fsp_cmds.c | 2 | ||||
-rwxr-xr-x | src/occ_405/dimm/dimm.c | 8 | ||||
-rwxr-xr-x | src/occ_405/occbuildname.c | 2 | ||||
-rw-r--r-- | src/occ_gpe1/gpe1_dimm_control.c | 55 |
5 files changed, 53 insertions, 18 deletions
diff --git a/src/common/mca_addresses.h b/src/common/mca_addresses.h index b3917cb..a2f4c65 100644 --- a/src/common/mca_addresses.h +++ b/src/common/mca_addresses.h @@ -171,4 +171,8 @@ mc23.port3 0x080108C0 + 0x00000100 = 0x080109C0 // NIMBUS MCA Calibration FIR SCOM Register Addresses macro #define MCA_CAL_FIR_REG_MCA(mca) (MCA_CAL_FIR_ADDRESS + MC_PORT_SPACE((mca>>2),(mca&3))) +// MCBIST Control Register: MC#.MCBIST.MBA_SCOMFIR.MCB_CNTLQ +#define MCBIST_BASE_ADDRESS 0x070123DB +#define MCBIST_CTRL_REG(mc) (MCBIST_BASE_ADDRESS + (MCA_MCPAIR_SPACE * (mc))) + #endif // _MCA_ADDRESSES_H diff --git a/src/occ_405/cmdh/cmdh_fsp_cmds.c b/src/occ_405/cmdh/cmdh_fsp_cmds.c index df7ae94..000ede9 100755 --- a/src/occ_405/cmdh/cmdh_fsp_cmds.c +++ b/src/occ_405/cmdh/cmdh_fsp_cmds.c @@ -1023,7 +1023,7 @@ errlHndl_t cmdh_clear_elog (const cmdh_fsp_cmd_t * i_cmd_ptr, l_elog_id = l_cmd_ptr->elog_id; // version 0 only supported elogs from the 405 l_elog_source = ERRL_SOURCE_405; - } + } else if( (l_data_length == CLEAR_ELOG_V1_CMD_LEN) && (l_cmd_version_ptr->version == 1) ) { diff --git a/src/occ_405/dimm/dimm.c b/src/occ_405/dimm/dimm.c index 6d7f54c..56d36dd 100755 --- a/src/occ_405/dimm/dimm.c +++ b/src/occ_405/dimm/dimm.c @@ -712,7 +712,11 @@ void disable_all_dimms() TRAC_INFO("disable_all_dimms: DIMM temp collection is being stopped"); G_mem_monitoring_allowed = false; } - occ_i2c_lock_release(G_dimm_sm_args.i2cEngine); + + if (MEM_TYPE_NIMBUS == G_sysConfigData.mem_type) + { + occ_i2c_lock_release(G_dimm_sm_args.i2cEngine); + } } // Function Specification @@ -749,7 +753,7 @@ void task_dimm_sm(struct task *i_self) #ifdef DEBUG_LOCK_TESTING SIMULATE_HOST(); #endif - if (MEM_TYPE_NIMBUS == G_sysConfigData.mem_type) + if (MEM_TYPE_NIMBUS == G_sysConfigData.mem_type) { // First handle any outstanding I2C reset diff --git a/src/occ_405/occbuildname.c b/src/occ_405/occbuildname.c index ed2d432..80b1b27 100755 --- a/src/occ_405/occbuildname.c +++ b/src/occ_405/occbuildname.c @@ -34,6 +34,6 @@ volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = #else -volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/ "op_occ_181001a\0" /*</BuildName>*/ ; +volatile const char G_occ_buildname[16] __attribute__((section(".buildname"))) = /*<BuildName>*/ "op_occ_181029a\0" /*</BuildName>*/ ; #endif diff --git a/src/occ_gpe1/gpe1_dimm_control.c b/src/occ_gpe1/gpe1_dimm_control.c index d36247f..781bcac 100644 --- a/src/occ_gpe1/gpe1_dimm_control.c +++ b/src/occ_gpe1/gpe1_dimm_control.c @@ -100,6 +100,7 @@ void gpe_scom_nvdimms_nimbus(ipc_msg_t* cmd, void* arg) int rc = 0; int mc = 0; int port = 0; + uint64_t regValue = 0; uint64_t mbarpc_regValue = 0; uint64_t mbastr_regValue = 0; ipc_async_cmd_t *async_cmd = (ipc_async_cmd_t*)cmd; @@ -115,6 +116,30 @@ void gpe_scom_nvdimms_nimbus(ipc_msg_t* cmd, void* arg) uint16_t mask = 0x8000; for (mc = 0; mc < NUM_MBAS_NIMBUS; mc++) { + const uint32_t reg_MCBIST = MCBIST_CTRL_REG(mc); + rc = getscom_abs(reg_MCBIST, ®Value); + if (rc) + { + PK_TRACE("E>gpe_scom_nvdimms_nimbus: Failed to read (MCBIST) Reg:0x%08X, rc:0x%08x", + reg_MCBIST, rc); + } + else + { + // Step 1 - In MCBIST_CTRL_REG, stop mcbist + // (must be done first) + // + // bit 1 - MCB_STOP + regValue |= 0x4000000000000000; // stop mcbist (set bit 1) + rc = putscom_abs(reg_MCBIST, regValue); + if (rc) + { + PK_TRACE("E>gpe_scom_nvdimms_nimbus: Failed to stop mcbist (MCBIST)" + " Reg:0x%08X, Data:0x%08X %08X, rc:0x%08x", + reg_MCBIST, WORD_HIGH(regValue), WORD_LOW(regValue), rc); + gpe_set_ffdc(&(args->error), reg_MCBIST, GPE_RC_SCOM_PUT_FAILED, rc); + } + } + for (port = 0; port < NUM_PORTS_PER_MBA; port++) { if (args->configured_mbas & mask) @@ -130,10 +155,10 @@ void gpe_scom_nvdimms_nimbus(ipc_msg_t* cmd, void* arg) } else { - // Step 1 - In MBARPC0Q, disable power domain control - // (must be done first, before domains are set) + // Step 2 - In MBARPC0Q, disable power domain control + // (must be done before domains are set) // - // bit 2 - power domain control, + // bit 2 - power domain control mbarpc_regValue &= 0xDFFFFFFFFFFFFFFF; // disable power control (clear bit 2) rc = putscom_abs(reg_MBARPC0Q, mbarpc_regValue); if (rc) @@ -145,13 +170,14 @@ void gpe_scom_nvdimms_nimbus(ipc_msg_t* cmd, void* arg) GPE_RC_SCOM_PUT_FAILED, rc); } - // Step 2 - In MBARPC0Q, set domain to MAXALL_MINALL(0b000), - // and enable minimum domain reduction + // Step 3 - In MBARPC0Q, set domain to MAXALL_MIN0(0b010), + // disable minimum domain reduction and set power down delay to 0 // - // bits 3:5 - min/max domains - // bit 22 - domain reduction - mbarpc_regValue &= 0xE3FFFFFFFFFFFFFF; // zero out bits 3-5 - mbarpc_regValue |= 0x0000020000000000; // set bit 22 + // bits 3:5 - min/max domains + // bit 22 - min domain reduction enable + // bit 23:32 - min domain reduction time + mbarpc_regValue &= 0xEBFFFC007FFFFFFF; // MAXALL_MIN0 & delay (clear bits 3,5,22-32) + mbarpc_regValue |= 0x0800000000000000; // MAXALL_MIN0 (set bit 4) rc = putscom_abs(reg_MBARPC0Q, mbarpc_regValue); if (rc) { @@ -162,9 +188,10 @@ void gpe_scom_nvdimms_nimbus(ipc_msg_t* cmd, void* arg) GPE_RC_SCOM_PUT_FAILED, rc); } - // Step 3 - In MBASTR0Q, enable STR entry + // Step 4 - In MBASTR0Q, enable STR entry and set entry delay to 0 // - // bit 0 - STR enable + // bit 0 - STR enable + // bit 2:11 - STR entry time const uint32_t reg_MBASTR0Q = STR_REG0(mc,port); rc = getscom_abs(reg_MBASTR0Q, &mbastr_regValue); if (rc) @@ -174,6 +201,7 @@ void gpe_scom_nvdimms_nimbus(ipc_msg_t* cmd, void* arg) } else { + mbastr_regValue &= 0xC00FFFFFFFFFFFFF; // set entry time to 0 (clear bits 2-11) mbastr_regValue |= 0x8000000000000000; // enable STR (set bit 0) rc = putscom_abs(reg_MBASTR0Q, mbastr_regValue); if (rc) @@ -186,7 +214,7 @@ void gpe_scom_nvdimms_nimbus(ipc_msg_t* cmd, void* arg) } } - // Step 4 - In MBARPC0Q, re-enable power domain control + // Step 5 - In MBARPC0Q, re-enable power domain control // // bit 2 - power domain control mbarpc_regValue |= 0x2000000000000000; // enable power control (set bit 2) @@ -218,10 +246,9 @@ void gpe_scom_nvdimms_nimbus(ipc_msg_t* cmd, void* arg) { if (args->configured_mbas & mask) { - // Step 5 - In FARB5Q (DDR Interface SCOM Control), assert ddr_resetn + // Step 6 - In FARB5Q (DDR Interface SCOM Control), assert ddr_resetn // // bit 4 - assert ddr_resetn - uint64_t regValue = 0; const uint32_t reg_FARB5Q = DDR_IF_SCOM_CTRL(mc,port); rc = getscom_abs(reg_FARB5Q, ®Value); if (rc) |