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| author | Chris Cain <cjcain@us.ibm.com> | 2017-08-15 15:23:26 -0500 |
|---|---|---|
| committer | William A. Bryan <wilbryan@us.ibm.com> | 2017-08-15 16:41:31 -0400 |
| commit | 0faa5bf44b69510065a5ddea380dc18ceea0e2a6 (patch) | |
| tree | 9d51bb0cf585ebae63cc4d268701a4ef1cee685d | |
| parent | 8a335d83ed938f05f95ca1cfdbbb5292053ed51f (diff) | |
| download | talos-occ-0faa5bf44b69510065a5ddea380dc18ceea0e2a6.tar.gz talos-occ-0faa5bf44b69510065a5ddea380dc18ceea0e2a6.zip | |
Update divisor for I2C resets to match what is used reading temps
Change-Id: I89b082eea7d23327c519ddeb6a9d473ec35341cf
Reviewed-on: http://ralgit01.raleigh.ibm.com/gerrit1/44644
Tested-by: FSP CI Jenkins <fsp-CI-jenkins+hostboot@us.ibm.com>
Reviewed-by: Martha Broyles <mbroyles@us.ibm.com>
Reviewed-by: William A. Bryan <wilbryan@us.ibm.com>
| -rw-r--r-- | src/occ_gpe1/gpe1_dimm_reset.c | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/src/occ_gpe1/gpe1_dimm_reset.c b/src/occ_gpe1/gpe1_dimm_reset.c index 0463977..161bd43 100644 --- a/src/occ_gpe1/gpe1_dimm_reset.c +++ b/src/occ_gpe1/gpe1_dimm_reset.c @@ -123,7 +123,10 @@ void dimm_reset_slave(ipc_msg_t* cmd, void* arg) // Write I2C mode register with the speed/port scomAddr = I2C_MODE_REG | SCOM_ENGINE_OFFSET(args->i2cEngine); - regValue = 0x0177000000000000; + // 0-15: Bit Rate Divisor - 0x0049 gives approx 391kHz (and allows margin for clock variation) + // 16-21: Port Number (0-5) + // 22-26: reserved (0s) + regValue = 0x0049000000000000; if ((args->i2cPort > 0) && (args->i2cPort < 6)) { regValue |= ((uint64_t)args->i2cPort << 42); |
