blob: 0d9fa220e922ed9009b8a6aca5cf3d9ffe383c0e (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
|
/**
* io.h - DesignWare USB3 DRD IO Header
*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
*
* Authors: Felipe Balbi <balbi@ti.com>,
* Sebastian Andrzej Siewior <bigeasy@linutronix.de>
*
* Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/io.h) and ported
* to uboot.
*
* commit 2c4cbe6e5a : usb: dwc3: add tracepoints to aid debugging
*
* SPDX-License-Identifier: GPL-2.0
*
*/
#ifndef __DRIVERS_USB_DWC3_IO_H
#define __DRIVERS_USB_DWC3_IO_H
#include <asm/io.h>
#define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
static inline u32 dwc3_readl(void __iomem *base, u32 offset)
{
unsigned long offs = offset - DWC3_GLOBALS_REGS_START;
u32 value;
/*
* We requested the mem region starting from the Globals address
* space, see dwc3_probe in core.c.
* However, the offsets are given starting from xHCI address space.
*/
value = readl(base + offs);
return value;
}
static inline void dwc3_writel(void __iomem *base, u32 offset, u32 value)
{
unsigned long offs = offset - DWC3_GLOBALS_REGS_START;
/*
* We requested the mem region starting from the Globals address
* space, see dwc3_probe in core.c.
* However, the offsets are given starting from xHCI address space.
*/
writel(value, base + offs);
}
static inline void dwc3_flush_cache(int addr, int length)
{
flush_dcache_range(addr, addr + ROUND(length, CACHELINE_SIZE));
}
#endif /* __DRIVERS_USB_DWC3_IO_H */
|
